CN108334299B

CN108334299B - Automatic screen expansion parameter display consistency adjusting system

Info

Publication number: CN108334299B
Application number: CN201810078640.2A
Authority: CN
Inventors: 罗春柳; 张廷银; 郭坤; 陈向前
Original assignee: Shandong Chaoyue CNC Electronics Co Ltd
Current assignee: Shandong Chaoyue CNC Electronics Co Ltd
Priority date: 2018-01-26
Filing date: 2018-01-26
Publication date: 2020-11-24
Anticipated expiration: 2038-01-26
Also published as: CN108334299A

Abstract

The invention provides a system for automatically adjusting the consistency of screen expansion parameter display, which comprises: the display device comprises a main display device, an extended display device and a display information processing unit; the display information processing unit is respectively connected with the main display device and the extended display device; the display information processing unit is used for acquiring the current display parameters of the main display device and adjusting the display parameters of the extended display device according to the current display parameters of the main display device, so that the current display parameters of the main display device and the extended display device are the same. Therefore, the display parameters of the main display device and the display parameters of the extension display device are the same, the phenomenon that the brightness and color displayed by the two screens always have large contrast is avoided, poor visual experience is brought to a user, and the vision of the user is damaged by the long-time visual contrast.

Description

Automatic screen expansion parameter display consistency adjusting system

Technical Field

The invention mainly relates to the field of display of displays, in particular to a system for automatically adjusting the display consistency of screen expansion parameters.

Background

The current screen expansion display technology is increasingly used in commercial office environments or home places, however, when an all-in-one machine and a notebook computer are connected to an expansion screen or connected to the expansion screen for display, the brightness and color display of the two screens are often in great contrast. At this time, the user needs to adjust each corresponding display parameter through manual setting, but often finds that the parameters are not satisfactory after being adjusted. Greater brightness and color contrast can lead to a poor visual experience for the user, and the visual contrast can also impair the user's vision over time.

Disclosure of Invention

In order to overcome the defects in the prior art, the invention provides a system for automatically adjusting the display consistency of screen expansion parameters, which comprises: the display device comprises a main display device, an extended display device and a display information processing unit;

the display information processing unit is respectively connected with the main display device and the extended display device;

the display information processing unit is used for acquiring the current display parameters of the main display device and adjusting the display parameters of the extended display device according to the current display parameters of the main display device, so that the current display parameters of the main display device and the extended display device are the same.

Preferably, the display parameters include: contrast, brightness, color temperature, gamma, sharpness.

Preferably, the display information processing unit includes: the device comprises a main display parameter acquisition module, a main display parameter cache module, an extended display parameter acquisition module, an extended display parameter cache module, a display parameter comparison module and an extended display control module;

the main display parameter acquisition module is used for acquiring the current display parameters of the main display device in real time and caching the acquired current main display parameters to the main display parameter caching module;

the extended display parameter acquisition module is used for acquiring the current display parameters of the extended display device in real time and caching the acquired current extended display parameters to the extended display parameter caching module;

the display parameter comparison module is used for respectively obtaining current main display parameters from the main display parameter cache module and current extended display parameters from the extended display parameter cache module at preset time points, comparing the current main display parameters with the current extended display parameters, and when the current main display parameters are different from the current extended display parameters, the extended display control module adjusts the display parameters of the extended display device to enable the display parameters of the extended display device to be the same as the display parameters of the main display device.

Preferably, the display information processing unit further includes: the main display parameter acquisition low-pass filtering module and the extended display parameter acquisition low-pass filtering module;

the main display parameter acquisition low-pass filtering module is connected with the main display parameter acquisition module and is used for filtering a current display parameter signal which is acquired by the main display device in real time;

the extended display parameter acquisition low-pass filtering module is connected with the extended display parameter acquisition module and is used for filtering a current display parameter signal acquired by the extended display device in real time.

Preferably, the main display parameter acquisition low-pass filtering module comprises: a first basic transconductance cell Gm1, a second basic transconductance cell Gm2 and a capacitor C1;

a first end of the first basic transconductance unit Gm1 is connected with a power supply Vin +, a second end of the first basic transconductance unit Gm1 is connected with a second end of the second basic transconductance unit Gm2, and a third end of the first basic transconductance unit Gm1 is connected with a first end of a capacitor C1 and Vout +;

the first end of the second basic transconductance unit Gm2 is connected with a power supply Vin-, and the third end of the second basic transconductance unit Gm2 is respectively connected with the second end of the capacitor C1 and Vout-;

the first basic transconductance unit Gm1 and the second basic transconductance unit Gm2 share a group of current sources by adopting a current multiplexing technology to form a whole.

According to the technical scheme, the invention has the following advantages:

the display information processing unit adopts a mobile phone, or a camera, or a flat panel. The current display parameters of the main display device are collected through a mobile phone, a camera or a panel, the parameters are stored, and the display parameters of the expansion display device are adjusted according to the current display parameters of the main display device, so that the current display parameters of the main display device and the expansion display device are the same. Therefore, the display parameters of the main display device and the display parameters of the extension display device are the same, the phenomenon that the brightness and color displayed by the two screens always have large contrast is avoided, poor visual experience is brought to a user, and the vision of the user is damaged by the long-time visual contrast.

Drawings

In order to more clearly illustrate the technical solution of the present invention, the drawings used in the description will be briefly introduced, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.

FIG. 1 is a general schematic diagram of a display consistency system for automatically adjusting screen expansion parameters;

FIG. 2 is a schematic diagram of an embodiment of a system for automatically adjusting the display uniformity of the expansion parameters;

FIG. 3 is a schematic diagram of a main display parameter acquisition low pass filtering module;

FIG. 4 is a schematic diagram of an embodiment of the main display parameter acquisition low-pass filter module.

Fig. 5 is a schematic diagram of a current multiplexing structure.

Detailed Description

In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions of the present invention will be clearly and completely described below with reference to specific embodiments and drawings. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the scope of protection of this patent.

The present embodiment provides a system for automatically adjusting display consistency of screen expansion parameters, as shown in fig. 1 to 5, including: a main display device 11, an extended display device 12, and a display information processing unit 13; the display information processing unit 13 is connected with the main display device 11 and the extended display device 12, respectively; the display information processing unit 13 is configured to obtain current display parameters of the main display device 11, and adjust the display parameters of the extended display device 12 according to the current display parameters of the main display device 11, so that the current display parameters of the main display device 11 and the extended display device 12 are the same.

The display information processing unit 13 employs a mobile phone, or a camera, or a tablet. The current display parameters of the main display device 11 are acquired through a mobile phone, a camera or a flat panel, the parameters are stored, and the display parameters of the extended display device 12 are adjusted according to the current display parameters of the main display device 11, so that the current display parameters of the main display device 11 and the extended display device 12 are the same. Therefore, the display parameters of the main display device and the display parameters of the extension display device are the same, the phenomenon that the brightness and color displayed by the two screens always have large contrast is avoided, poor visual experience is brought to a user, and the vision of the user is damaged by the long-time visual contrast.

The display parameters include: contrast, brightness, color temperature, gamma, sharpness.

In this embodiment, the display information processing unit 13 includes: a main display parameter obtaining module 14, a main display parameter caching module 15, an extended display parameter obtaining module 16, an extended display parameter caching module 17, a display parameter comparing module 18 and an extended display control module 19;

the main display parameter obtaining module 14 is configured to obtain a current display parameter of the main display device 11 in real time, and cache the obtained current main display parameter to the main display parameter caching module;

the extended display parameter acquiring module 16 is configured to acquire a current display parameter of the extended display device 12 in real time, and cache the acquired current extended display parameter in the extended display parameter caching module;

the display parameter comparison module 18 is configured to obtain a current main display parameter from the main display parameter cache module and a current extended display parameter from the extended display parameter cache module at preset time points, respectively, compare the current main display parameter with the current extended display parameter, and when the current main display parameter is different from the current extended display parameter, the extended display control module 19 adjusts the display parameter of the extended display device 12, so that the display parameter of the extended display device 12 is the same as the display parameter of the main display device 11.

In this embodiment, the display information processing unit 13 further includes: the main display parameter acquisition low-pass filtering module and the extended display parameter acquisition low-pass filtering module;

the main display parameter acquisition low-pass filtering module is connected with the main display parameter acquisition module, and is used for filtering a current display parameter signal acquired by the main display device 11 in real time; the extended display parameter acquisition low-pass filtering module is connected with the extended display parameter acquisition module, and is used for filtering a current display parameter signal acquired in real time by the extended display device 12.

The main display parameter acquisition low-pass filtering module and the extended display parameter acquisition low-pass filtering module can realize low-pass filtering. The low-pass filtering can solve the problem of contradiction between cut-off frequency and chip area, and can enable transmission and acquisition of display parameters to be more accurate.

The main display parameter acquisition low-pass filtering module comprises: a first basic transconductance cell Gm1, a second basic transconductance cell Gm2 and a capacitor C1;

In this embodiment, a current multiplexing structure 1 is disposed between the first basic transconductance cell Gm1 and the second basic transconductance cell Gm 2;

the current multiplexing structure 1 is used for enabling each corresponding branch between the first basic transconductance unit Gm1 and the second basic transconductance unit Gm2 to share one current, so that the current utilization efficiency is improved, and the power consumption is reduced; the first basic transconductance unit Gm1 and the second basic transconductance unit Gm2 both adopt a unit gain negative feedback connection method, so that the gain of the filter at low frequency is 1.

The first basic transconductance unit Gm1 and the second basic transconductance unit Gm2 are basic transconductance units, and C1 is an on-chip mim capacitor, which form a second-order Gm-C low pass filter. The first transconductance unit Gm1 and the second transconductance unit Gm2 share a set of current sources by adopting a current multiplexing technology to form a whole.

In this embodiment, the first basic transconductance cell Gm1 has a first adaptive source degeneration structure 2; the second basic transconductance unit Gm2 is provided with a second adaptive source negative feedback structure 3; the first adaptive source degeneration structure 2 includes: a twenty-first MOS transistor M21, a sixteenth MOS transistor M16, and a seventeenth MOS transistor M17; the second adaptive source degeneration structure 3 includes: a twelfth MOS transistor M12, a thirteenth MOS transistor M13 and a sixth MOS transistor M6; the D pole and the G pole of the twenty-first MOS transistor M21 are respectively connected with the G pole of the twenty-sixth MOS transistor M26, the sixteenth MOS transistor M16G pole and the seventeenth MOS transistor M17G pole; a twenty-sixth MOS tube M26G pole is connected with a bias voltage, and a twenty-sixth MOS tube M26S pole is connected with a power supply; the S pole of the twenty-first MOS transistor M21 is connected with the pole of a sixteenth MOS transistor M16D, the pole of a seventeenth MOS transistor M17S and the pole of a current multiplexing structure 1G; a sixteenth MOS tube M16S pole is respectively connected with the current multiplexing structure 1E pole and the first current division structure 4; a seventeenth MOS tube M17S pole is respectively connected with the I pole of the current multiplexing structure 1 and the second current division structure 5; the D pole and the G pole of the sixth MOS transistor M6 are respectively connected with the M12G pole of the twelfth MOS transistor, the M13G pole of the thirteenth MOS transistor, the M3D pole of the third MOS transistor, the M3G pole of the third MOS transistor is connected with bias voltage, and the M3S pole of the third MOS transistor is grounded; a sixth MOS transistor M6S pole is connected to the twelfth MOS transistor M12D pole, the thirteenth MOS transistor M13S pole and the current multiplexing structure 1H pole, respectively; a twelfth MOS tube M12S pole is respectively connected with the current multiplexing structure 1F pole and the third current division structure 6; the thirteenth MOS transistor M13D is connected to the current multiplexing structure 1J and the fourth current splitting structure 7 respectively.

In this embodiment, the first current splitting structure 4 includes: a nineteenth MOS transistor M19 and a twentieth MOS transistor M20; the second current dividing structure 5 includes: a twenty-second MOS transistor M22 and a twenty-third MOS transistor M23; the third current dividing structure 6 includes: a seventh MOS transistor M7 and an eighth MOS transistor M8; the fourth current dividing structure 7 includes: a ninth MOS transistor M9 and a tenth MOS transistor M10; the source electrode of the seventh MOS transistor M7 is connected with the source electrode of the eighth MOS transistor M8, the gate electrode of M7 is connected with the gate electrode of the eighth MOS transistor M8, and the drain electrode of the seventh MOS transistor M7 is grounded; the drain of the eighth MOS transistor M8 is connected to the drain of the second M2MOS transistor, and the source of the eighth MOS transistor M8 is connected to the source of the twelfth MOS transistor M12. The source of the ninth MOS transistor M9 is connected with the source of the tenth MOS transistor M10, the gate of the ninth MOS transistor M9 is connected with the gate of the tenth MOS transistor M10, the source of the ninth MOS transistor M9 is connected with the drain of the thirteenth MOS transistor M13, and the drain of the tenth MOS transistor M10 is grounded; the source of the nineteenth MOS transistor M19 is connected with the source of the twentieth MOS transistor M20, the gate of the nineteenth MOS transistor M19 is connected with the gate of the twentieth MOS transistor M20, and the drain of the nineteenth MOS transistor M19 is connected with VDD. The drain of the twentieth MOS transistor M20 is connected to the drain of the twenty-fifth MOS transistor M25, and the source of the twentieth MOS transistor M20 is connected to the source of the sixteenth MOS transistor M16. The source of the twenty-second MOS transistor M22 is connected with the source of the twenty-third MOS transistor M23, the gate of the twenty-second MOS transistor M22 is connected with the gate of the twenty-third MOS transistor M23, the source of the twenty-second MOS transistor M22 is connected with the drain of the M17, and the drain of the M23 is connected with VDD;

the size ratios of a ninth MOS transistor M9, a tenth MOS transistor M10, an eighth MOS transistor M8, a seventh MOS transistor M7, a twentieth MOS transistor M20, a nineteenth MOS transistor M19, a twelfth MOS transistor M22 and a thirteenth MOS transistor M23 are all 1: and N, realizing the division of the current.

In this embodiment, the current multiplexing structure 1 includes: the clamp amplifier AMP, a twenty-ninth MOS transistor M29, a thirty-ninth MOS transistor M30, a thirty-first MOS transistor M31, a thirty-second MOS transistor M32, a thirty-third MOS transistor M33, a thirty-fourth MOS transistor M34, a thirty-fifth MOS transistor M35, a thirty-sixth MOS transistor M36 and a thirty-seventh MOS transistor M37; the width-length ratios of a thirty-third MOS transistor M30, a thirty-first MOS transistor M31, a thirty-second MOS transistor M32, a thirty-fourth MOS transistor M34, a thirty-fifth MOS transistor M35 and a thirty-sixth MOS transistor M36 are n times of those of a twenty-ninth MOS transistor M29 and a thirty-third MOS transistor M33 respectively; the inverting input terminal of the amplifier AMP is connected to the reference voltage VREF, the non-inverting input terminal thereof is connected to the source of the thirty-third MOS transistor M33, and the output terminal thereof is connected to the gate of the thirty-seventh MOS transistor M37. The grid electrode and the drain electrode of the twenty-ninth MOS tube M29 are connected; two ends of the current source IB are respectively grounded and the drain electrode of the twenty-ninth MOS transistor M29; the drain and the gate of the thirty-third MOS transistor M33 are connected; the drain of the thirty-seventh MOS transistor M37 is connected with the drain of the thirty-third MOS transistor M33, the source of the thirty-third MOS transistor M33, the thirty-fourth MOS transistor M34, the thirty-fifth MOS transistor M35 and the gate of the thirty-sixth MOS transistor M36 are connected with VDD, and the gates of the twenty-ninth MOS transistor M29, the thirty-fourth MOS transistor M30, the thirty-eleventh MOS transistor M31 and the thirty-twelfth MOS transistor M32 are connected with one another; a thirty-third MOS transistor M33, a thirty-fourth MOS transistor M34, a thirty-fifth MOS transistor M35, and a source of the thirty-sixth MOS transistor M36 is connected to sources of the twenty-ninth MOS transistor M29, the thirty-fifth MOS transistor M30, the thirty-eleventh MOS transistor M31, and the thirty-twelfth MOS transistor M32, respectively.

In this embodiment, the sources of the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, and the fifth MOS transistor M5 are grounded, and the gates and drains of the second MOS transistor M2 and the fourth MOS transistor M4 are connected; the grid electrode of the first MOS tube M1 is connected with the drain electrode of the second MOS tube M2; the drain electrode of the first MOS transistor M1 is connected with the drain electrode of the eleventh MOS transistor M11; the gate of the third MOS transistor M3 is connected to the bias voltage VBIAS 1; the grid electrode of the fifth MOS tube M5 is connected with the drain electrode of the fourth MOS tube M4, and the drain electrode of the fifth MOS tube M5 is connected with the drain electrode of the fourteenth MOS tube M14; the grid electrode of the eleventh M11MOS tube is connected with the drain electrode, and the source electrode of the eleventh M11MOS tube is connected with the source electrode of the fifteenth MOS tube M15; the grid electrode of the fourteenth MOS tube M14 is connected with the drain electrode of the eleventh MOS tube M11, and the source electrode of the fourteenth MOS tube M18 is connected with the source electrode of the eighteenth MOS tube M18; the gate and the drain of the fifteenth MOS transistor M15 are connected; the grid electrode of the eighteenth MOS tube M18 is connected with the grid electrode of the fifteenth MOS tube, and the drain electrode of the eighteenth MOS tube M18 is connected with the drain electrode of the twenty-eighth MOS tube M28; the source electrodes of the twenty-fourth MOS transistor M24, the twenty-fifth MOS transistor M25, the twenty-sixth MOS transistor M26, the twenty-seventh MOS transistor M27 and the twenty-eighteenth MOS transistor M28 are connected with VDD. The drain electrode of the twenty-fourth MOS tube M24 is connected with the drain electrode of the fifteenth MOS tube M15, and the gate electrode of the twenty-fifth MOS tube M25 is connected with the grid electrode of the twenty-fourth MOS tube M24; the gate and the drain of the twenty-fifth MOS transistor M25 are connected. The gate of the twenty-sixth MOS transistor M26 is connected to the bias voltage VBIAS 2; the grid electrode of the twenty-seventh MOS tube M27 is connected with the drain electrode, the grid electrode of the twenty-eighth MOS tube M28 is connected with the grid electrode of the twenty-seventh MOS tube M27.

In this embodiment, the current multiplexing structure further includes: multiplexing current sources L1, L2, L3; the E end of the L1 is connected with the source electrode of the sixteenth MOS tube M16, and the F end is connected with the source electrode of the twelfth MOS tube M12. The G terminal of the L2 is connected with the drain of the sixteenth MOS transistor M16, and the H terminal is connected with the drain of the twelfth MOS transistor M12. The I end of the L3 is connected with the drain electrode of a seventeenth MOS tube M17, and the J end is connected with the drain electrode of a thirteenth MOS tube M13.

In a circuit implementation form of the first transconductance unit Gm1 and the second transconductance unit Gm2, sources of MOS tubes M1-M5 are grounded, and gates and drains of MOS tubes M2 and M4 are connected. The gate of M1 and the drain of M2 are connected. The drain of M1 and the drain of M11 are connected. The gate of M3 is connected to bias voltage VBIAS 1. The gate of M5 is connected to the drain of M4, and the drain of M5 is connected to the drain of M14. The gate of M11 is connected to the drain, and the source is connected to the source of M15. The gate of M14 is connected to the drain of M11 and the source is connected to the source of M18. The gate and drain of M15 are connected. The gate of M18 is connected with the gate of M15, and the drain is connected with the drain of M28. The sources of M24-M28 are connected to VDD. The drain of M24 is connected with the drain of M15, and the gate is connected with the gate of M25. The gate and drain of M25 are connected. The gate of M26 is connected to bias voltage VBIAS 2. The gate and the drain of M27 are connected, and the gate of M28 and the gate of M27 are connected.

In the circuit structures of the first transconductance unit Gm1 and the second transconductance unit Gm2, the adaptive source degeneration structure includes: m6, M12, M13, M16, M17, M21. Wherein the drain of M6 is connected to the drain of M3 and the gate and drain of M6 are connected. The source of M6, the source of M13, and the drain of M12 are connected. The gates of M12, M13, M16 are connected. The drain of M21 is connected to the drain of M26, and the gate and drain of M21 are connected. The source of M17, the source of M21, and the drain of M16 are connected. The gates of M16, M17, M21 are connected.

In the circuit structure of the first transconductance cell Gm1 and the second transconductance cell Gm2, the current division structure includes: m7, M8, M9, M10, M19, M20, M22 and M23.

In the circuit structure of the first transconductance cell Gm1 and the second transconductance cell Gm2, the current multiplexing structure includes: multiplexing current sources L1, L2, L3. Wherein the E terminal of L1 is connected to the source of M16, and the F terminal is connected to the source of M12. Wherein the G terminal of L2 is connected to the drain of M16, and the H terminal is connected to the drain of M12. Wherein the I terminal of L3 is connected to the drain of M17 and the J terminal is connected to the drain of M13.

The current multiplexing structure comprises a clamping amplifier AMP and MOS tubes M29-M37. The specific circuit implementation is shown in fig. 4. Wherein the width-length ratios of M30-M32 and M34-M36 are n times of M29 and M33 respectively. The inverting input terminal of the amplifier AMP is connected to the reference voltage VREF, the non-inverting input terminal thereof is connected to the source of the MOS transistor M33, and the output terminal thereof is connected to the gate of the transistor M37. The gate and drain of M29 are connected. The two terminals of the current source IB are respectively connected to ground and the drain of M29. The drain and gate of M33 are connected. The drain of M37 is connected to the drain of M33 and the source is connected to VDD. The gates of M33, M34, M35 and M36 are connected, and the gates of M29, M30, M31 and M32 are connected. The sources of M33, M34, M35 and M36 are respectively connected with the sources of M29, M30, M31 and M32.

The circuit implementation form of the current multiplexing structure is that IB provides reference current, and M29 and M30, M31 and M32, M33 and M34, M35 and M36 form a current mirror. The clamping operational amplifier AMP, the PMOS pipe M37 and the NMOS pipe M33 form a negative feedback loop, and the inverting terminal of the AMP is connected with a reference voltage, so that the voltage of the point A is clamped at VREF, wherein VREF is 0.5 VDD. A. Point B, C, D is equal in potential to VREF. E, F, G, H, I, G in FIG. 3 are all high impedance nodes and correspond to the corresponding nodes of FIG. 4. The width-length ratios of M30-M32 and M34-M36 are n times of those of M29 and M33 respectively, so that the current flowing through the branch where the B, C, D node is located is enlarged by n times of IB, and the current is provided for the first transconductance unit Gm1 and the second transconductance unit Gm 2. Compared with the traditional single-ended current source, the two output ends of the current sources L1-L3 in the current multiplexing structure are both the drains of MOS tubes, so that the two output ends are both high-resistance nodes.

The extended display parameter acquisition low-pass filtering module has the same structure as the main display parameter acquisition low-pass filtering module.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. The utility model provides an automatic adjust and expand screen parameter display uniformity system which characterized in that includes: the display device comprises a main display device, an extended display device and a display information processing unit;

the display information processing unit is used for acquiring the current display parameters of the main display device and adjusting the display parameters of the extended display device according to the current display parameters of the main display device, so that the current display parameters of the main display device and the extended display device are the same;

the display information processing unit includes: the device comprises a main display parameter acquisition module, a main display parameter cache module, an extended display parameter acquisition module, an extended display parameter cache module, a display parameter comparison module and an extended display control module;

the display parameter comparison module is used for respectively obtaining current main display parameters from the main display parameter cache module and current extended display parameters from the extended display parameter cache module at preset time points, comparing the current main display parameters with the current extended display parameters, and when the current main display parameters are different from the current extended display parameters, the extended display control module adjusts the display parameters of the extended display device to enable the display parameters of the extended display device to be the same as the display parameters of the main display device;

the display information processing unit further includes: the main display parameter acquisition low-pass filtering module and the extended display parameter acquisition low-pass filtering module;

the extended display parameter acquisition low-pass filtering module is connected with the extended display parameter acquisition module and is used for filtering a current display parameter signal acquired by the extended display device in real time;

the main display parameter acquisition low-pass filtering module comprises: a first basic transconductance cell (Gm1), a second basic transconductance cell (Gm2) and a capacitor C1;

a first end of the first basic transconductance unit (Gm1) is connected with a power supply Vin +, a second end of the first basic transconductance unit (Gm1) is connected with a second end of the second basic transconductance unit (Gm2), and a third end of the first basic transconductance unit (Gm1) is respectively connected with a first end of a capacitor C1 and Vout +;

the first end of the second basic transconductance unit (Gm2) is connected with a power supply Vin-, and the third end of the second basic transconductance unit (Gm2) is respectively connected with the second end of the capacitor C1 and Vout-;

the first basic transconductance unit (Gm1) and the second basic transconductance unit (Gm2) share a group of current sources by adopting a current multiplexing technology to form a whole;

a current multiplexing structure (1) is arranged between the first basic transconductance unit (Gm1) and the second basic transconductance unit (Gm 2);

the current multiplexing structure (1) is used for enabling each corresponding branch between the first basic transconductance unit (Gm1) and the second basic transconductance unit (Gm2) to share one current, so that the current utilization efficiency is improved, and the power consumption is reduced; the first basic transconductance unit (Gm1) and the second basic transconductance unit (Gm2) adopt a negative feedback connection method of unit gain, so that the gain of the filter at low frequency is 1;

the first basic transconductance unit (Gm1) is provided with a first adaptive source negative feedback structure (2);

the second basic transconductance unit (Gm2) is provided with a second adaptive source negative feedback structure (3);

the first adaptive source degeneration structure (2) comprises: a twenty-first MOS transistor M21, a sixteenth MOS transistor M16, and a seventeenth MOS transistor M17;

the second adaptive source degeneration structure (3) comprises: a twelfth MOS transistor M12, a thirteenth MOS transistor M13 and a sixth MOS transistor M6;

a D pole and a G pole of the twenty-first MOS transistor M21 are respectively connected with a G pole of the twenty-sixth MOS transistor M26, a sixteenth MOS transistor M16G pole and a seventeenth MOS transistor M17G pole; a twenty-sixth MOS tube M26G pole is connected with a bias voltage, and a twenty-sixth MOS tube M26S pole is connected with a power supply;

the S pole of the twenty-first MOS transistor M21 is connected with the M16D pole of the sixteenth MOS transistor, the M17S pole of the seventeenth MOS transistor and the G pole of the current multiplexing structure (1);

a pole of a sixteenth MOS transistor M16S is respectively connected with a pole E of the current multiplexing structure (1) and the first current division structure (4);

a pole of a seventeenth MOS transistor M17S is respectively connected with the I pole of the current multiplexing structure (1) and the second current division structure (5);

the D pole and the G pole of the sixth MOS transistor M6 are respectively connected with the M12G pole of the twelfth MOS transistor, the M13G pole of the thirteenth MOS transistor, the M3D pole of the third MOS transistor, the M3G pole of the third MOS transistor is connected with bias voltage, and the M3S pole of the third MOS transistor is grounded;

a sixth MOS transistor M6S pole is respectively connected with a twelfth MOS transistor M12D pole, a thirteenth MOS transistor M13S pole and a current multiplexing structure (1) H pole;

a pole of the twelfth MOS transistor M12S is respectively connected with a pole F of the current multiplexing structure (1) and the third current division structure (6);

a thirteenth MOS tube M13D pole is respectively connected with a J pole of the current multiplexing structure (1) and the fourth current division structure (7);

the first current dividing structure (4) includes: a nineteenth MOS transistor M19 and a twentieth MOS transistor M20;

the second current dividing structure (5) includes: a twenty-second MOS transistor M22 and a twenty-third MOS transistor M23;

the third current dividing structure (6) includes: a seventh MOS transistor M7 and an eighth MOS transistor M8;

the fourth current division structure (7) includes: a ninth MOS transistor M9 and a tenth MOS transistor M10;

the source electrode of the seventh MOS transistor M7 is connected with the source electrode of the eighth MOS transistor M8, the gate electrode of M7 is connected with the gate electrode of the eighth MOS transistor M8, and the drain electrode of the seventh MOS transistor M7 is grounded; the drain electrode of the eighth MOS transistor M8 is connected with the drain electrode of the second M2MOS transistor, the source electrode of the eighth MOS transistor M8 is connected with the source electrode of the twelfth MOS transistor M12, the source electrode of the ninth MOS transistor M9 is connected with the source electrode of the tenth MOS transistor M10, the gate electrode of the ninth MOS transistor M9 is connected with the gate electrode of the tenth MOS transistor M10, the source electrode of the ninth MOS transistor M9 is connected with the drain electrode of the thirteenth MOS transistor M13, and the drain electrode of the tenth MOS transistor M10 is grounded; the source of the nineteenth MOS tube M19 is connected with the source of the twentieth MOS tube M20, the gate of the nineteenth MOS tube M19 is connected with the gate of the twentieth MOS tube M20, the drain of the nineteenth MOS tube M19 is connected with VDD, the drain of the twentieth MOS tube M20 is connected with the drain of the twenty-fifth MOS tube M25, the source of the twentieth MOS tube M20 is connected with the source of the sixteenth MOS tube M16, the source of the twelfth MOS tube M22 is connected with the source of the twenty-third MOS tube M23, the gate of the twenty-second MOS tube M22 is connected with the gate of the twenty-third MOS tube M23, the source of the twenty-second MOS tube M22 is connected with the drain of the M17, and the drain of the M23 is connected with VDD;

the size ratios of a ninth MOS transistor M9, a tenth MOS transistor M10, an eighth MOS transistor M8, a seventh MOS transistor M7, a twentieth MOS transistor M20, a nineteenth MOS transistor M19, a twelfth MOS transistor M22 and a thirteenth MOS transistor M23 are all 1: n, realizing the division of the current;

the current multiplexing structure (1) comprises: the clamp amplifier AMP, a twenty-ninth MOS transistor M29, a thirty-ninth MOS transistor M30, a thirty-first MOS transistor M31, a thirty-second MOS transistor M32, a thirty-third MOS transistor M33, a thirty-fourth MOS transistor M34, a thirty-fifth MOS transistor M35, a thirty-sixth MOS transistor M36 and a thirty-seventh MOS transistor M37;

the width-length ratios of a thirty-third MOS transistor M30, a thirty-first MOS transistor M31, a thirty-second MOS transistor M32, a thirty-fourth MOS transistor M34, a thirty-fifth MOS transistor M35 and a thirty-sixth MOS transistor M36 are n times of those of a twenty-ninth MOS transistor M29 and a thirty-third MOS transistor M33 respectively;

the inverting input end of the amplifier AMP is connected with the reference voltage VREF, the non-inverting input end of the amplifier AMP is connected with the source electrode of the thirty-third MOS tube M33, the output end of the amplifier AMP is connected with the grid electrode of the thirty-seventh MOS tube M37, and the grid electrode of the twenty-ninth MOS tube M29 is connected with the drain electrode; two ends of the current source IB are respectively grounded and the drain electrode of the twenty-ninth MOS transistor M29; the drain and the gate of the thirty-third MOS transistor M33 are connected; the drain of the thirty-seventh MOS transistor M37 is connected with the drain of the thirty-third MOS transistor M33, the source of the thirty-third MOS transistor M33, the thirty-fourth MOS transistor M34, the thirty-fifth MOS transistor M35 and the gate of the thirty-sixth MOS transistor M36 are connected with VDD, and the gates of the twenty-ninth MOS transistor M29, the thirty-fourth MOS transistor M30, the thirty-eleventh MOS transistor M31 and the thirty-twelfth MOS transistor M32 are connected with one another; a thirty-third MOS transistor M33, a thirty-fourth MOS transistor M34, a thirty-fifth MOS transistor M35 and a thirty-sixth MOS transistor M36 are connected with the sources of the twenty-ninth MOS transistor M29, the thirty-fifth MOS transistor M30, the thirty-eleventh MOS transistor M31 and the thirty-twelfth MOS transistor M32 respectively;

the source electrodes of the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4 and the fifth MOS transistor M5 are grounded, and the grid electrodes and the drain electrodes of the second MOS transistor M2 and the fourth MOS transistor M4 are connected; the grid electrode of the first MOS tube M1 is connected with the drain electrode of the second MOS tube M2; the drain electrode of the first MOS transistor M1 is connected with the drain electrode of the eleventh MOS transistor M11; the gate of the third MOS transistor M3 is connected to the bias voltage VBIAS 1; the grid electrode of the fifth MOS tube M5 is connected with the drain electrode of the fourth MOS tube M4, and the drain electrode of the fifth MOS tube M5 is connected with the drain electrode of the fourteenth MOS tube M14; the grid electrode of the eleventh M11MOS tube is connected with the drain electrode, and the source electrode of the eleventh M11MOS tube is connected with the source electrode of the fifteenth MOS tube M15;

the grid electrode of the fourteenth MOS tube M14 is connected with the drain electrode of the eleventh MOS tube M11, and the source electrode of the fourteenth MOS tube M18 is connected with the source electrode of the eighteenth MOS tube M18; the gate and the drain of the fifteenth MOS transistor M15 are connected; the grid electrode of the eighteenth MOS tube M18 is connected with the grid electrode of the fifteenth MOS tube, and the drain electrode of the eighteenth MOS tube M18 is connected with the drain electrode of the twenty-eighth MOS tube M28;

a twenty-fourth MOS tube M24, a twenty-fifth MOS tube M25, a twenty-sixth MOS tube M26, a twenty-seventh MOS tube M27, and a twenty-eighteenth MOS tube M28, wherein the source electrode of the twenty-fourth MOS tube M24 is connected with VDD, the drain electrode of the twenty-fourth MOS tube M24 is connected with the drain electrode of the fifteenth MOS tube M15, and the grid electrode of the twenty-fifth MOS tube M25 is connected with the grid electrode of the twenty-fourth MOS tube M25; the gate and the drain of the twenty-fifth MOS transistor M25 are connected, and the gate of the twenty-sixth MOS transistor M26 is connected with the bias voltage VBIAS 2; the grid electrode of the twenty-seventh MOS tube M27 is connected with the drain electrode, the grid electrode of the twenty-eighth MOS tube M28 is connected with the grid electrode of the twenty-seventh MOS tube M27;

the current multiplexing structure further includes: multiplexing current sources L1, L2, L3; the E end of the L1 is connected with the source electrode of a sixteenth MOS tube M16, the F end is connected with the source electrode of a twelfth MOS tube M12, the G end of the L2 is connected with the drain electrode of the sixteenth MOS tube M16, the H end is connected with the drain electrode of the twelfth MOS tube M12, the I end of the L3 is connected with the drain electrode of a seventeenth MOS tube M17, and the J end is connected with the drain electrode of the thirteenth MOS tube M13.

2. The system for automatically adjusting display uniformity of screen expansion parameters according to claim 1,