CN108321203B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN108321203B
CN108321203B CN201711381037.3A CN201711381037A CN108321203B CN 108321203 B CN108321203 B CN 108321203B CN 201711381037 A CN201711381037 A CN 201711381037A CN 108321203 B CN108321203 B CN 108321203B
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region
insulating film
semiconductor device
main surface
isolation
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CN108321203A (zh
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藤井宏基
森隆弘
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
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    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
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    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
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    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
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    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
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    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/152—Source regions of DMOS transistors
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    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
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    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
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    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
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    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
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    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
CN201711381037.3A 2016-12-20 2017-12-20 半导体器件及其制造方法 Active CN108321203B (zh)

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JP2016246521A JP6710627B2 (ja) 2016-12-20 2016-12-20 半導体装置およびその製造方法

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JP6837384B2 (ja) * 2017-05-23 2021-03-03 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US10424647B2 (en) 2017-10-19 2019-09-24 Texas Instruments Incorporated Transistors having gates with a lift-up region
JP7195167B2 (ja) * 2019-02-08 2022-12-23 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
US11195915B2 (en) * 2019-04-15 2021-12-07 Texas Instruments Incorporated Semiconductor devices with a sloped surface
US11222955B2 (en) * 2020-04-22 2022-01-11 Wolfspeed, Inc. Semiconductor power devices having gate dielectric layers with improved breakdown characteristics and methods of forming such devices
US11469307B2 (en) * 2020-09-29 2022-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. Thicker corner of a gate dielectric structure around a recessed gate electrode for an MV device
US12057475B2 (en) * 2021-03-11 2024-08-06 Taiwan Semiconductor Manufacturing Company Limited Field effect transistor including a downward-protruding gate electrode and methods for forming the same
US20240030341A1 (en) * 2022-07-25 2024-01-25 Globalfoundries U.S. Inc. High performance laterally-diffused metal-oxide semiconductor structure
US20240162345A1 (en) * 2022-11-10 2024-05-16 Globalfoundries U.S. Inc. Transistor with metal field plate contact
TWI828536B (zh) * 2023-02-08 2024-01-01 力晶積成電子製造股份有限公司 電晶體結構及其製造方法

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US6608351B1 (en) * 1999-06-03 2003-08-19 Koninkl Philips Electronics Nv Semiconductor device comprising a high-voltage circuit element
JP2005183633A (ja) * 2003-12-18 2005-07-07 Toyota Central Res & Dev Lab Inc 半導体装置とその製造方法
CN104685614A (zh) * 2012-10-16 2015-06-03 旭化成微电子株式会社 场效应晶体管以及半导体装置
CN104882481A (zh) * 2014-02-27 2015-09-02 瑞萨电子株式会社 半导体器件

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JP5385679B2 (ja) * 2008-05-16 2014-01-08 旭化成エレクトロニクス株式会社 横方向半導体デバイスおよびその製造方法

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US6608351B1 (en) * 1999-06-03 2003-08-19 Koninkl Philips Electronics Nv Semiconductor device comprising a high-voltage circuit element
JP2005183633A (ja) * 2003-12-18 2005-07-07 Toyota Central Res & Dev Lab Inc 半導体装置とその製造方法
CN104685614A (zh) * 2012-10-16 2015-06-03 旭化成微电子株式会社 场效应晶体管以及半导体装置
CN104882481A (zh) * 2014-02-27 2015-09-02 瑞萨电子株式会社 半导体器件

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CN108321203A (zh) 2018-07-24
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US20180175192A1 (en) 2018-06-21
JP6710627B2 (ja) 2020-06-17

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