CN108231690A - The forming method of dynamic random access memory - Google Patents

The forming method of dynamic random access memory Download PDF

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Publication number
CN108231690A
CN108231690A CN201611198384.8A CN201611198384A CN108231690A CN 108231690 A CN108231690 A CN 108231690A CN 201611198384 A CN201611198384 A CN 201611198384A CN 108231690 A CN108231690 A CN 108231690A
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CN
China
Prior art keywords
layer
forming
stochastic
dynamic
memory component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201611198384.8A
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Chinese (zh)
Inventor
陈意维
郑存闵
鄒世芳
蔡志杰
张凯钧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
Original Assignee
Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujian Jinhua Integrated Circuit Co Ltd, United Microelectronics Corp filed Critical Fujian Jinhua Integrated Circuit Co Ltd
Priority to CN201611198384.8A priority Critical patent/CN108231690A/en
Publication of CN108231690A publication Critical patent/CN108231690A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/10882Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line
    • H01L27/10885Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line with at least one step of making a bit line

Abstract

The present invention discloses a kind of forming method of stochastic and dynamic processing memory component, and it includes following steps.First, multiple active areas are formed in substrate, active area extends along a first direction.Then, multiple embedded grids are formed in substrate, embedded grid extends along second direction, and second direction is across first direction.Then, multiple bit lines are formed on embedded grid, bit line extends along third direction, third direction is across first direction and second direction, each bit line includes polysilicon layer, barrier layer and metal layer, wherein, barrier layer is formed by the RF physical manufacture craft that is vapor-deposited.

Description

The forming method of dynamic random access memory
Technical field
The present invention relates to a kind of forming methods of memory component, and storage element is handled more particularly, to a kind of stochastic and dynamic The forming method of part.
Background technology
As various electronic products are towards the trend of miniaturization, dynamic random access memory (dynamic random Access memory, DRAM) design of unit also has to comply with high integration and highdensity requirement.Have for one recessed For the DRAM cell of formula gate structure, due to it, longer carrier pathway can be obtained in identical semiconductor base long Degree, to reduce the generation of the electric leakage situation of capacitance structure, therefore under current mainstream development trend, gradually replace only have it is flat The DRAM cell of face gate structure.
In general, the DRAM cell for having concave grid structure can include a transistor unit and charge storage dress It puts, comes from bit line and the voltage signal of wordline to receive.However, be limited to Manufacturing Techniques it is therefore, it is existing have it is recessed There are still there are many defect, also treat further to improve and effective promotion concerned memory element the DRAM cell of formula gate structure Efficiency and reliability.
Invention content
The one of the present invention is designed to provide a kind of forming method of stochastic and dynamic processing memory component, is using single One manufacture craft and the smaller barrier layer of the high and thick degree of density is formed in its bit line, the premise simplified as a result, in manufacture craft The lower resistance value for reducing the barrier layer.
In order to achieve the above object, one embodiment of the invention provides a kind of stochastic and dynamic processing memory component, it includes with Lower step.First, multiple active areas are formed in a substrate, those active areas extend along a first direction.Then, at this Multiple embedded grids are formed in substrate, those embedded grids extend along a second direction, the second direction across this One direction.Finally, multiple bit lines are formed on those embedded grids, those bit lines extend along a third direction, the third Direction includes a polysilicon layer, a barrier layer and a metal layer across the first direction and the second direction, the respectively bit line, In, which formed by the RF physical manufacture craft that is vapor-deposited.
The forming method of the stochastic and dynamic processing memory component of the present invention, is to make work using RF physical vapor deposition Skill forms the barrier layer of a bit line in stochastic and dynamic processing memory component.Make the barrier layer that there can be the thickness of thinning as a result, Degree and the density of optimization, e.g. reach about 20 to 30 angstroms of thickness and the density of about 4.7 to 5.4 grams/cubic centimeter, thus can Make the bit line that there is relatively low resistance value and smaller integral thickness.Meanwhile forming method of the invention also has manufacture craft letter The effect of change.
Description of the drawings
Fig. 1 to Fig. 9 is the forming method schematic diagram that stochastic and dynamic handles memory component in present pre-ferred embodiments;Its In
Fig. 1 is that the stochastic and dynamic of the present invention handles the vertical view of memory component;
Fig. 2 to Fig. 7 is the step diagrammatic cross-section to form stochastic and dynamic processing memory component;
Fig. 8 is along the diagrammatic cross-section of tangent line A-A ' in Fig. 1;And
Fig. 9 is along the diagrammatic cross-section of tangent line B-B ' in Fig. 1.
Wherein, the reference numerals are as follows:
10 dynamic random access memories
100 substrates
101 active regions
102 memory blocks (memory body area)
104 peripheral regions
106th, 105 shallow-channel insulation
108 grooves
110 wordline (character line)
112 dielectric layers
114 grids
116 insulating layers
120 gate dielectrics
122 semiconductor layers
124 insulating layers
126 sacrificial layers
128 patterned mask layers
129 openings
130 plug trenches
160 bit lines
160a bit line contact plugs
161 polysilicon layers
163 barrier layers
163a titanium layers
163b titanium nitride layers
165 boundary layers
167 metal layers
Specific embodiment
For the general technology person for being familiar with the technical field of the invention is enable to be further understood that the present invention, hereafter spy enumerates Several preferred embodiments of the present invention, and attached drawing, the constitution content that the present invention will be described in detail and the work(to be reached appended by cooperation Effect.
Fig. 1 to Fig. 9 is please referred to, illustrated is in present pre-ferred embodiments, and stochastic and dynamic handles memory component The step schematic diagram of forming method, wherein, Fig. 1 shows the vertical view of stochastic and dynamic processing memory component 10, Fig. 2 to Fig. 7 Show the step diagrammatic cross-section of its forming method, Fig. 8 and Fig. 9 then show cuing open along tangent line A-A ' and B-B ' in Fig. 1 respectively View.
As shown in Figure 1, the present embodiment is to provide a memory cell (memory cell), e.g. have concave type grid Stochastic and dynamic processing memory (dynamic random access memory, DRAM) element 10 of pole, it includes have at least One transistor unit (not being painted) and an at least capacitance structure (not being painted), using as the minimum composition unit in DRAM array And it receives and comes from bit line (bit line, WL) 160 and the voltage signal of wordline (word line, BL) 110.In the present embodiment In, dynamic random access memory 10 includes a substrate 100, an e.g. silicon base, containing silicon base (such as SiC, SiGe) Or silicon-coated insulated (silicon-on-insulator, SOI) substrate etc., and definition has a memory block 102 and one week in substrate 100 Border area 104.Wherein, illustrating to simplify, Fig. 1 of the invention only shows the upper schematic diagram of the element positioned at memory block 102, and Omit the element positioned at peripheral region 104.Multiple active regions (active area, AA) 101 are formed in substrate 100, are mutually parallel Ground extends along a first direction.It is also formed with multiple embedded grids 114 in substrate 100, and word that can be embedded as one Line (buried word line, BWL) 110.Embedded grid 114 is to extend in parallel to each other along a second direction, and horizontal Across the first direction.In addition, being separately formed with multiple bit lines 160 in substrate 100, it is formed on embedded grid 114, and phase Mutually parallelly extend along a third direction, and simultaneously across active region 101 and wordline 110, as shown in Figure 1.It that is, should Third direction is different from the first direction and second direction, and is preferably vertical with second direction and is not orthogonal to the first party To as shown in Figure 1.Be between bit line 160 and wordline 110 by an at least bit line contact plug (bit line contact, BLC) 160a is to electrically couple to the source/drain region (not being painted) of the respectively transistor unit.Bit line contact plug 160a is for example 160 lower section of bit line is formed in, and boundary is between two wordline 110.
In one embodiment, dynamic random access memory 10 can be formed using following steps, it is not limited to This.First, at least shallow trench isolation shallow trench an isolation, STI is formed in substrate 100), the shallow trench Isolation is to be located at memory block 102 and peripheral region 104 simultaneously.In the present embodiment, memory block 102 and peripheral region 104 are selected at The different shallow trench isolation 106,105 of depth is respectively formed, as shown in Fig. 2, but not limited to this.Also, it is formed in memory block 102 shallow trench isolation 106 can define active region 101 as shown in Figure 1 in substrate 100.
Then, form multiple grooves 108 in the memory block of substrate 100 102, each groove 108 it is parallel to each other and towards this Two directions extend (not being painted).Then, a dielectric layer of 108 overall surface of covering groove is sequentially formed in each groove 108 112nd, it fills up an embedded grid 114 of 108 lower half of groove and fills up an insulating layer 116 of 108 first half of groove, make absolutely Edge layer 116 trims 100 surface of substrate, and forms wordline 110 as shown in Figure 1.
It is formed and is only located at a gate dielectric 120 of peripheral region 104 and semi-conductor layer 122, e.g. a polysilicon layer. Then, it is formed simultaneously positioned at an insulating layer 124 of memory block 102 and peripheral region 104, is covered in gate dielectric 120 with partly leading On body layer 122.As shown in Fig. 2, insulating layer 124 is for example comprising silicon monoxide-silicon-nitride and silicon oxide (oxide-nitride- Oxide, ONO) structure, and it is in direct contact the semiconductor layer 122 positioned at peripheral region 104 and the substrate 100 positioned at memory block 102 With the wordline 110 in it.
Then, a sacrificial layer 126 and a patterned mask layer 128 are sequentially formed in substrate 100, sacrificial layer 126 is for example It is an organic dielectric layer, but not limited to this.Patterned mask layer 128 can define opening for plug trenches at least one The patterns of openings is transferred to the sacrificial layer 126 of lower section by mouth pattern (not being painted), you can opening is formed in sacrificial layer 126 129, and the insulating layer 124 of part is exposed, as shown in Figure 2.
Continue an etching process, remove from the insulating layer 124 that opening 129 exposes and part base below Bottom 100, to form at least one plug trenches 130 in the memory block of substrate 100 102.Plug trenches 130 are preferably formed in Between two wordline 110, and the substrate 100 of a part is exposed, as shown in Figure 3.In one embodiment, the exposure can also be passed through Substrate 100 carries out an ion implanting manufacture craft, e.g. primary antibody junction breakdown (anti-punch-through) ion implanting Manufacture craft, to form the doped region (not being painted) that can avoid current leakage in the substrate 100 of the exposure.
Later, patterned mask layer 128 is being removed completely with after sacrificial layer 126, being formed in the memory block of substrate 100 102 Semi-conductor layer 161, e.g. a polysilicon layer.For example, a chemical vapor deposition (chemical vapor are utilized Deposition, CVD) manufacture craft, semiconductor material layer (not being painted), Ran Houjin are first comprehensively formed in substrate 100 Row at least one planarization manufacture craft, such as comprising a chemical mechanical grinding (chemical-mechanical polishing, CMP) manufacture craft to be located at the insulating layer 124 of 122 top of semiconductor layer as stop-layer, partly removes the semi-conducting material Layer, and the flush semiconductor layer 161 of top surface is formed, as shown in Figure 4.Then, another planarization manufacture craft, example are carried out CMP manufacture crafts in this way, part removes the semiconductor layer 161 positioned at memory block 102, while removes be located at semiconductor layer completely The insulating layer 124 of 122 tops to expose the semiconductor layer 122 of peripheral region 104, and makes the semiconductor layer positioned at memory block 102 161 have the top surface flushed with semiconductor layer 122, as shown in Figure 5.
Then, it may be selected to carry out a prerinse (pre-cleaning) manufacture craft, remove aforementioned planarization manufacture craft Remaining residue afterwards.However, it in other embodiments, also may be selected to omit the prerinse manufacture craft.Then, in substrate 100 form a barrier layer (barrier layer) 163, pair of lamina structure are preferably had, e.g. by a titanium (Ti) layer 163a It is formed with titanium nitride (TiN) layer 163b, as shown in Figure 6.In the present embodiment, a RF physical vapor deposition is preferably carried out (radio frequency physical vapor deposition, RF-PVD) manufacture craft, the sequentially shape in substrate 100 Into titanium layer 163a and titanium nitride layer 163b.Specifically, the RF physical vapor deposition be in a physical vapor deposition chamber (not Be painted) in carry out, be under vacuum conditions, a target (not to be painted), e.g. titanium, be placed in the physical vapor deposition chamber Top, substrate 100 is then placed in the bottom of physical vapor deposition chamber, wherein, be supplied to the power source (RF of the target Source) be about 40 megahertzs (MHz) to 50 megahertzs, be supplied to the power source (RF bias) of substrate 100 be about then 20 megahertzs extremely 100 megahertzs, the gas pressure of sputter is made to be promoted to about 100 millitorrs (mTorr) to 150 millitorrs, and with the deposition rate of about 6A/s Form titanium layer 163a and titanium nitride layer 163b.Titanium layer 163a and titanium nitride layer 163b can have thickness and the optimization of thinning as a result, Density.For example, the thickness of titanium layer 163a is, for example, about 10 to 20 angstroms (angstroms);And the thickness of titanium nitride layer 163b Degree is, for example, about 20 to 30 angstroms, and density then can reach about 4.7 to 5.4 gram/cubic centimeter (g/cm3).That is, using penetrating Frequency physical vapour deposition (PVD) manufacture craft can form integral thickness between 40 angstroms to 50 angstroms and with highdensity barrier layer 163.
Then, as shown in fig. 7, sequentially forming a boundary layer 165 and a metal layer 167 on barrier layer 163.Come in detail It says, boundary layer 165 is, for example, a tungsten silicide (tungsten silicon, WSi) layer, and metal layer 167 then includes tungsten The low-resistances matter metal material such as (tungsten, W), aluminium (aluminum, Al) or copper (copper, Cu).In one embodiment, interface Layer 165 with metal layer 167 is formed by a physical vapour deposition (PVD) manufacture craft, and but not limited to this.
Finally, a pattern mask layer (not being painted) is formed on metal layer 167, with the metal layer 167 of patterning lower section, boundary Face layer 165, barrier layer 163 and semiconductor layer 161, and form bit line 160 as shown in Figure 1.In other words, bit line 160 is by scheming Semiconductor layer 161, barrier layer 163, the boundary layer 165 of case are collectively constituted with metal layer 167, and insert plug trenches 130 Interior semiconductor layer 161 can form bit line contact plug (bit line contact, BLC) 160a, as can be seen from figures 8 and 9. Bit line contact plug 160a is formed in 160 lower section of bit line, and is integrally formed with bit line 160.Between bit line 160 and wordline 114 It is mutually isolated by the insulating layer 124 being formed in substrate 100, and bit line 160 further passes through bit line contact plug 160a is electrically connected to the source/drain region (not being painted) of the respectively transistor unit.
The stochastic and dynamic processing memory component 10 in present pre-ferred embodiments can be formed as a result,.In the present embodiment In be using RF physical vapor deposition manufacture craft formed bit line 160 barrier layer 163, with double-layer structure, such as wrap Titanium-containing layer 163a and titanium nitride layer 163b.The barrier layer 163 of the present embodiment is (such as former compared to by other manufacture crafts as a result, Son deposition manufacture craft or other chemical vapor deposition manufacture crafts etc.) film layer that is formed can have thickness and the optimization of thinning Density, wherein, the thickness of titanium nitride layer 163b is about 20 to 30 angstroms, and density then can reach about 4.7 to 5.4 gram/cube public affairs Point.Therefore, it is handled in memory component 10 by the stochastic and dynamic that the method for the present embodiment is formed, the resistance value of bit line 160 can Effectively reduce.On the other hand, though barrier layer 163 have double-layer structure, its integral thickness only between 40 angstroms to 50 angstroms, because And the height of bit line 160 and the effect simplified with manufacture craft can be effectively improved.
Generally speaking, the present invention is to provide a kind of forming method of stochastic and dynamic processing memory component, is to utilize to penetrate Frequency physical vapour deposition (PVD) manufacture craft forms the barrier layer of stochastic and dynamic processing memory component neutrality line.Make the resistance as a result, Barrier layer can have the thickness of thinning and the density of optimization, e.g. reach about 20 to 30 angstroms of thickness with about 4.7 to 5.4 grams/it is vertical The density of Fang Gongfen, thus can make the bit line that there is relatively low resistance value and smaller integral thickness.Meanwhile the present invention also has system Make the effect of technique simplification.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, that is made any repaiies Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.

Claims (12)

1. a kind of forming method of stochastic and dynamic processing memory component, it is characterised in that include:
Multiple active areas are formed in a substrate, those active areas extend along a first direction;
Multiple embedded grids are formed in the substrate, those embedded grids extend along a second direction, the second direction Across the first direction;And
Form multiple bit lines on those embedded grids, those bit lines extend along a third direction, the third direction across The first direction and the second direction, respectively the bit line include polysilicon layer, barrier layer and metal layer, wherein, which is It is formed by the RF physical manufacture craft that is vapor-deposited.
2. the forming method according to stochastic and dynamic described in claim 1 processing memory component, which is characterized in that the barrier layer Include pair of lamina structure.
3. the forming method according to stochastic and dynamic described in claim 1 processing memory component, which is characterized in that the barrier layer Include titanium layer and titanium nitride layer.
4. the forming method according to stochastic and dynamic described in claim 1 processing memory component, which is characterized in that the titanium nitride The density of layer is 4.7 to 5.4 grams/cubic centimeters.
5. the forming method according to stochastic and dynamic described in claim 1 processing memory component, which is characterized in that the titanium nitride The thickness of layer is 20 to 30 angstroms (angstroms).
6. the forming method according to stochastic and dynamic described in claim 1 processing memory component, it is characterised in that also include:
Before barrier layer formation, a precleaning manufacture craft is first carried out.
7. the forming method according to stochastic and dynamic described in claim 1 processing memory component, which is characterized in that carry out one and change Vapor deposition manufacture craft is learned to form the polysilicon layer.
8. the forming method according to stochastic and dynamic described in claim 1 processing memory component, which is characterized in that carry out an object Physical vapor deposition manufacture craft forms the metal layer.
9. the forming method according to stochastic and dynamic described in claim 1 processing memory component, which is characterized in that in the bit line An at least plug is formed between lower section, the two embedded grids, the plug and the polysilicon layer are integrally formed.
10. the forming method according to stochastic and dynamic described in claim 1 processing memory component, which is characterized in that this first Direction is not orthogonal to the second direction and the third direction.
11. the forming method according to stochastic and dynamic described in claim 1 processing memory component, which is characterized in that the radio frequency Physical vapour deposition (PVD) manufacture craft carries out in a hyperbaric environment.
12. the forming method according to the stochastic and dynamic processing memory component described in claim 11, which is characterized in that the radio frequency Physical vapour deposition (PVD) manufacture craft is carried out under 100 millitorrs to the pressure limit of 150 millitorrs.
CN201611198384.8A 2016-12-22 2016-12-22 The forming method of dynamic random access memory Pending CN108231690A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
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CN101872745A (en) * 2009-04-24 2010-10-27 海力士半导体有限公司 Semiconductor memory device and method for manufacturing the same
CN102097375A (en) * 2009-12-09 2011-06-15 海力士半导体有限公司 Method for manufacturing semiconductor device having buried gate
US20130240959A1 (en) * 2012-03-15 2013-09-19 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
CN103811554A (en) * 2012-11-13 2014-05-21 三星电子株式会社 Semiconductor devices and methods of manufacturing the same
CN105448919A (en) * 2014-09-01 2016-03-30 华邦电子股份有限公司 Dynamic random access memory and manufacturing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101872745A (en) * 2009-04-24 2010-10-27 海力士半导体有限公司 Semiconductor memory device and method for manufacturing the same
CN102097375A (en) * 2009-12-09 2011-06-15 海力士半导体有限公司 Method for manufacturing semiconductor device having buried gate
US20130240959A1 (en) * 2012-03-15 2013-09-19 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
CN103811554A (en) * 2012-11-13 2014-05-21 三星电子株式会社 Semiconductor devices and methods of manufacturing the same
CN105448919A (en) * 2014-09-01 2016-03-30 华邦电子股份有限公司 Dynamic random access memory and manufacturing method thereof

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