CN108231543A - Improve the method for polysilicon step side metal residual - Google Patents

Improve the method for polysilicon step side metal residual Download PDF

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Publication number
CN108231543A
CN108231543A CN201810024815.1A CN201810024815A CN108231543A CN 108231543 A CN108231543 A CN 108231543A CN 201810024815 A CN201810024815 A CN 201810024815A CN 108231543 A CN108231543 A CN 108231543A
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polysilicon
layer
improve
interlayer film
thickness
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CN108231543B (en
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张辉
陈正嵘
周颖
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a kind of method for improving polysilicon step side metal residual, including step：It forms polysilicon layer and lithographic definition goes out the forming region of polysilicon structure；It carries out anisotropic etching and forms polysilicon structure, the perpendicular structure of side step of polysilicon structure；The interlayer film formed by the superposition of normobaric oxygen SiClx and boron-phosphorosilicate glass is deposited, the thickness of interlayer film is more than or equal to the height of the side step of polysilicon structure；Annealing reflux, the boron-phosphorosilicate glass after reflux form a complete inclined structure at the side step of polysilicon structure；The thickness that the thickness of interlayer film is reduced to less than polysilicon structure by comprehensive wet etching is carried out to interlayer film；Form the opening of contact hole；Formed metal layer go forward side by side row metal etching.The present invention can make boron-phosphorosilicate glass be complete inclined structure at the side step of the polysilicon structure, so as to eliminate the metal residual at the side step of polysilicon structure.

Description

Improve the method for polysilicon step side metal residual
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture method, more particularly to a kind of improvement polysilicon step side The method of metal residual.
Background technology
In semiconductor integrated circuit, Electro-static Driven Comb (ESD) can generate destruction to device, so in the defeated of integrated circuit Entering output terminal needs that ESD protection circuit is set to carry out electrostatic protection, and the device for being currently used for esd protection circuit includes horizontal proliferation Metal-oxide semiconductor (MOS) (LDMOS).LDMOS device includes forming gate structure i.e. polysilicon gate, polysilicon by polysilicon layer Grid can form step structure on the surface of device, can form interlayer film and contact hole in the subsequent technique of polysilicon gate, contact Hole include by the interlayer film of contact area remove the step of forming opening and into row metal fill the step of, in the gold of contact hole Belonging to needs the metal layer that will be contacted outside bore region all to remove after filling is completed, but due to the step structure of polysilicon gate In the presence of, easily at the side of the step of polysilicon gate formed metal residual.
It is the device architecture schematic diagram in each step of existing method as shown in Figure 1A to Fig. 1 D；Existing method includes as follows Step：
Step 1: as shown in Figure 1A, 102 He of gate oxide is sequentially formed on the surface of Semiconductor substrate such as silicon substrate 101 Polysilicon layer 103.
Step 2: as shown in Figure 1A, form the forming region that photoresist (PR) figure 104 defines polysilicon gate 1031. Photoetching offset plate figure 104 is also marked in figure 1A with PR.
Step 3: as shown in Figure 1B, polysilicon gate 1031 is formed using anisotropic etching.It can be seen that polysilicon gate 1031 side is vertical stratification.Polysilicon gate is individually marked with label 1031.
Step 4: as shown in Figure 1 C, removing photoetching offset plate figure 104, interlayer film 105 is formed.Interlayer film 105 is usually by normal pressure Silica (APM) and boron-phosphorosilicate glass (BPSG) are formed by stacking.The normobaric oxygen SiClx uses Films Prepared by APCVD (Atmosphere Pressure Chemical Vapor Deposition, APCVD) technique is formed.The boron-phosphorosilicate glass Using sub- Films Prepared by APCVD (Sub-Atmosphere Pressure Chemical Vapor Deposition, SACVD) technique is formed.
BPSG has the characteristic that can carry out annealing reflux, forms BPSG and carries out annealing reflux to BPSG later.Due to more The side of crystal silicon grid 1031 is vertical stratification, can still be protected at the side step of polysilicon gate 1031 after BPSG annealing reflux Precipitous structure is held, a complete inclined side can not be formed.
Step 5: as shown in figure iD, the chemical wet etching for carrying out contact hole later forms the opening of contact hole, and contact hole is opened Mouth can not illustrate the forming region of contact hole across the interlayer film 105 in Fig. 1 D.Forming metal layer later will contact The opening in hole is filled up completely, and the deposition of fill process including metal layer and returns carving technology, and metal layer includes the folded of titanium and titanium nitride Layer 106 and tungsten 107, tungsten 107 are the agent structures of the opening of filling contact hole；Carving technology is returned to require the tungsten except contact hole 107 removals completely.But it is found that keeping steep since the BPSG of the side step in polysilicon gate 1031 has shown in Fig. 1 D High and steep structure so that the tungsten 107 at the side step of polysilicon gate 1031 is not easy to remove easily to generate tungsten residual completely.
Invention content
The technical problems to be solved by the invention are to provide a kind of method for improving polysilicon step side metal residual, energy Eliminate the metal residual at the side step of polysilicon structure.
In order to solve the above technical problems, the method provided by the invention for improving polysilicon step side metal residual is included such as Lower step：
Step 1: forming polysilicon layer, the formation of polysilicon structure is defined using photoetching process formation photoetching offset plate figure Region.
Step 2: using the photoetching offset plate figure as mask, the polysilicon layer is carried out using anisotropic etch process Etch the polysilicon structure, the perpendicular structure of side step of the polysilicon structure.
Step 3: deposition interlayer film；Superimposed layer of the interlayer film for normobaric oxygen SiClx and boron-phosphorosilicate glass, the interlayer The thickness of film is more than or equal to the height of the side step of the polysilicon structure.
Step 4: carrying out annealing reflux to the boron-phosphorosilicate glass, set by the thickness of the interlayer film in step 3 It puts the boron-phosphorosilicate glass after making reflux and a complete inclined structure is formed at the side step of the polysilicon structure.
Step 5: carrying out comprehensive wet etching to the interlayer film, the thickness of the interlayer film is reduced to target thickness Degree, the target thickness are less than the thickness of the polysilicon structure.
Step 6: the forming region of contact hole is defined using photoetching process, to the institute of the forming region of the contact hole It states interlayer film and performs etching the opening to form the contact hole.
Step 7: forming metal layer, the contact hole is filled up completely by the metal layer；The etching of metal layer is carried out by institute State contact bore region outside the metal layer all remove, using the boron-phosphorosilicate glass the polysilicon structure side platform Metal residual at rank for completely inclined feature elimination at the side step of the polysilicon structure.
A further improvement is that the polysilicon structure is polysilicon gate.
A further improvement is that the polysilicon gate is the polysilicon gate of ESD products.
A further improvement is that the ESD products are LDMOS device.
A further improvement is that the thickness of polysilicon layer described in step 1 is
A further improvement is that the target thickness of interlayer film described in step 5 is
A further improvement is that the wet etching in step 5 uses Advanced process control (Advanced Process Control, APC) table (Table) controlled.
A further improvement is that the thickness of normobaric oxygen SiClx described in step 3 isThe thickness of the boron-phosphorosilicate glass It spends and is
A further improvement is that the material of metal layer described in step 7 is tungsten.
A further improvement is that the etching of the metal layer uses dry etching.
A further improvement is that polysilicon layer described in step 1 is formed in semiconductor substrate surface.
A further improvement is that being formed in the semiconductor substrate surface by gate oxide, the polysilicon layer is superimposed upon The gate oxide surface.
A further improvement is that the normobaric oxygen SiClx is formed using APCVD techniques.
A further improvement is that the boron-phosphorosilicate glass is formed using SACVD techniques.
A further improvement is that metal layer described in step 7 further includes the superimposed layer of titanium and titanium nitride, the metal layer Tungsten be formed on the superimposed layer of the titanium and titanium nitride.
The present invention under conditions of the etching technics for not changing polysilicon layer i.e. still using anisotropy carved by polysilicon layer Erosion forms the side step with vertical stratification, later thickeies the thickness of interlayer film during interlayer film is deposited, and utilizes The thickness of the interlayer film of thickening more than or equal to polysilicon structure side step height the characteristics of eliminate the side of polysilicon structure Influence of the face step to the pattern of the side of interlayer film carries out energy after annealing reflux by the boron-phosphorosilicate glass to interlayer film in this way It is enough that a complete inclined interlayer film side structure is formed at the side step of polysilicon structure；Forming inclined layer completely Between carry out the target thickness that interlayer film is thinned to needs by comprehensive wet etching again after film side structure, can finally eliminate more Metal residual at the side step of crystal silicon structure.
Description of the drawings
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments：
Figure 1A-Fig. 1 D are the device architecture schematic diagrames in each step of existing method；
Fig. 2 is the flow chart for the method that the embodiment of the present invention improves polysilicon step side metal residual；
Fig. 3 A- Fig. 3 E are the device architecture schematic diagrames in each step of present invention method.
Specific embodiment
As shown in Fig. 2, it is the flow chart for the method that the embodiment of the present invention improves polysilicon step side metal residual；Such as figure It is the device architecture schematic diagram in each step of present invention method shown in 3A to Fig. 3 E；The embodiment of the present invention improves polycrystalline The remaining method of silicon bench side metal includes the following steps：
Step 1: as shown in Figure 3A, forming polysilicon layer 3, forming photoetching offset plate figure 4 using photoetching process defines polycrystalline The forming region of silicon structure 31.Photoetching offset plate figure 4 is also marked in figure 3 a with PR.
In present invention method, polysilicon layer 3 described in step 1 is formed in Semiconductor substrate such as 1 table of silicon substrate Face.It is formed on 1 surface of Semiconductor substrate by gate oxide 2, the polysilicon layer 3 is superimposed upon 2 surface of gate oxide. The polysilicon structure 31 is polysilicon gate.
Preferably, the polysilicon gate is the polysilicon gate of ESD products.The ESD products are LDMOS device.It is described more The thickness of crystal silicon layer 3 is
Step 2: it is mask with the photoetching offset plate figure 4, using anisotropic etch process to described as shown in Figure 3B Polysilicon layer 3 performs etching the polysilicon structure 31, the perpendicular structure of side step of the polysilicon structure 31.
Step 3: as shown in Figure 3 C, deposit interlayer film 5；The interlayer film 5 is the folded of normobaric oxygen SiClx and boron-phosphorosilicate glass Add layer, the thickness of the interlayer film 5 is more than or equal to the height of the side step of the polysilicon structure 31.
Preferably, the thickness of the normobaric oxygen SiClx isThe thickness of the boron-phosphorosilicate glass is
The normobaric oxygen SiClx is formed using APCVD techniques.
The boron-phosphorosilicate glass is formed using SACVD techniques.
Step 4: as shown in Figure 3 C, annealing reflux is carried out to the boron-phosphorosilicate glass, pass through the interlayer in step 3 The thickness setting of film 5 make the boron-phosphorosilicate glass after reflux formed at the side step of the polysilicon structure 31 one it is complete The structure of full reclining.
Step 5: as shown in Figure 3 C, comprehensive wet etching is carried out to the interlayer film 5, by the thickness of the interlayer film 5 Target thickness is reduced to, the target thickness is less than the thickness of the polysilicon structure 31.
In present invention method, the target thickness of the interlayer film 5 isWet etching in step 5 is adopted It is controlled with Advanced process control table.
Step 6: the forming region of contact hole is defined using photoetching process, to the institute of the forming region of the contact hole It states interlayer film 5 and performs etching the opening to form the contact hole.
Step 7: as shown in FIGURE 3 E, forming metal layer, the contact hole is filled up completely by the metal layer；Into row metal The etching of layer all removes the metal layer outside the contact bore region, using the boron-phosphorosilicate glass in the polysilicon It is residual for metal of the completely inclined feature elimination at the side step of the polysilicon structure 31 at the side step of structure 31 It stays.
The material of the metal layer is tungsten.Preferably, the metal layer further includes the superimposed layer 6 of titanium and titanium nitride, described The tungsten of metal layer is formed on the superimposed layer of the titanium and titanium nitride.The etching of the metal layer uses dry etching.
Present invention method under conditions of the etching technics for not changing polysilicon layer 3 i.e. still adopt by polysilicon layer 3 The side step with vertical stratification is formed with anisotropic etching, later by interlayer film 5 during interlayer film 5 is deposited Thickness thickeies, using thickening interlayer film 5 thickness more than or equal to polysilicon structure 31 side step height the characteristics of disappear Except influence of the side step to the pattern of the side of interlayer film 5 of polysilicon structure 31, pass through the boron phosphorus silicon to interlayer film 5 in this way Glass can form complete inclined 5 side of interlayer film after carrying out annealing reflux at the side step of polysilicon structure 31 Structure；Comprehensive wet etching is carried out again after inclined 5 side structure of interlayer film completely is formed, and interlayer film 5 is thinned to needs Target thickness, the last metal residual that can be eliminated at the side step of polysilicon structure 31.
The present invention has been described in detail through specific embodiments, but these not form the limit to the present invention System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these also should It is considered as protection scope of the present invention.

Claims (15)

  1. A kind of 1. method for improving polysilicon step side metal residual, which is characterized in that include the following steps：
    Step 1: forming polysilicon layer, the forming region of polysilicon structure is defined using photoetching process formation photoetching offset plate figure；
    Step 2: using the photoetching offset plate figure as mask, the polysilicon layer is performed etching using anisotropic etch process The polysilicon structure, the perpendicular structure of side step of the polysilicon structure；
    Step 3: deposition interlayer film；The interlayer film is the superimposed layer of normobaric oxygen SiClx and boron-phosphorosilicate glass, the interlayer film Thickness is more than or equal to the height of the side step of the polysilicon structure；
    Step 4: carrying out annealing reflux to the boron-phosphorosilicate glass, made by the thickness setting of the interlayer film in step 3 The boron-phosphorosilicate glass after reflux forms a complete inclined structure at the side step of the polysilicon structure；
    Step 5: carrying out comprehensive wet etching to the interlayer film, the thickness of the interlayer film is reduced to target thickness, institute State the thickness that target thickness is less than the polysilicon structure；
    Step 6: the forming region of contact hole is defined using photoetching process, to the layer of the forming region of the contact hole Between film perform etching the opening to form the contact hole；
    Step 7: forming metal layer, the contact hole is filled up completely by the metal layer；The etching for carrying out metal layer connects described The metal layer outside contact hole region all removes, using the boron-phosphorosilicate glass at the side step of the polysilicon structure The metal residual at the side step of the polysilicon structure is eliminated for completely inclined feature.
  2. 2. improve the method for polysilicon step side metal residual as described in claim 1, it is characterised in that：The polysilicon Structure is polysilicon gate.
  3. 3. improve the method for polysilicon step side metal residual as claimed in claim 2, it is characterised in that：The polysilicon Grid are the polysilicon gate of ESD products.
  4. 4. improve the method for polysilicon step side metal residual as claimed in claim 3, it is characterised in that：The ESD productions Product are LDMOS device.
  5. 5. improve the method for polysilicon step side metal residual as described in claim 1, it is characterised in that：Institute in step 1 The thickness for stating polysilicon layer is
  6. 6. improve the method for polysilicon step side metal residual as claimed in claim 5, it is characterised in that：Institute in step 5 The target thickness for stating interlayer film is
  7. 7. the method as described in claim 1 or 6 for improving polysilicon step side metal residual, it is characterised in that：Step 5 In wet etching controlled using Advanced process control table.
  8. 8. improve the method for polysilicon step side metal residual as claimed in claim 5, it is characterised in that：Institute in step 3 The thickness for stating normobaric oxygen SiClx isThe thickness of the boron-phosphorosilicate glass is
  9. 9. improve the method for polysilicon step side metal residual as described in claim 1, it is characterised in that：Institute in step 7 The material for stating metal layer is tungsten.
  10. 10. improve the method for polysilicon step side metal residual as claimed in claim 9, it is characterised in that：The metal The etching of layer uses dry etching.
  11. 11. improve the method for polysilicon step side metal residual as claimed in claim 2, it is characterised in that：In step 1 The polysilicon layer is formed in semiconductor substrate surface.
  12. 12. improve the method for polysilicon step side metal residual as claimed in claim 11, it is characterised in that：Described half Conductor substrate surface is formed by gate oxide, and the polysilicon layer is superimposed upon the gate oxide surface.
  13. 13. improve the method for polysilicon step side metal residual as described in claim 1, it is characterised in that：The normal pressure Silica is formed using APCVD techniques.
  14. 14. improve the method for polysilicon step side metal residual as described in claim 1, it is characterised in that：The boron phosphorus Silica glass is formed using SACVD techniques.
  15. 15. improve the method for polysilicon step side metal residual as claimed in claim 9, it is characterised in that：In step 7 The metal layer further includes the superimposed layer of titanium and titanium nitride, and the tungsten of the metal layer is formed in the superimposed layer of the titanium and titanium nitride On.
CN201810024815.1A 2018-01-11 2018-01-11 Method for improving metal residue on side surface of polycrystalline silicon step Active CN108231543B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109148280A (en) * 2018-07-11 2019-01-04 上海华虹宏力半导体制造有限公司 Improve the method for polysilicon step side metal residual

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5132774A (en) * 1990-02-05 1992-07-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including interlayer insulating film
US5336640A (en) * 1991-01-28 1994-08-09 Kawasaki Steel Corporation Method of manufacturing a semiconductor device having an insulating layer composed of a BPSG film and a plasma-CVD silicon nitride film
US5455205A (en) * 1992-03-25 1995-10-03 Matsushita Electric Industrial Co., Ltd. Method of producing semiconductor device
CN102412153A (en) * 2010-09-26 2012-04-11 上海华虹Nec电子有限公司 Method for reducing gate resistance in LDMOS device
CN103855017A (en) * 2012-12-03 2014-06-11 上海华虹宏力半导体制造有限公司 Method for forming trench type double-layer-gate MOS structure two-layer polycrystalline silicon transverse isolation

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5132774A (en) * 1990-02-05 1992-07-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including interlayer insulating film
US5336640A (en) * 1991-01-28 1994-08-09 Kawasaki Steel Corporation Method of manufacturing a semiconductor device having an insulating layer composed of a BPSG film and a plasma-CVD silicon nitride film
US5455205A (en) * 1992-03-25 1995-10-03 Matsushita Electric Industrial Co., Ltd. Method of producing semiconductor device
CN102412153A (en) * 2010-09-26 2012-04-11 上海华虹Nec电子有限公司 Method for reducing gate resistance in LDMOS device
CN103855017A (en) * 2012-12-03 2014-06-11 上海华虹宏力半导体制造有限公司 Method for forming trench type double-layer-gate MOS structure two-layer polycrystalline silicon transverse isolation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109148280A (en) * 2018-07-11 2019-01-04 上海华虹宏力半导体制造有限公司 Improve the method for polysilicon step side metal residual

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