CN108107852A - A kind of algorithms library implementation method based on bus architecture - Google Patents
A kind of algorithms library implementation method based on bus architecture Download PDFInfo
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- CN108107852A CN108107852A CN201711189133.8A CN201711189133A CN108107852A CN 108107852 A CN108107852 A CN 108107852A CN 201711189133 A CN201711189133 A CN 201711189133A CN 108107852 A CN108107852 A CN 108107852A
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- 238000000034 method Methods 0.000 title claims abstract description 13
- 238000004364 calculation method Methods 0.000 claims abstract description 10
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 241000208340 Araliaceae Species 0.000 claims 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 claims 1
- 235000003140 Panax quinquefolius Nutrition 0.000 claims 1
- 235000008434 ginseng Nutrition 0.000 claims 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
- G05B19/41865—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] characterised by job scheduling, process planning, material flow
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/30—Nc systems
- G05B2219/32—Operator till task planning
- G05B2219/32252—Scheduling production, machining, job shop
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
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Abstract
The invention belongs to technical field of industrial control, and in particular to a kind of algorithms library implementation method based on bus architecture.All algorithmic blocks are on same bus in algoritic module storehouse, for algorithmic dispatching cell scheduling, complete the access of operational data, the calculating of assignment algorithm block；Specifically include following steps：Algoritic module storehouse receives the scheduling of algorithmic dispatching unit, and the algorithmic block that is scheduled obtains bus control right, starts algorithmic block operation, input data is obtained from bus, and type is converted to the form of needs；Each algorithmic block realizes that logical resource is multiplexed by shared arithmetic element, while is realized by multioperation unit and calculate parallelization；After calling shared arithmetic element and multioperation unit, result of calculation is obtained, the form of output data type is converted calculated result to, exports to bus, and discharge bus control right.The scheduling between different algorithmic blocks is realized using bus form, arithmetic speed is fast, operational reliability is high.
Description
Technical field
The invention belongs to technical field of industrial control, and in particular to a kind of algorithms library implementation method based on bus architecture.
Background technology
I＆C system is digitized, is the control axis of nuclear power station.Because its is efficient, failure rate is low, and the advantages such as easy care are adopted
Have become the trend of domestic and international nuclear power developing with digitlization I＆C system.In view of nuclear plant digital I＆C system is to safety
Property, reliability requirement it is high, be also most important, most difficult part in nuclear power domestic manufacture of key equipment at present.The realization of algorithms library is
The important component that table control system is realized is digitized, there is operational data amount is big, logic function is complicated, algorithm species is more etc.
Feature includes the basic operations such as logical operation, floating point math operation, temporal calculation and engineer application class such as PID control, RTD
The complex calculations such as temperature computation are the cores in digitlization table control system.
The realization of configuration algorithm at present is mainly：By the way that different algorithmic blocks is encapsulated in algorithms library, each algorithmic block
External interface is different, causes algorithms library internal schedule control complexity, algorithm performs efficiency is low, and each cycle operation time does not know
Shortcomings increase unnecessary workload.
The content of the invention
It is an object of the invention to provide a kind of algorithms library implementation methods based on bus architecture, have reliability height, calculate
Method execution efficiency is high, using it is flexible the features such as, the shortcomings that overcoming during traditional DCS system algorithm performs, improve DCS systems
The response speed of system.
In order to achieve the above objectives, the technical solution used in the present invention is：
A kind of algorithms library implementation method based on bus architecture, all algorithmic blocks are in same bus in algoritic module storehouse
On, for algorithmic dispatching cell scheduling, complete the access of operational data, the calculating of assignment algorithm block；Specifically include following steps：
The first step：Algoritic module storehouse receives the scheduling of algorithmic dispatching unit, and the algorithmic block that is scheduled obtains bus control right, opens
Algorithmic block operation is moved, input data is obtained from bus, and type is converted to the form of needs；
Second step：Each algorithmic block realizes that logical resource is multiplexed by shared arithmetic element, while passes through multioperation unit
It realizes and calculates parallelization；
3rd step：After calling shared arithmetic element and multioperation unit, result of calculation is obtained, result of calculation is turned
The form of output data type is changed to, is exported to bus, and discharges bus control right.
The shared arithmetic element includes parameter definition, state definition and control signal definition.
The multioperation unit includes single-precision floating point arithmetic element, arithmetic logic unit, fixed-point number computing list
Member and data type conversion unit；Single-precision floating point arithmetic element realizes IEEE754 single-precision format addition subtraction multiplication and division computings, compares
And integer data turns real-coded GA computing；Arithmetic logic unit realizes the and-or inverter logical operation function of parametrization；
Fixed-point number arithmetic element realizes the Qn form addition subtraction multiplication and division computings of parametrization；Data type conversion unit, which is realized, turns operational data
It is changed to the data of specified format.
Having the beneficial effect that acquired by the present invention：
The scheduling between different algorithmic blocks is realized using bus form, arithmetic speed is fast, operational reliability is high.Each calculation
Shared logic resource between method block, calculating process can greatly improve calculated performance with parallelization.
Description of the drawings
Fig. 1 realizes structure chart for algorithms library.
Specific embodiment
The present invention is described in detail with specific embodiment below in conjunction with the accompanying drawings.
All algorithmic blocks are on same bus in the present invention, for algorithmic dispatching cell scheduling, complete operational data
Access, the calculating of assignment algorithm block.
As shown in Figure 1, the algorithms library implementation method of the present invention based on bus architecture comprises the following steps：
The first step：Algoritic module storehouse receives the scheduling of algorithmic dispatching unit, and the algorithmic block that is scheduled obtains bus control right, opens
Algorithmic block operation is moved, input data is obtained from bus, and type is converted to the form of needs.
Second step：Each algorithmic block realizes that logical resource is multiplexed by shared arithmetic element, while passes through multioperation unit
It realizes and calculates parallelization to improve calculated performance.Shared arithmetic element mainly includes parameter definition, state definition and control signal
Definition etc..Multioperation unit includes single-precision floating point arithmetic element, arithmetic logic unit, fixed-point number arithmetic element and data
Type conversion unit.Single-precision floating point arithmetic element realizes IEEE754 single-precision format addition subtraction multiplication and division computings, including addition subtraction multiplication and division
Computing, compares and integer data turns real-coded GA computing；Arithmetic logic unit realizes that and-or inverter of parametrization etc. is patrolled
Collect calculation function；Fixed-point number arithmetic element realizes the Qn form addition subtraction multiplication and division computings of parametrization；Data type conversion unit is realized
Operational data is converted to the data of specified format.
3rd step：After calling shared arithmetic element and multioperation unit, result of calculation is obtained, result of calculation is turned
The form of output data type is changed to, is exported to bus, and discharges bus control right.
Claims (3)
1. a kind of algorithms library implementation method based on bus architecture, it is characterised in that：All algorithmic blocks are located in algoritic module storehouse
In on same bus, for algorithmic dispatching cell scheduling, the access of operational data, the calculating of assignment algorithm block are completed；Specific bag
Include following steps：
The first step：Algoritic module storehouse receives the scheduling of algorithmic dispatching unit, and the algorithmic block that is scheduled obtains bus control right, and starting should
Algorithmic block is run, and input data is obtained from bus, and type is converted to the form of needs；
Second step：Each algorithmic block realizes that logical resource is multiplexed by shared arithmetic element, while is realized by multioperation unit
Calculate parallelization；
3rd step：After calling shared arithmetic element and multioperation unit, result of calculation is obtained, is converted calculated result to
The form of output data type, exports to bus, and discharges bus control right.
2. the algorithms library implementation method according to claim 1 based on bus architecture, it is characterised in that：The shared fortune
Calculating unit includes parameter definition, state definition and control signal definition.
3. the algorithms library implementation method according to claim 1 based on bus architecture, it is characterised in that：The multioperation
Unit includes single-precision floating point arithmetic element, arithmetic logic unit, fixed-point number arithmetic element and data type conversion unit；
Single-precision floating point arithmetic element realizes IEEE754 single-precision format addition subtraction multiplication and division computings, compares and integer data turns floating type
Data operation；Arithmetic logic unit realizes the and-or inverter logical operation function of parametrization；Fixed-point number arithmetic element realizes ginseng
The Qn form addition subtraction multiplication and division computings of numberization；Data type conversion unit realizes the data that operational data is converted to specified format.
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| CN201711189133.8A CN108107852A (en) | 2017-11-24 | 2017-11-24 | A kind of algorithms library implementation method based on bus architecture |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711189133.8A CN108107852A (en) | 2017-11-24 | 2017-11-24 | A kind of algorithms library implementation method based on bus architecture |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050071031A1 (en) * | 2003-09-26 | 2005-03-31 | Taiwan Semiconductor Manufacturing Co. | Algorithms tunning for dynamic lot dispatching in wafer and chip probing |
| CN101141339A (en) * | 2007-02-09 | 2008-03-12 | 江苏怡丰通信设备有限公司 | Embedded SoC chip based wireless network industry monitoring management system |
| CN102393656A (en) * | 2011-11-29 | 2012-03-28 | 北京邮电大学 | Embedded multinuclear main controller of modular robot based on FPGA (Field Programmable Gata Array) |
| CN102438338A (en) * | 2011-12-14 | 2012-05-02 | 北京邮电大学 | Base station based on multicore general processor for broadband mobile communication system |
| CN103778013A (en) * | 2014-01-24 | 2014-05-07 | 中国科学院空间应用工程与技术中心 | Multi-channel Nand Flash controller and control method for same |
| CN105824769A (en) * | 2016-03-14 | 2016-08-03 | 合肥工业大学 | Configurable dynamical time slice round-robin scheduling algorithm |
-
2017
- 2017-11-24 CN CN201711189133.8A patent/CN108107852A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050071031A1 (en) * | 2003-09-26 | 2005-03-31 | Taiwan Semiconductor Manufacturing Co. | Algorithms tunning for dynamic lot dispatching in wafer and chip probing |
| CN101141339A (en) * | 2007-02-09 | 2008-03-12 | 江苏怡丰通信设备有限公司 | Embedded SoC chip based wireless network industry monitoring management system |
| CN102393656A (en) * | 2011-11-29 | 2012-03-28 | 北京邮电大学 | Embedded multinuclear main controller of modular robot based on FPGA (Field Programmable Gata Array) |
| CN102438338A (en) * | 2011-12-14 | 2012-05-02 | 北京邮电大学 | Base station based on multicore general processor for broadband mobile communication system |
| CN103778013A (en) * | 2014-01-24 | 2014-05-07 | 中国科学院空间应用工程与技术中心 | Multi-channel Nand Flash controller and control method for same |
| CN105824769A (en) * | 2016-03-14 | 2016-08-03 | 合肥工业大学 | Configurable dynamical time slice round-robin scheduling algorithm |
Non-Patent Citations (1)
| Title |
|---|
| 刘志凯 等: ""一种基于FPGA的算法组态技术在安全级数字化I&C中的应用"", 《仪器仪表用户》 * |
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Application publication date: 20180601 |