CN108028277A - The contact of semiconductor device of contact area with increase - Google Patents

The contact of semiconductor device of contact area with increase Download PDF

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Publication number
CN108028277A
CN108028277A CN201580083356.9A CN201580083356A CN108028277A CN 108028277 A CN108028277 A CN 108028277A CN 201580083356 A CN201580083356 A CN 201580083356A CN 108028277 A CN108028277 A CN 108028277A
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Prior art keywords
groove
gate
fin
offset spacers
source electrode
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CN201580083356.9A
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CN108028277B (en
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R.梅汉德鲁
T.加尼
廖思雅
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Intel Corp
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Intel Corp
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    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Abstract

Semiconductor contact framework is provided, wherein contacting metal is extended in the semiconductor layer contacted, thus increases contact area.Offset spacers portion allows for the relatively deep etching in semi-conducting material.Therefore, it is not that the flat horizontal surface of only semiconductor is exposed to contact area, but relatively long vertical trench sidewalls and bottom wall are exposed and can be used for contact area.Then the groove can be filled using desired contacting metal.It can implement the doping that contact is formed into semiconductor layer therein in a manner of promoting high-efficient contact groove etching process, such as by, for example, being adulterated after trench etch or there is following semiconductor layer：Contact trench etches passed through top undoped with area and lower part doping S/D areas.The offset spacers portion can be removed from final structure.

Description

The contact of semiconductor device of contact area with increase
Technical field
The present invention relates to the contact of semiconductor device of the contact area with increase.
Background technology
Including transistor, diode, resistor, the capacitor and other are passive and active formed on a semiconductor substrate The performance of the increase of the circuit devcie of electronic device typically considers main during the design, manufacture and operation of those devices Factor.For example, in metal-oxide semiconductor (MOS)（MOS）Transistor semiconductor device（Such as in complementary metal oxide semiconductor （CMOS）Those used in technique）Design and manufacture during, it is often desirable to minimize with otherwise referred to as non-essential resistance Rext The associated dead resistance of contact.The R of reductionextRealize the higher driving current from the design of identical crystal pipe.
Brief description of the drawings
Fig. 1 a and nonplanar semiconductor device of the 1b diagrams with the contact framework configured according to one embodiment of the disclosure The viewgraph of cross-section of part.
Fig. 2 a and nonplanar semiconductor device of the 2b diagrams with the contact framework configured according to another embodiment of the present disclosure The viewgraph of cross-section of part.
Fig. 3 a are until each in 3d is illustrated with the contact framework configured according to another embodiment of the present disclosure The viewgraph of cross-section of non-planar semiconductor device.
Each in Fig. 4 a and 4b is illustrated has contact framework and selection according to one embodiment of the disclosure The viewgraph of cross-section of the non-planar semiconductor device of property impure source/drain region.
Fig. 5 a are until 5g illustrates the side for being used to manufacture semiconductor contact framework of one embodiment according to the disclosure jointly Method.
Fig. 6 a and nonplanar semiconductor device of the 6b diagrams with the contact framework configured according to another embodiment of the present disclosure The viewgraph of cross-section of part.
Fig. 6 c show the perspective view of the example embodiment shown in Fig. 6 a and 6b.
Fig. 6 d illustrate Fig. 6 a according to some such embodiments until the offset spacers portion shown in 6c and contacting metal The various top-down views for the example shapes that may have.
Fig. 7 a and nonplanar semiconductor device of the 7b diagrams with the contact framework configured according to another embodiment of the present disclosure The viewgraph of cross-section of part.
Fig. 7 c show the perspective view of the example embodiment shown in Fig. 7 a and 7b.
Fig. 7 d illustrate Fig. 7 a according to some such embodiments until the offset spacers portion shown in 7c and contacting metal The various top-down views for the example shapes that may have.
Fig. 8 a and nonplanar semiconductor device of the 8b diagrams with the contact framework configured according to another embodiment of the present disclosure The viewgraph of cross-section of part.
Fig. 8 c show the perspective view of the example embodiment shown in Fig. 8 a and 8b.
Fig. 8 d illustrate Fig. 8 a according to some such embodiments up to what the contacting metal shown in 8c may have shows The various top-down views of example shape.
The calculating system that Fig. 9 diagrams are implemented using the one or more integrated circuit structures configured in accordance with an embodiment of the present disclosure System.
As will be appreciated that, figure is not necessarily to scale specifically matches somebody with somebody to draw or be intended to by what the disclosure was limited to show Put.For example, although some figures are indicated generally at straight line, right angle and smooth surface, it is contemplated that used processing equipment and skill The real world limitation of art, the actual implementation of structure may have not perfect straight line, right angle, and some features may have There is surface topology or be in addition non-smooth.Briefly, which is merely provided for showing exemplary construction.
Embodiment
Disclose the semiconductor contact frame with contact area and low resistance relatively large for Standard contact Structure.Standard contact in MOS transistor is usually contacted using exposed doped semiconductor area, wherein total contact area It is horizontal and is limited by the semiconductor area of top-down exposure.In contrast, according to the disclosure a implementation The contact framework of example configuration provides increased contact area, so that contact is extended in the semiconductor layer just contacted.Root According to an example embodiment, offset spacers portion is used during formation is contacted, it has the effect for allowing to perform selective etch. Especially, lower layer semiconductor layers are etched with the faster speed of ratio deviation spacer portion material, so as to allow for semi-conducting material In other parts of the relatively deep etching without etching away transistor arrangement.Therefore, the single flat of only semiconductor it is not Horizontal surface is exposed to contact area, but relatively long vertical trench sidewalls and bottom wall are exposed and can be used for contacting Area.Then the groove can be filled using desired contacting metal.Can be in a manner of promoting contact trench etch process To implement the doping that contact is formed into semiconductor layer therein.For example, under a sample situation, it is formed in contact trench The doping semiconductor layer afterwards but before contacting metal is deposited in groove, and another sample situation lower semiconductor layer by with Be equipped with contact trench etching by through undoped with part and the local doping lower part portion that is extended to close to contact trench Point.In certain embodiments, contact framework is formed on source/drain（S/D）It is whole between Qu Shang, wherein neighboring gate structures A space limits critical level distance（CD）, and total contact area is more than CD4 times or more.It is to be noted, that in some embodiments In, which is likely to be present in final transistor arrangement, but in other embodiments, which may It is removed during groove etching process or after trench etch is completed.
Overview
As previously explained, the driving current increased in transistor can be realized by reducing device resistance.Contact resistance A big chunk of the all-in resistance of device is become.Typical transistors contact, which stacks, includes such as silicon or SiGe（SiGe）Source electrode/ Drain electrode layer, nickel silicide layer, titanium nitride adhesion layer and tungsten contact/pad.In any such configuration, contact area usually limits In the flat area of the semi-conducting material of exposure during contact trench etch process.As in view of the disclosure will be appreciated that, deposit It can be formed on the limited areal of contact.For example, the grid from a gate spacer portion to adjacent transistor can be passed through First distance of pole spacer portion（Referred to herein as CD）It is multiplied by the second distance for the width for limiting source/drain regions（At this It is referred to as W in text1）To limit the whole area between neighboring gate structures.Therefore, top-down source drain is relied on to open The common contact of mouth has about CD x W1Contact area.
Therefore, and in accordance with an embodiment of the present disclosure, there is provided contact forms technology, it is connect using offset spacers portion to increase Contacting surface is accumulated, so that contact is extended in the semiconductor layer just contacted.According to an example embodiment, the offset spacers portion The effect of the bushing or mask of material is effectively acted as in the opening of contact trench.For being implemented into the contact in semiconductor layer The etch chemistries of trench etch can be relative to offset spacers portion material and other non-target materials（Surround source/drain The insulating material in area）With selectivity, or otherwise it is configured to the speed lower than aimed semiconductor material Etch offset spacers portion's material and any other non-target materials.In view of the disclosure, many selective etch schemes will be apparent 's.The offset spacers portion allow for relatively deep etching into semi-conducting material without etch away transistor arrangement other Part.Therefore, it is not that the single flat horizontal surface of only semiconductor is exposed to contact area, but it is relatively long vertical Trenched side-wall and bottom wall are exposed and can be used for contact area.Once semiconductor layer is doped, it is possible to is connect using desired Tactile metal fills groove.Offset spacers portion need not be retained in final structure.
It can implement contact in a manner of promoting contact trench etch process and be formed into mixing for semiconductor layer therein It is miscellaneous.For example, under a sample situation, mixed after contact trench is formed but before contacting metal is deposited in groove Miscellaneous semiconductor layer, such as by injecting doping and annealing process.Under another sample situation, semiconductor layer is formed or with it His mode be configured with contact trench etching by through undoped upper part and the arrived doping lower part of contact trench extension Part.In another embodiment, semiconductor layer is configured with gradual concentration of dopant, its at the top of the groove without adulterating Or in addition it is lightly doped and changes between the target doped level at channel bottom.As in view of the disclosure will be appreciated that, eliminate or Etching contact trench may be made it is easier to by otherwise reducing the doping in semiconductor layer（What etching had been doped partly leads Body material may be more difficult than etching identical undoped semi-conducting material）.In also other embodiment, can use do not know The etching scheme of any doped level in road.
Depending on target contact area, the depth of contact trench etching can be because of embodiment and different.According to an example reality Example is applied, which is the function of gash depth and usually can such as be calculated according to equation 1：
Contact area=[(2 x Hc) + (CD - (2 x W2))] x W1（Equation 1）
H hereincIt is contact height, CDIt is the gate spacer stacked from the gate spacer portion of a gate stack to neighboring gates The distance in portion, W2It is offset spacers portion thickness（If present）, and W1It is the distance for the width for limiting source/drain regions. In some cases, contact etch depth is in the range of 50% or more of fin height, wherein example fin height （HF）It is in the range of 30nm to 50nm, although any number of fin geometric figure and it is not intended that sheet can be used It is open be limited to it is any specific one.In a specific embodiment, contact trench is etched so as to incision gate structure, to permit Perhaps the dopant injection in incision.Such incision etching and doping injection between source/drain regions and channel region can be into One step helps to reduce the all-in resistance of MOS device.For example, after dopant can be injected into source/drain regions and can implement It is continuous to anneal to make dopant be spread towards channel region.
It is to be noted, that source/drain regions are probably primary fin material or epitaxial deposition or otherwise supply Replace source/drain material.It is further noted that depend on process node and device density, W1、W2And CDIn each can Can be because of embodiment and different.As will be appreciated that, technology provided herein can dramatically increase contact area, especially when device ruler During very little reduced and use more wide aspect ratio fin.Under a sample situation using 45nm fins, it is assumed that have The contact trench opening of 15nm, then can make contact area increase to up to 4 times, wherein connecing by using offset spacers portion technology Tactile groove is in the scope of 20nm to 30nm depths, or deeper.The technology can lift device by reducing contact resistance Performance, so as to allow every watt of better performance.For this reason, simulation is shown compared with typically contacting framework, for according to one The contact about 17% or better performance gain of a little embodiment configurations.
The shape of contact trench can be different because of embodiment, and will depend on such as used mask pattern and etching Chemical substance, the semi-conducting material being etched, offset spacers portion material and whether it is expected incision etch（Source/drain herein Polar region is at least partially in may extend below gate spacer portion and below gate-dielectric）Etc factor.It can use Any appropriate etching technique（Including dry method and/or wet etching, isotropism and/or anisotropy or some groups Close）To complete to etch.Further point out below offset spacers portion and/or grid that there may be incision.Any number can be produced Purpose contact trench shape（Give some instances, for example, it is square, rectangle, ellipse, circle, angular）.It is further noted that depend on In the certain cross section profile checked, groove shape may be further change in（For example, parallel with fin and pass through fin The cross section profile that obtained cross-sectional profiles may be visually different from perpendicular to fin and be obtained by source/drain regions）. Can for example it be detected using transmission electron microscopy and scanning electron microscopy or other appropriate imaging techniques according to this public affairs The contact structures that the embodiment opened is formed, to show to extend to the contact of the metal in the semi-conducting material just contacted.
Method and framework
Fig. 1 a and non-planar semiconductor device of the 1b diagrams with the contact framework configured according to one embodiment of the disclosure Viewgraph of cross-section.Especially, Fig. 1 a show perpendicular to fin and cut through the viewgraph of cross-section that source/drain regions obtain, and scheme Viewgraph of cross-section obtained from 1b shows parallel to fin and cuts through fin and gate regions.Point out not every typical case Device feature is all illustrated, to allow to focus on contact framework.The device can be for example with multiple MOS transistors（It is all As FinFET or nano wire are configured）Integrated circuit device, or other on-plane surface devices of generally use fin-shaped semiconductor body Part.FinFET is in thin semi-conducting material band（Commonly known as fin）The transistor of surrounding structure.The transistor bag Include the field-effect transistor of standard（FET）Grid, source area and drain region on node, including raceway groove.The conductive ditch of the device Road resided on the outside of the fin below grid/within.Specifically, two side walls of the electric current along fin（Vertically In the side of substrate surface）And/or flowed within the two side walls, also along the top of fin（Parallel to substrate surface Side）And/or at the top of this within flow.Because the conducting channel of such configuration is essentially along three differences of the fin Outer planar area/within the plane area be resident, so this FinFET design is sometimes referred to as three grid FinFET.Other classes The FinFET configurations of type are also available, such as so-called bigrid FinFET（Wherein, conducting channel is mainly only along fin The two side walls of shape thing（And will not be along the top of fin）/ be resident within the two side walls）.Nano-wire transistor （Sometimes referred to as grid surrounds FET entirely）It is very similarly configured, but fin is that instead of, and use nano wire or nanobelt （Thickness depending on line）And grid material is usually on all sides around channel region.Depending on particular design, nano wire are brilliant Body pipe, which has, is for example up to 4 effective grids.Provided herein is contact technique can match somebody with somebody with any such non-planar transistor Put and be used together, although other configurations may also be benefited.
As that can see in Fig. 1 a and 1b, which includes fin 101, is formed on many gate structures 109 together with the either side to each grid source/drain regions 105.As is commonly done, the raceway groove of the device usually exists Below grid and between source area and drain region.Each gate structure 109 usually includes gate spacer portion 109a, grid Electrode 109b and gate-dielectric 109c, as will be appreciated that, which can will replace metal gate later Pole（RMG）The dummy gate electrode being replaced in technique（Polysilicon electrode）Or actual metal gate structure, this depends on desired work Skill flow.
As it can further be seen that, provide offset spacers portion 111 in contact trench opening, and in source/drain Metal contact 107 is formed in the contact trench of each in area 105.Contact extended distance HCTo the half of source/drain regions 105 In conductor material.In fig 1 a, to point out that source/drain regions 105 effectively occupy the whole sky between adjacent separation layer 103 Between.The distance between separation layer 103 is designated as W1.In addition and with reference to figure 1b, it is pointed out that in this example embodiment, Source/drain regions 105 effectively occupy the whole space between neighboring gate structures 109.The distance between gate structure 109 It is designated as CD.Other embodiment can include the further insulator material between S/D areas 105 and gate structure 109.As in view of What the disclosure will be appreciated that, these sizes HC、W1、CDIt can be used to contact of the estimation according to the contact structures of one embodiment Area.Depth on etching, it is also contemplated that fin height HF。
Can be different because of embodiment for manufacturing the material of the various features of shown transistor device, and be not intended to The disclosure is limited to any certain material system.For example, silicon, germanium, SiGe can be utilized（SiGe）Or III-V material（Such as arsenic Change gallium, indium arsenide etc.）Substrate implements some embodiments, forms many fins 101 over the substrate.Other embodiment can To use semiconductor-on-insulator（SOI）Or multi-layer substrate structure is provided with some desired qualities（For example, low sub- fin-shaped Thing is revealed）Fin.In a most general sense, according to embodiment can use on it can be formed such as FinFET and Any appropriate substrate of the nonplanar device of nano-wire transistor etc.
The fin 101 is probably the primary replacement fin either provided by recessed and replacement technique of substrate, This is recessed and replaces technique including removing primary fin material and replacing it using the expectation material of arbitrary composition.Example Such as, under a sample situation, substrate is bulk silicon substrate and fin 100 is primary silicon fin, or SiGe （SiGe）Replace fin or III-V material replaces fin or combination that is primary and replacing fin.Further note , in some example embodiments, fin 100 can be etched or otherwise be processed into channel region One or more nanometer line or belts surround device entirely in order to provide grid.It is to be noted, that in the specific context to nano wire or The reference of line is intended to include line and other of band or line derivative.It is further noted that band is typically the line of relative thin.
It can implement gate structure using standard material and formation technology.For example, gate spacer portion 109a can be Silica or silicon nitride or any other appropriate spacer portion material.Gate-dielectric 109c can be for example by such as silica Or the material of high-k dielectric material etc is formed.The example of high k gate dielectric materials includes such as hafnium oxide, hafnium oxide Silicon, lanthana, aluminium oxide lanthanum, zirconium oxide, silicic acid Zirconium oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanates, Yittrium oxide, aluminium oxide, lead scandium tantalum pentoxide and lead zinc niobate.Gate electrode 109b materials can be later as previously explained The expendable material that a part as RMG techniques is removed（Such as polysilicon）Or gate electrode material（Such as aluminium, tungsten, Titanium, tantalum, nickel, platinum, highly doped silicon, the silicide of one of these（Such as titanium silicide, nickle silicide etc.）Or such material The combination of layer）.
The source/drain regions 105 can also be primary fin material or alternate material, this depends on desired device group Compound.In an example embodiment, which is original silicon or is doped to provide expectation polarity（PMOS or NMOS）Other substrate materials.As in view of the disclosure will be appreciated that, according to some such embodiments, doping can connect Tactile trench etch is implemented after being performed, so that dopant will be without prejudice to etch process.In another example embodiment, source Pole/drain region 105 is the epitaxial depositions of SiGe into the primary silicon fin base of PMOS device or on it, and III-V Material（Such as indium arsenide）Epitaxial deposition into the primary silicon fin base of nmos device or on it.In certain situation Under, epi dopant, which occupies to have, passes through width W1With critical dimension CDThe space of the area of restriction.It is to be noted, that CDActually from One visual angle is seen（The cross section obtained parallel to fin）Source/drain regions 105 width, and W1Actually from another One visual angle is seen（Perpendicular to the cross section that fin obtains）Source/drain regions 105 width.The depth of epitaxial deposition can be with It is for example to the bottom of fin, either crosses the bottom of fin into underlying substrate or to above fin bottom A certain position（To leave fin base, extension is on the fin base）.Can use any number of source electrode/ Drain configuration, and it is not intended that the disclosure is limited to any particular types.
111 material of offset spacers portion can be any material, it is for giving etch chemistries compared with being etched The semi-conducting material of source/drain regions 105, will either provide a degree of etching selectivity or otherwise etch It is slower.For example, in an example embodiment, utilize silicon nitride（SiN）To implement the offset spacers portion 111, the silicon nitride （SiN）With the etch-rate lower than the silicon using standard etch chemistries.It is to be noted, that offset in certain embodiments 111 material of spacer portion can be with gate spacer portion 109a material identicals, but need not be identical, and in other embodiment In can be different materials.Any number of oxide or nitride or other appropriate offset spacers portion materials can be used To implement offset spacers portion 111.
Contacting metal 107 may, for example, be the metal identical with gate electrode 109b, such as aluminium, tungsten, titanium, tantalum, nickel, platinum, Highly doped silicon, the silicide of one of these（For example, titanium silicide, nickle silicide etc.）Or the combination of such material layer, but It can also be different, the germanide such as in the case of the source/drain regions 105 containing germanium（Such as titanium germanide, nickel Germanide etc.）.Any number of contacting metal material can be used, and is not intended to the disclosure being limited to any specific contact Metal solution.As long as the contact area interface between source/drain regions 105 and contacting metal 107 can be extended, such as herein Description.
In the example embodiment shown in Fig. 1 a-b, in two cross-sectional profiles shown, contacting metal 107 is phase To rectangular shape.However, many groove shapes can be produced by depending on used material, mask pattern and etching scheme, And any such shape can be used to provide increased contact area as described in this article.So, for example, The rectangle groove shape shown in the viewgraph of cross-section of Fig. 1 b may be produced for example by orienting anisotropic etching, and be had The groove shape for having angle wall as shown in the viewgraph of cross-section of Fig. 2 b may be produced for example by isotropic etching.Refer to Go out, in these example embodiments, the viewgraph of cross-section of the groove shown in Fig. 1 a and 2a looks like identical.Further refer to Go out, be sightless in the viewgraph of cross-section that offset spacers portion 111 is shown in Fig. 1 a and 2a in this particular example, and its His embodiment offset spacers portion 111 may be visible in that viewgraph of cross-section, as and then by as explain.Fig. 2 a Those shown in Fig. 1 a and 1b are similar to other features of 2b, and previous relevant discussion is equally applicable to Fig. 2 a- b。
Fig. 3 a are until each in 3d is illustrated with the contact framework configured according to another embodiment of the present disclosure The viewgraph of cross-section of non-planar semiconductor device.As that can see in fig. 3 a, the contact trench etching of use provides and figure The similar groove shape shown in 1b, except further using incision etching so that etching face in source/drain regions 105 Product extension exceeds the opening in offset spacers portion 111.Such incision etching is probably desired, such as to further expand Contact area at contact trench bottom.Incision etched pattern can be for example by using the initial orientation to pass through offset spacers portion Etching is afterwards isotropic etching to realize.Alternatively, incision etched pattern can be with selected materials and etch chemistries And become, such as source/drain material is etched than it in used given etch chemistries etching spacer portion offset material In the case that aggressiveness is much smaller.For example, potassium hydroxide（KOH）It can be used to have aggressively by SiN offset spacers relatively Portion 111 comes the source/drain regions 105 of etching silicon-containing, in order to provide incision pattern as shown.Fig. 3 b are shown using less fixed To similar pattern made of, more isotropic etchings.Each in Fig. 3 c and 3d shows issuable another example Etched pattern.What many other possible etched patterns with and without incision feature will be apparent, and be not intended to by The disclosure is limited to any special etch pattern.
Each in Fig. 4 a and 4b is illustrated has contact framework and selection according to one embodiment of the disclosure The viewgraph of cross-section of the non-planar semiconductor device of property impure source/drain region.As previously explained, in general, mix Miscellaneous semi-conducting material may be more difficult to etch than undoped semi-conducting material.As such, can using such as doped scheme provided herein Implement contact trench etch process to allow in a more efficient manner.For example, and with reference to figure 4a, to source/drain regions 105 Gradual concentration of dopant is provided, its non-impurity-doped at the top of source/drain regions 105 or be in addition lightly doped with close to source Change between the target doped level of the bottom of pole/drain region 105.In the example of Fig. 4 b, the source/drain regions 105 by with Top is equipped with undoped with part and lower part doped portion.Doping target can be set based on intended application and performance purpose.Connect Part can more be lightly doped to pass through the undoped of semi-conducting material or in addition and start in target dopant level for tactile groove Position at or surrounding stop.In another embodiment（Shown in such as Fig. 5 f）, can be carried out in groove etching process Source/drain regions 105 are doped afterwards but before contacting metal is deposited.In view of the disclosure, many doped schemes will It is obvious.
Fig. 5 a are until 5g illustrates the side for being used to manufacture semiconductor contact framework of one embodiment according to the disclosure jointly Method.It is to be noted, that each in Fig. 5 a-g shows parallel to fin and cuts through transversal obtained from fin and gate regions Face view.As that can see in fig 5 a, in the manned technique of semi-conducting material for forming source/drain regions 105 Exemplary construction is shown at point, no matter its be as primary fin material semi-conducting material or replace semi-conducting material.Source The semi-conducting material in pole/drain region 105 can be doped, is undoped or so that a part of undoped or another More it is lightly doped outside.In general, 105 semi-conducting materials of S/D contacted with contacting metal 107 are most doped at last.For example, In certain embodiments, undoped semiconductor may initially be used to promote contact trench etching, wherein undoped S/D 105 semi-conducting materials can be then doped after the trenches are formed, as discussed by and then on Fig. 5 f.As explained previously , the structure can be implemented using any number of material system and formation process.In an example embodiment, use is recessed Supply the semi-conducting material in source/drain regions 105 into etching and replacing technique, wherein primary sacrifice silicon fin serve as it is pre- Position is stayed, the reserved location is removed and is replaced using the epitaxial deposition of such as germanium, SiGe or III-V material.One In a little embodiments, multiple fin-shaped compositions can be provided on substrate, such as PMOS device SiGe fins and/or Primary silicon fin for nmos device and/or the III-V material fin for nmos device.
Fig. 5 b show the resulting structure after being recessed into according to one embodiment in source/drain regions 105. Can be recessed to implement this using any appropriate dry method and/or wet etching, this depends on material system in place, and such as As it will be appreciated that.Etching may have selectivity to the material of the semi-conducting material different from forming source/drain regions 105 （Etch source/drain regions 105 but do not etch the non-target materials of 109 material of gate structure and any other exposure）.Alternatively Ground, the recessed period in source/drain regions 105, the gate structure 109 and any other non-targeted surface can be masked Fall.Under a sample situation, anisotropy is used（Or isotropism）KOH is etched to implement etching so that silicon source/drain electrode Area 105 is recessed, and wherein gate spacer portion 109a is silicon nitride and gate electrode 109b is polysilicon or has selectivity to KOH Other metals.Many other etchings and material solution can be used.It is to be noted, that in this example embodiment, source/drain regions 105 take entirely distance CD, and may have the width W for desirably setting and being suitable for given device target1.Other Embodiment can have different 105 sizes of S/D areas.
According to one embodiment, once source/drain regions 105 are recessed into, which continues to deposition offset spacers portion material Material 111, as shown in Fig. 5 c.Can be heavy to implement this using any number of appropriate offset spacers portion material and depositing operation Product.Under a sample situation, for example, using low-pressure chemical vapor deposition（LPCVD）Or the chemical gaseous phase of plasma enhancing Deposition（PECVD）Technique deposits to SiN in groove.Many other depositions and material solution can be used.It is to be noted, that deposition Offset spacers portion layer 111 be shown as being conformal in nature, but be so not required.Such as can be in the sample situation It is lower it is further seen that, which has thickness W2.In the case of a specific example, gate spacer portion 109a SiN and offset spacers portion is also SiN, it is selectively deposited in groove using LPCVD or pecvd process but only heavy On product gate spacer portion 109a materials.In such an embodiment, it may not be necessary to the spacer portion material shown in figure 5d The etching of material 111.
Fig. 5 d show to be etched in offset spacers portion that is conformal or otherwise depositing material 111 according to one embodiment To provide the structure that the result after sleeve-like offset spacers portion 111 obtains.The bushing can cover ditch in certain embodiments The all surface of channel opening is to provide continuous rings of material, but the offset spacers portion 111 is only in groove in other embodiments On some surfaces of opening, 109 part of gate spacer portion of such as groove, as explained previously with reference to Fig. 5 c.And then will ginseng Fig. 6 a are examined until 8d discusses the other details of the configuration of example offset spacers portion 111.Can use any appropriate dry method and/or Wet etching implements the etching, this depends on material system in place, and as it will be appreciated that as.Etching may be to not The material for being same as offset spacers portion material 111 has selectivity（Etch offset spacers portion material 111 but do not etch grid knot 109 material of structure or the non-target materials of other exposures）.Alternatively, in the recessed period of offset spacers portion material 111, the grid Structure 109 can it is masked fall.Under a sample situation, there is N via using2CHF3Dry anisotropic plasma The etching is implemented in body etching, and wherein gate spacer portion 109a is silica and gate electrode 109b is polysilicon or right CHF3Other selective metals.Many other appropriate etchings and material solution can be used.
Once offset spacers portion 111 is in place, this method can continue contact trench etching into source/drain regions 105 Semi-conducting material in.Fig. 5 e show the resulting knot after contact trench has been etched according to one embodiment Structure.It can implement the etching using any appropriate dry method and/or wet etching, this depends on material system in place, and And as will be appreciated that.The depth of the etching can be because of embodiment and different.For example, in certain embodiments, the groove Depth is 30% or total vertical length of at least 25% or total vertical length of total vertical length of corresponding source/drain regions 50% or total vertical length of 45% or total vertical length of 40% or total vertical length of 35% or total vertical length 55%, Or the 75% or total of 70% or total vertical length of 65% or total vertical length of 60% or total vertical length of total vertical length The 95% or total of 90% or total vertical length of 85% or total vertical length of 80% or total vertical length of vertical length is vertical The 100% of length.It is to be noted, that may look like for forming the etching of contact trench for making the recessed etching of source drain area, And the previous relevant discussion on Fig. 5 b is equally applicable to here.Under a sample situation, lost using anisotropy KOH Carve to implement the etching so that silicon source/drain region 105 is recessed, wherein gate spacer portion 109a and offset spacers portion 111 are nitrogen SiClx, and gate electrode 109b is polysilicon or to other selective metals of KOH.Under another sample situation, make With anisotropy sulfur hexafluoride（SF6）Or Nitrogen trifluoride（NF3）To implement the etching, between wherein gate spacer portion 109a and offset It is silicon nitride every portion 111 and gate electrode 109b is polysilicon or to SF6Or NF3Other selective metals.Such as high-ranking military officer It can arrive, many other appropriate etchings and material solution can be used.As can in the illustrated case it is further seen that, It is to be noted, that the result as etching can change 111 thickness W of offset spacers portion2, W is generally designated as in Fig. 5 e2'.More one As in the sense that, the result as etching can change the global shape in offset spacers portion, and in some example embodiments, Result offset spacers portion 111 as etching is substantially removed or is otherwise reduced.However, other embodiment may Thickness W is not changed2。
Fig. 5 f show to be injected dopant according to one embodiment experience in the source/drain regions 105 being etched and right The structure of the technique for the contact doping for performing annealing afterwards to be lifted at semiconductor-metal interface.As is commonly done, may be used To select dopant material based on desired polarity.In an example embodiment, using ion or wait after the trenches are formed Gas ions injection technology is doped the source/drain regions 105 etched, and uses process annealing and/or SPER（Solid phase Epitaxial regrowth）Come to it into line activating.Any number of known injection and annealing technology can be used.There are other implementations In example, doped and undoped part can be configured with by remembering the semiconductor layer of source/drain regions 105, or is configured with slow The concentration of dopant of change, as explained earlier.
Fig. 5 g show the resulting structure after contacting metal is deposited and is polished according to one embodiment.Can be with Implement the deposition using any number of appropriate metallic contact material and depositing operation.Can via such as sputtering deposit or CVD carrys out depositing contact metal.Deposition after annealing can be used to cause the underlying semiconductor in metal and source/drain regions 105 Reaction between material（Such as silicide or germanide are formed）.The examples material previously pointed out, or contact layer can be used Combination.Many configurations can be used.It is to be noted, that contacting metal fills whole contact trench, although because being such as attributed to nothing The hole of meaning or the whatsoever reason of other defect, filling may not be perfect（Groove is by 100% filling herein）.For This, the reference to the contact trench of " significantly " filling herein is intended to include perfect filling and imperfect filling, it has certain Kind of degree without the groove filled with contact material（For example, 10% or less or 5% or less or 2% or less or Person 1% or less）.
Fig. 6 a and nonplanar semiconductor device of the 6b diagrams with the contact framework configured according to another embodiment of the present disclosure The viewgraph of cross-section of part.The embodiment is similar to the embodiment that shows in Fig. 2 a-b, except such as and then by the offset spacers of explanation Outside the configuration of portion 111 and channel arrangements.For the still common feature of two embodiments, previous relevant discussion is equally applicable in In here.On difference, it is pointed out that the offset spacers portion 111 of the example embodiment forms continuous loop at groove opening, such as may be used With what is seen in the viewgraph of cross-section of Fig. 6 a.In contrast, the embodiment shown in Fig. 2 a-b is only included in contact trench On gate spacer portion 109a parts（Or in addition not on 103 part of isolation of groove）111 material of offset spacers portion.This Outside, which includes configuration just like the line or belt 102 shown in Fig. 6 b rather than the fin 101 as shown in Fig. 2 b Channel region.Although showing two lines in the certain cross section view of Fig. 6 b, other embodiment can be included more Few line（One）Or more line（Such as three, four or more）.As previously explained, which can be primary substrate Material or alternate material（Such as the SiGe nano wires above silicon substrate）.
Fig. 6 c show the perspective view of the example embodiment shown in Fig. 6 a and 6b.In the illustrated case, contacting metal 107 There is spherical form in contact trench opening with each in offset spacers portion 111（Although any geometry can be produced Shape, such as square or rectangle, this depends on mask pattern and etching scheme）.As it can further be seen that, between each offset Corresponding gate spacer portion 109a is abutted every portion 111, and top nano wire/band 102 of corresponding raceway groove is contacted and only deviated Source/drain regions 105 below spacer portion 111.It is further noted that in this example embodiment, partly led using substrate is primary Body material（Fin 101a）To implement some in source/drain 105, and utilize the primary semi-conducting material of non-substrate（Fin Shape thing 101b）To implement other in source/drain 105.It is further noted that in the example arrangement, the fin of non-protogenous 101b is located in the groove of substrate 100.Other embodiment, which may have, to be flushed on 100 surface of substrate（Rather than groove In）, or 105 alternate material of source/drain regions on the primary base fin of substrate 100.As it can further be seen that, Raceway groove below grid can have any number of configuration, including fin, line or belt structure.With multiple transistors Some embodiments of part, can use and combine various channel arrangements, be shown in such as Fig. 6 c.For line and with channel arrangements, Point out that multiple lines and/or band can be provided.As previously explained, to point out channel material is probably that substrate 100 is primary Or alternate material, just as source/drain regions 105.In view of the disclosure, many channel arrangements and material system scheme will be aobvious Right.
Fig. 6 d illustrate Fig. 6 a according to some such embodiments until the offset spacers portion 111 shown in 6c and contact gold Belong to the various top-down views of 107 example shapes that may have.In each case, offset spacers portion 111 is pointed out Continuous annular structure.It is further noted that all may be used for any number of geometry in offset spacers portion 111 and contact 107 To be patterned and it is not intended that the disclosure is limited to the configuration of any given shape.
Fig. 7 a and nonplanar semiconductor device of the 7b diagrams with the contact framework configured according to another embodiment of the present disclosure The viewgraph of cross-section of part.The embodiment is similar to the embodiment shown in Fig. 2 a-b, in addition to channel arrangements.For two realities The still common feature of example is applied, previous relevant discussion is equally applicable to here.It is to be noted, that between the offset of the example embodiment Every portion 111 be not continuous loop at groove opening, such as can be but only on 109 part of gate spacer portion of groove opening See in the viewgraph of cross-section of Fig. 7 a and 7b.On channel arrangements, which includes configuration just like being shown in Fig. 7 b Line or belt 102 and similar to the channel region of the channel arrangements shown in Fig. 6 b.On 102 channel arrangements of nano wire/band Previous relevant discussion is equally applicable to here.
Fig. 7 c show the perspective view of the example embodiment shown in Fig. 7 a and 7b.In the illustrated case, contacting metal 107 There is rectangular shape in contact trench opening with each in offset spacers portion 111（Although as previously explained may be used To produce any geometry）.As it can further be seen that, each offset spacers portion 111 abuts corresponding gate spacer portion 109a, and top nano wire/band 102 of corresponding raceway groove contacts the only source/drain regions below offset spacers portion 111 105.It is equally applicable to here on primary and replacement source/drain regions 105 previous relevant discussions.
Fig. 7 d illustrate Fig. 7 a according to some such embodiments until the offset spacers portion 111 shown in 7c and contact gold Belong to the various top-down views of 107 example shapes that may have.In each case, offset spacers portion 111 is pointed out Discontinuous property.In these example embodiments, the offset spacers portion 111 is substantially on gate spacer portion 109a and base In sheet not in isolation 103, so that contacting metal 107 can be directly against isolation 103.But, it is pointed out that at some so Example embodiment in, lining or diffusion barrier can be provided between contacting metal 107 and isolation 103.It is further noted that It can be patterned and be not intended to this public affairs for any number of geometry in offset spacers portion 111 and contact 107 Open and be limited to any given shape configuration.
Fig. 8 a and nonplanar semiconductor device of the 8b diagrams with the contact framework configured according to another embodiment of the present disclosure The viewgraph of cross-section of part.The embodiment is similar to the embodiment shown in Fig. 2 a-b, except channel arrangements and offset spacers portion 111 it is removed or the fact that otherwise significantly reduced outside.It is still common feature for two embodiments, Previous relevant discussion is equally applicable to here.It is to be noted, that the offset spacers portion 111 of the example embodiment can be moved completely Remove, but need not in this way, and in some such embodiments, which is between the offset initially supplied Thinner version every portion 111.It is to be noted, that allow big semiconductor-metal interface area with smaller offset spacers portion 111, This can further reduce contact resistance.As previously explained, it can be etched in contact trench and/or object removal deviates Offset spacers portion 111 is removed during the special etching of spacer portion 111.On channel arrangements, which includes configuration just like figure The line or belt 102 that is shown in 7b and similar to the channel region of the channel arrangements shown in Fig. 6 b.On 102 ditch of nano wire/band The previous relevant discussion of road configuration is equally applicable to here.
Fig. 8 c show the perspective view of the example embodiment shown in Fig. 7 a and 7b.In the illustrated case, contacting metal 107 In each there is square configuration in contact trench opening（Although any geometric form can be produced as previously explained Shape）, and offset spacers portion 111 is not retained in some such configurations.As it can further be seen that, metal contact 107 each top square configuration is partially filled with whole groove opening and proceeds to the semi-conducting material of source/drain regions 105 In to provide the contact surface area of bigger, and top nano wire/band 102 of corresponding raceway groove is contacted only in the top square configuration Source/drain regions 105 below part.Equally it is applicable on primary and replacement source/drain regions 105 previous relevant discussions In here.
Fig. 8 d illustrate Fig. 8 a according to some such embodiments until what the contacting metal 107 shown in 8c may have The various top-down views of example shapes.In these example embodiments, offset spacers portion 111 it is removed or with Other modes are significantly reduced, so that contacting metal 107 can be directly against 103 and gate spacer portion 109a of isolation.However, It is to be noted, that in some such example embodiments, can contacting metal 107 with isolate 103 and gate spacer portion 109a it Between lining or barrier layer are provided.It is further noted that it can be patterned simultaneously for any number of geometry of contact 107 And it is not intended to the disclosure being limited to any given shape configuration.
Example system
The calculating system that Fig. 9 diagrams are implemented using the one or more integrated circuit structures configured according to one embodiment of the disclosure System.As can be seen, which is equipped with motherboard 1002.The motherboard 1002 can include many components, including but It is not limited to processor 1004 and at least one communication chip 1006（Two are shown in this example）, each of which can By physics and to be electrically coupled to the motherboard 1002, or otherwise it is integrated in.As will be appreciated that, the motherboard 1002 can be for example any printed circuit board (PCB), and either mainboard is also mounted in daughter board on mainboard or system 1000 only One plate etc..Depending on its application, computing system 1000 can include one or more miscellaneous parts, they may or may Physics and motherboard 1002 is not electrically coupled to it.These miscellaneous parts can include but is not limited to volatile memory（Such as DRAM）, nonvolatile memory（Such as ROM）, graphics processor, digital signal processor, cipher processor, chipset, day Line, display, touch-screen display, touch screen controller, battery, audio codec, Video Codec, power amplification Device, global positioning system（GPS）Equipment, compass, accelerometer, gyroscope, loudspeaker, camera and mass-memory unit（It is all Such as hard disk drive, compact disk（CD）, digital versatile disc（DVD）, etc.）.It is included in the component in computing system 1000 Any one can include configuration just like contact structures provided herein one or more integrated circuit structures.In some realities Apply in example, multiple functions can be integrated on one or more chips（Such as, for example, to point out communication chip 1006 It can be a part for processor 1004 or be otherwise integrated into processor 1004）.
The communication chip 1006 realizes that data are gone to and the wireless communication of transmission from computing system 1000.Term " nothing Line " and its derivative, which can be used to description, to transmit number by non-solid medium by using modulated electromagnetic radiation According to circuit, equipment, system, method, technology, communication channel etc..The term does not imply that associated equipment does not include and appoints What line, although they may not include in certain embodiments.The communication chip 1006 can implement many wireless standards or association Any one in view, includes but not limited to Wi-Fi（802.11 races of IEEE）、WiMAX（802.16 races of IEEE）、IEEE 802.20th, Long Term Evolution（LTE）、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、 Bluetooth, its derivative and it is designated as 3G, 4G, 5G and any other wireless protocols of the above.The computing system 1000 can With including many communication chips 1006.For example, the first communication chip 1006 may be exclusively used in shorter range wireless communication（Such as Wi-Fi and bluetooth）And the second communication chip 1006 may be exclusively used in longer range wireless communication（Such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and other）.The processor 1004 of the computing system 1000 includes being encapsulated in processor 1004 Interior integrated circuit lead.In some such example embodiments of the disclosure, the integrated circuit lead of the processor 1004 It can include one or more transistors based on fin, it includes such as contact structures provided herein.Term " processing Device " may refer to handle the electronic data for example from register and/or memory so that the electronic data to be transformed into and can be deposited Store up a part for any equipment or equipment of other electronic data in register and/or memory.
The communication chip 1006 can also include the integrated circuit lead being encapsulated in communication chip 1006.According to some this The example embodiment of sample, the integrated circuit lead of the communication chip 1006 are included with one such as contact structures provided herein A or multiple transistors based on fin（Such as tri-gate transistor, nano-wire transistor, nanobelt transistor）.As in view of What the disclosure will be appreciated that, to point out that multistandard wireless ability can be integrated directly into processor 1004（Such as herein The function of any chip 1006 is integrated into processor 1004, rather than has single communication chip）.Further to refer to Go out, processor 1004 can be the chipset for having such wireless capability.In brief, any number of processing can be used Device 1004 and/or communication chip 1006.Similarly, any one chip or chipset can have the multiple work(being integrated in Energy.
In various embodiments, the computing system 1000 can be laptop computer, net book, laptop, Smart phone, tablet computer, personal digital assistant（PDA）, super mobile PC, mobile phone, desktop computer, server, beat Print machine, scanner, monitor, set-top box, amusement control unit, digital camera, portable music player or digital video note Record instrument.In other embodiment, which can be processing data or be connect as described in this article using being configured with Touch the transistor device and other electronic devices of structure（Such as diode）Any other electronic device.Such as in view of the disclosure will Understand, the various embodiments of the disclosure can be used to by allowing on the same die using the Gao Qian with customization Shifting rate and various channel arrangements（Such as Si, SiGe, Si/SiGe, III-IV and/or its combination）The transistor based on fin To improve with any process node（For example, in micrometer range or sub-micron and farther）The performance of the product of making.
Other example embodiment
Following example will be apparent on further embodiment according to their many arrangements and configuration.
Example 1 is a kind of semiconductor devices, including：Substrate, it is configured with the fin from substrate extension, the fin Including channel region；Gate electrode on the channel region, wherein providing gate dielectric layer between gate electrode and channel region And gate spacer portion is provided on the side of gate electrode；Source electrode and drain region, its in fin or on fin simultaneously Adjacent to channel region and including semi-conducting material；Extend to the groove in each in source electrode and drain region；And in source electrode and The contacting metal in groove in each in drain region.
Example 2 includes the theme of example 1, wherein each groove has bottom and top, and the device further wraps Include the offset spacers portion at the top of each groove.
Example 3 includes the theme of example 2, and wherein each in the groove is continued by corresponding offset spacers portion, And the contacting metal significantly fills each in the groove.
Example 4 includes the theme of example 2 or 3, wherein semiconductor material of each offset spacers portion in source electrode and drain region On the top of material.
Example 5 includes theme of the example 2 up to any one of 4, wherein each offset spacers portion is with providing in grid Gate spacer portion contact on the side of electrode.
Example 6 includes theme of the example 2 up to any one of 5, and wherein offset spacers portion and offer is in gate electrode Side on gate spacer portion include identical material.
Example 7 include example 1 until any one of 6 theme, wherein the fin include be not substrate it is primary half Conductor material.
Example 8 includes theme of the example 1 up to any one of 7, the wherein source electrode and the semi-conducting material of drain region not It is that substrate is primary.
Example 9 include example 1 until any one of 8 theme, wherein the fin include channel region in one or Multiple line or belts.
Example 10 include example 1 until any one of 9 theme, wherein the source electrode and drain region is raised so that it Extend beyond the top of fin.
Example 11 includes theme of the example 1 up to any one of 10, wherein each in the source electrode and drain region Gradual doped scheme is configured with, it includes higher in more low-doped and other regions in the region that respective grooves are passed through Doping.
Example 12 includes theme of the example 1 up to any one of 10, wherein each in the source electrode and drain region Including doped portion and undoped with part.
Example 13 includes the theme of example 12, wherein each in the groove through it is corresponding undoped with part and Terminated close to doped portion or in doped portion.
Example 14 includes theme of the example 1 up to any one of 13, and further comprises each in fin Correspondence channel region on multiple gate structures, each gate structure includes corresponding gate electrode, gate-dielectric and grid Pole spacer portion, wherein the distance between neighboring gate structures substantially limit corresponding source electrode or the width of drain region, the width exist On the direction parallel with fin.
Example 15 includes example 1 up to any one of 14 theme, and the wherein device is a part for computing device.
Example 16 includes the theme of example 15, and wherein the computing device is mobile computing device.The mobile computing device can To be such as tablet computer, smart phone, laptop computer or there is other of battery or other regenerative power sources movement Computing device.
Example 17 is a kind of integrated circuit device, including：Substrate, it is configured with the fin from substrate extension, the fin Shape thing includes multiple channel regions；Multiple gate structures, on correspondence of each gate structure in channel region one and are wrapped Include gate electrode, gate-dielectric and gate spacer portion；Multipair source electrode and drain region, per a pair of correspondence all in channel region One and including semi-conducting material；The groove in each in source electrode and drain region is extended to, each groove has bottom Portion and top, and further there is at least 25% depth of total vertical length of corresponding source/drain regions；And significantly fill out Fill the contacting metal of the groove in each of source electrode and drain region.
Example 18 includes the theme of example 17, and further comprises the offset spacers portion at the top of each groove, Each wherein in the groove is continued by corresponding offset spacers portion, wherein each offset spacers portion is in neighboring gates Between the gate spacer portion of structure, and the offset spacers portion is contacted with two in those gate spacer portions.
Example 19 includes the theme of example 18, and wherein the offset spacers portion and gate spacer portion include identical material.
Example 20 includes theme of the example 17 up to any one of 19, and it not is that substrate is primary that wherein the fin, which includes, Semi-conducting material.
Example 21 includes theme of the example 17 up to any one of 20, the wherein source electrode and the semi-conducting material of drain region It is not that substrate is primary.
Example 22 includes theme of the example 17 up to any one of 21, and the wherein fin includes one in channel region Or multiple line or belts.
Example 23 include example 17 until any one of 22 theme, wherein the source electrode and drain region be raised so that They extend beyond the top of fin.
Example 24 includes theme of the example 17 up to any one of 23, wherein each in the source electrode and drain region Gradual doped scheme is configured with, it includes higher in more low-doped and other regions in the region that respective grooves are passed through Doping.
Example 25 includes theme of the example 17 up to any one of 23, wherein each in the source electrode and drain region Including doped portion and undoped with part.
Example 26 includes the theme of example 25, wherein each in the groove through it is corresponding undoped with part and Terminated close to doped portion or in doped portion.
Example 27 includes theme of the example 17 up to any one of 26, and wherein the distance between neighboring gate structures are basic The upper width for limiting corresponding source pole or drain region, the width is on the direction parallel with fin.
Example 28 includes example 17 up to any one of 27 theme, and the wherein device is a part for computing device.
Example 29 includes the theme of example 28, and wherein the computing device is mobile computing device.
Example 30 is a kind of method for forming semiconductor contact, and this method includes：Substrate is provided, it is configured with from lining The fin of bottom extension, the fin include channel region；Gate electrode is provided on channel region, wherein in gate electrode and ditch Gate dielectric layer is provided between road area and gate spacer portion is provided on the side of gate electrode；Source electrode and drain region are provided, It is in fin and adjacent to channel region and including semi-conducting material；By trench etch to each in source electrode and drain region In；And groove in each of source electrode and drain region is significantly filled with contacting metal.
Example 31 includes the theme of example 30, wherein each groove has bottom and top, and this method is further It is included at the top of each groove and forms offset spacers portion.
Example 32 includes the theme of example 31, and wherein each in groove is continued by corresponding offset spacers portion, And the contacting metal also significantly fills the offset spacers portion part of the groove.
Example 33 includes the theme of example 31 or 32, wherein semiconductor of each offset spacers portion in source electrode and drain region On the top of material.
Example 34 includes theme of the example 31 up to any one of 33, and each of which offset spacers portion all exists with providing Gate spacer portion contact on the side of gate electrode.
Example 35 includes theme of the example 31 up to any one of 34, and wherein the offset spacers portion and offer are in grid electricity Gate spacer portion on the side of pole includes identical material.
Example 36 includes theme of the example 30 up to any one of 35, and it not is that substrate is primary that wherein the fin, which includes, Semi-conducting material.
Example 37 includes theme of the example 30 up to any one of 36, the wherein source electrode and the semi-conducting material of drain region It is not that substrate is primary.
Example 38 includes theme of the example 30 up to any one of 37, and the wherein fin includes one in channel region Or multiple line or belts.
Example 39 include example 30 until any one of 38 theme, wherein the source electrode and drain region be raised so that They extend beyond the top of fin.
Example 40 includes theme of the example 30 up to any one of 39, wherein each in the source electrode and drain region Gradual doped scheme is configured with, it includes higher in more low-doped and other regions in the region that respective grooves are passed through Doping.
Example 41 includes theme of the example 30 up to any one of 39, wherein each in the source electrode and drain region Including doped portion and undoped with part.
Example 42 includes the theme of example 41, wherein each in the groove through it is corresponding undoped with part and Terminated close to doped portion or in doped portion.
Example 43 include example 30 until any one of 42 theme, wherein by trench etch to source electrode and drain region In each in after but before the groove is significantly filled, this method further comprises the semiconductor to source electrode and drain region Material is doped.
Example 44 includes the theme of example 43, wherein being doped the semi-conducting material of source electrode and drain region including injection Doping and Annealing Scheme.
Example 45 includes theme of the example 30 up to any one of 44, wherein by trench etch into source electrode and drain region Each include etching groove so that the depth of each groove be total vertical length of corresponding source/drain regions at least 25%。
Example 46 includes theme of the example 30 up to any one of 45, wherein by trench etch into source electrode and drain region Each include etching groove so that the depth of each groove be total vertical length of corresponding source/drain regions at least 50%。
Example 47 includes theme of the example 30 up to any one of 46, wherein by trench etch into source electrode and drain region Each include etching groove so that the depth of each groove be total vertical length of corresponding source/drain regions at least 60%。
Example 48 includes theme of the example 30 up to any one of 47, wherein by trench etch into source electrode and drain region Each include etching groove so that the depth of each groove be total vertical length of corresponding source/drain regions at least 70%。
Example 49 includes theme of the example 30 up to any one of 48, wherein by trench etch into source electrode and drain region Each include etching groove so that the depth of each groove be total vertical length of corresponding source/drain regions at least 80%。
Example 50 includes theme of the example 30 up to any one of 49, wherein by trench etch into source electrode and drain region Each include etching groove so that the depth of each groove be total vertical length of corresponding source/drain regions at least 90%。
The described above of the example embodiment of the disclosure is had been presented for for the purpose of illustration and description.It is not intended to be Disclosed precise forms are limited in detail or by the disclosure.In view of the disclosure, many modifications and variations are possible.It is intended to The scope of the present disclosure is not limited by the detailed description, but limited by investing this claim.

Claims (25)

1. a kind of semiconductor devices, including：
Substrate, it is configured with the fin from substrate extension, which includes channel region；
Gate electrode on the channel region, wherein providing gate dielectric layer between gate electrode and channel region and in grid Gate spacer portion is provided on the side of pole electrode；
Source electrode and drain region, it is in fin or on fin and adjacent to channel region and including semi-conducting material；
Extend to the groove in each in source electrode and drain region；And
The contacting metal in groove in each in source electrode and drain region.
2. device according to claim 1, wherein each groove has bottom and top, and the device further wraps Include the offset spacers portion at the top of each groove.
3. each in device according to claim 2, the wherein groove is continued by corresponding offset spacers portion, And the contacting metal significantly fills each in the groove.
4. device according to claim 2, wherein semi-conducting material of each offset spacers portion in source electrode and drain region Top on.
5. device according to claim 2, wherein each offset spacers portion is with providing the grid on the side of gate electrode Pole spacer portion contact.
6. between device according to claim 2, the wherein grid of the offset spacers portion and offer on the side of gate electrode Include identical material every portion.
It not is the primary semi-conducting material of substrate that 7. device according to claim 1, the wherein fin, which include,.
8. device according to claim 1, the wherein source electrode and the semi-conducting material of drain region are not that substrate is primary.
9. device according to claim 1, the wherein fin include one or more of channel region line or belt.
10. device according to claim 1, the wherein source electrode and drain region are raised so that they extend beyond fin-shaped The top of thing.
11. each in device according to claim 1, the wherein source electrode and drain region is configured with gradual doping Scheme, it includes the higher-doped in more low-doped and other regions in the region that respective grooves are passed through.
12. each in device according to claim 1, the wherein source electrode and drain region is including doped portion and not Doped portion.
13. each in device according to claim 12, the wherein groove passes through corresponding undoped part simultaneously And terminated close to doped portion or in doped portion.
14. device according to claim 1, further comprises each more on the correspondence channel region of fin A gate structure, each gate structure include corresponding gate electrode, gate-dielectric and gate spacer portion, wherein neighboring gates The distance between structure substantially limits corresponding source electrode or the width of drain region, and the width is on the direction parallel with fin.
15. according to claim 1 up to the device described in any one of 14, the wherein device is a part for computing device.
16. device according to claim 15, the wherein computing device are mobile computing devices.
17. a kind of integrated circuit device, including：
Substrate, it is configured with the fin from substrate extension, which includes multiple channel regions；
Multiple gate structures, on correspondence of each gate structure in channel region one and including gate electrode, grid Dielectric and gate spacer portion；
Multipair source electrode and drain region, per a pair of correspondence one all in channel region and including semi-conducting material；
The groove in each in source electrode and drain region is extended to, each groove has bottom and top, and further At least 25% depth of total vertical length with corresponding source/drain regions；And
The significantly contacting metal of the groove in each of filling source electrode and drain region.
18. device according to claim 17, further comprises：
In offset spacers portion at the top of each groove, the wherein groove each by corresponding offset spacers portion and Continue；
Wherein each offset spacers portion between the gate spacer portion of neighboring gate structures, and the offset spacers portion and those Two contacts in gate spacer portion.
19. a kind of method for forming semiconductor contact, this method includes：
Substrate is provided, it is configured with the fin from substrate extension, which includes channel region；
Gate electrode is provided on channel region, wherein between gate electrode and channel region provide gate dielectric layer and Gate spacer portion is provided on the side of gate electrode；
Source electrode and drain region are provided, it is in fin and adjacent to channel region and including semi-conducting material；
By trench etch into each in source electrode and drain region；And
The groove in each of source electrode and drain region is significantly filled with contacting metal.
20. according to the method for claim 19, wherein each groove has bottom and top, and this method is further It is included at the top of each groove and forms offset spacers portion.
21. according to the method for claim 20, wherein each in groove is continued by corresponding offset spacers portion, And the contacting metal also significantly fills the offset spacers portion part of the groove.
22. according to the method for claim 20, wherein semiconductor material of each offset spacers portion in source electrode and drain region On the top of material.
23. according to the method for claim 20, each of which offset spacers portion is all with providing on the side of gate electrode Gate spacer portion contact.
24. according to claim 19 until method described in any one of 23, wherein by trench etch to source electrode and drain electrode After in each in area but before the groove is significantly filled, this method further comprises partly leading to source electrode and drain region Body material is doped.
25. according to the method for claim 24, wherein being doped the semi-conducting material of source electrode and drain region including note Enter doping and Annealing Scheme.
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