CN108021060B

CN108021060B - ADS-B chip of integrated radio frequency

Info

Publication number: CN108021060B
Application number: CN201711097370.1A
Authority: CN
Inventors: 刘刚; 张锋烽; 徐丁海; 葛成
Original assignee: China Aeronautical Radio Electronics Research Institute
Current assignee: China Aeronautical Radio Electronics Research Institute
Priority date: 2017-11-09
Filing date: 2017-11-09
Publication date: 2020-10-09
Anticipated expiration: 2037-11-09
Also published as: CN108021060A

Abstract

The invention discloses an integrated radio frequency ADS-B chip, which comprises an analog circuit part and a digital circuit part, wherein the analog circuit part comprises a radio frequency transmitting module, a radio frequency receiving module and a transceiving switch, and the digital circuit part comprises an ADC module, a DAC module, a 1090ES interface module, a signal coding and decoding module, a CPR and data coding and decoding module and a data flow control module which are connected to a high-speed bus. The invention integrates an analog radio frequency 1090ES data chain module in ADS-B system equipment, a logic control module, a signal processing module, an ADS-B protocol processing module, a GNSS interface module, a memory module, an ADC/DAC front-end module and a power supply and power consumption management module in a digital circuit into a single special integrated chip by a semiconductor process integration technology, thereby realizing microminiaturization and low power consumption of the ADS-B system equipment and further realizing the integration of multiple functions of monitoring broadcast, receiving processing, display control and the like.

Description

ADS-B chip of integrated radio frequency

Technical Field

The invention relates to an integrated circuit technology in the technical field of aviation, in particular to a special chip for realizing an ADS-B function.

Background

The traditional portable ADS-B terminal system is often composed of a central processing module (comprising a GNSS module, a signal processing module, an S mode, an ADS-B protocol processing module and the like), a transmitting module, a receiving module, a power supply module and a series of discrete devices, wherein the central processing module is used for forming ADS-B information from navigation information of a local machine and sending the ADS-B information to the transmitting module for external transmission so as to complete the ADS-B OUT function; the ADS-B information sent by the receiving module is decoded and message analyzed, and the analyzed ADS-B information and navigation information of the local machine are output to a back-end device to complete the ADS-B IN function; the power module adopts a built-in rechargeable battery to provide power input for the whole machine. Although the miniaturization of the ADS-B system can be realized through a compact structural layout and a proper integrated circuit comprehensive technology, the method has a limited effect, and even if the cost factor is not considered, the method completely depends on high-performance small packaging components, and the miniaturization degree of the product cannot meet the installation requirement of a navigation airplane, particularly the current rapidly developed unmanned aerial vehicle.

With the gradual opening of a low-altitude airspace, the general aviation is rapidly developed, and meanwhile, further requirements are provided for ADS-B terminal equipment, and the equipment is low in power consumption, microminiaturization and light in weight and is the development trend of ADS-B airborne terminals, so that the special chip is an optimal way for solving the microminiaturization requirements of the ADS-B equipment in the navigation field.

Disclosure of Invention

In order to solve the above technical problems, an object of the present invention is to provide an integrated radio frequency ADS-B chip architecture, in which an analog radio frequency 1090ES data link module, a logic control module, a signal processing module, an ADS-B protocol processing module, a GNSS interface module, a memory module, an ADC/DAC front-end module, and a power supply and power consumption management module in an ADS-B system device are integrated into a single dedicated integrated chip by a semiconductor process integration technology, so as to achieve microminiaturization and low power consumption of the ADS-B system device, and further achieve integrated integration of multiple functions such as monitoring broadcast, receiving processing, display control, and the like.

The invention aims to be realized by the following technical scheme:

an integrated radio frequency ADS-B chip comprises an analog circuit part and a digital circuit part, wherein the analog circuit part comprises a radio frequency transmitting module, a radio frequency receiving module and a transceiving switch, and the digital circuit part comprises an ADC module, a DAC module, a 1090ES interface module, a signal coding and decoding module, a CPR and data coding and decoding module, a data flow control module and the like which are connected to a high-speed bus;

when the ADS-B chip works IN the ADS-B IN function state, the transceiving switch is switched on the radio frequency receiving module, the radio frequency receiving module receives ADS-B message electromagnetic waves of other machines received by an external antenna and generates 1090ES detection signals, and the 1090ES interface module starts the ADC module to receive and sample 1090ES detection signals according to the control of the data flow control module; the data flow control module controls the signal coding and decoding module to decode the sampled data to generate ADS-B original data; the CPR and data coding and decoding module is controlled by the data flow control module to carry out message analysis and data filtering on ADS-B original data to generate displayable information; the data flow control module transmits the displayable information to an external monitoring terminal; wherein, the displayable information comprises flight identification codes, positions, states, heights, headings and the like of other aircrafts;

when the ADS-B chip works in the ADS-B OUT function state, the receiving and transmitting switch is connected with the radio frequency transmitting module, the CPR and data coding and decoding module is controlled by the data flow control module to carry OUT message coding and data filtering on the flight situation information of the chip, and ADS-B original data are generated; the data flow control module controls the signal coding and decoding module to perform data framing on ADS-B original data and synthesize an ADS-B message suitable for 1090ES data chain transmission; 1090ES interface module starts DAC module according to control of data flow control module to send ADS-B message to radio frequency emission module, which modulates ADS-B message into 1090MHz carrier signal and completes emission through external antenna.

Preferably, the radio frequency receiving module includes a first filter circuit, an LNA circuit, a second filter circuit, a mixer circuit, a detector circuit, and a first local oscillator circuit, an output end of which is connected to an input end of the mixer circuit.

Preferably, the radio frequency transmitting module comprises a second local oscillator circuit and a third filter circuit; the second local oscillation circuit generates 1090MHz carrier signals, carries out PPM modulation on the ADS-B message and outputs the ADS-B message to an external power amplifier circuit for power amplification; and the third filter circuit filters the 1090MHz carrier signal after power amplification and outputs the filtered signal to an external antenna.

Furthermore, the ADS-B chip integrated with the radio frequency also comprises a GNSS interface module connected to the high-speed bus, and the data flow control module forms the received local barometric altitude signal and the external GNSS data received by the GNSS interface module into local flight situation information.

Furthermore, the radio frequency integrated ADS-B chip also comprises a central control unit connected to the high-speed bus, and the central control unit is used for performing state control on the ADC module, the DAC module, the 1090ES interface module, the signal coding and decoding module, the CPR and data coding and decoding module, the data flow control module and the GNSS interface module.

Preferably, the 1090ES interface module, the signal encoding and decoding module, the CPR and data encoding and decoding module, the data flow control module, the GNSS interface module and the central control unit adopt an ASIC custom hardmac mode.

Preferably, the 1090ES interface module, the signal encoding and decoding module, the CPR and data encoding and decoding module, the data flow control module, the GNSS interface module and the central control unit adopt an FPGA self-defined soft core mode.

Preferably, the 1090ES interface module, the signal coding and decoding module, the data flow control module, the GNSS interface module and the central control unit adopt an ASIC custom hard core mode, and the CPR and data coding and decoding module adopts a DSP custom soft core mode.

Preferably, the signal encoding and decoding module includes: the device comprises a first control register module, an uplink decoding and analyzing module, an ES data generating module and a downlink framing module;

the first control register module controls and starts an uplink decoding and analyzing module or starts an ES generating module and a downlink framing module according to the data flow control module;

the uplink decoding and analyzing module is used for decoding the 1090ES detection signal to generate ADS-B original data;

the ES data generating module is used for generating ES data and transmitting the ES data to the downlink framing module;

the downlink framing module is used for framing data of ADS-B original data and synthesizing an ADS-B message suitable for 1090ES data chain transmission.

Preferably, the CPR and data codec module comprises: CPR decoding module, other data decoding module, alpha-beta-gamma filter

The device comprises a wave module, a second control register module, a CPR coding module and other data coding modules;

the second control register module starts the CPR decoding module, other data decoding modules and the alpha-beta-gamma filtering module according to the control of the data flow control module, or starts the alpha-beta-gamma filtering module, the CPR coding module and other data coding modules;

the CPR decoding module is used for analyzing the position information of other machines in the ADS-B original data;

the other data decoding module is used for analyzing other information of other machines in the ADS-B original data;

the CPR coding module is used for converting the position information of the computer into ADS-B original data;

the other data coding module is used for converting other information of the local computer into ADS-B original data;

the alpha-beta-gamma filtering module is used for filtering the position information of other machines, other information of other machines, the position information of the local machine and other information of the local machine.

Preferably, the data flow control module comprises: the third control register module, the data flow control state machine module and the data flow switching module;

the third control register module is used for monitoring the working state of the data flow control state machine module and sampling an external key value;

the data flow control state machine module changes a working state according to internal configuration or sampling change of an external key value, wherein the working state is an ADS-B IN functional state or an ADS-B OUT functional state;

the data flow switching module is used for sequentially starting the 1090ES interface module, the signal coding and decoding module, the CPR and data coding and decoding module when the data flow control state machine module is IN an ADS-B IN functional state, and sequentially starting the CPR and data coding and decoding module, the signal coding and decoding module and the 1090ES interface module when the data flow control state machine module is IN an ADS-B OUT functional state.

Furthermore, the ADS-B chip integrated with the radio frequency also comprises a JTAG test unit, a ROM unit, a bus controller, a memory controller, an SVGA controller and an SRAM which are connected to the high-speed bus in the form of an ASIC standard hard core; the system also comprises a timer/counter, an external interface controller, a universal input/output device and a system configuration register group which are connected with the low-speed bus in the form of an ASIC standard hard core, wherein the high-speed bus and the low-speed bus are connected through a bus bridge.

Furthermore, the ADS-B chip of the integrated radio frequency also comprises a power management and reset module, the power management and reset module comprises a built-in voltage stabilizer module and a power management module, the voltage stabilizer module outputs different voltages according to internal configuration or sampling external key values, and the power management module determines to supply the voltages to different internal or external modules.

Furthermore, the ADS-B chip integrated with the radio frequency also comprises a clock management module, the clock management module comprises a normal working clock, a low-power-consumption clock, a frequency divider and a clock management module, and the frequency divider and the clock management module select the normal working clock or the low-power-consumption clock according to the clock requirements of different IP cores and distribute different working frequencies to the IP cores.

The invention adopts integrated IC integration technology to integrate the analog radio frequency 1090ES data chain module and most digital modules in the portable ADS-B system equipment into a single chip, forms a special ADS-B chip architecture of A/D mixed mode with the functions of monitoring information broadcasting and receiving, navigation data processing, mode parameter configuration, display control and the like, really realizes the design requirements of small volume, light weight, low power consumption, renewability and update and convenient secondary integrated development, the system can be widely applied to light navigation airplanes, particularly airborne environments such as unmanned planes and paragliders, and ground environments such as maneuvering vehicle-mounted platforms and ground towers, provides effective and reliable flight situation monitoring for general aviation, achieves the expectation of safe cruising of general aviation aircrafts and all-weather monitoring of ground systems, and meets the development requirements of advanced general aviation.

Drawings

FIG. 1 is a general architecture diagram of an ADS-B chip architecture for integrated radio frequency according to an embodiment;

FIG. 2 is a schematic diagram of a portion of an analog circuit shown in the first embodiment;

FIG. 3 is a schematic diagram of a portion of a custom IP core shown in the first embodiment;

FIG. 4 is a block diagram of a power management & reset module according to the first embodiment

FIG. 5 is a block diagram of a clock management module shown in the first embodiment;

FIG. 6 is a diagram illustrating an internal data flow of the ADS-B chip architecture in the ADS-B OUT functional state according to the first embodiment;

fig. 7 is a diagram illustrating an internal data flow of the integrated radio frequency ADS-B chip architecture IN the ADS-B IN functional state according to an embodiment.

Detailed Description

In order to make the technical means, the creation features, the achievement purposes and the effects of the invention easy to understand, the invention is further elaborated below by combining the specific drawings and the embodiments.

Example one

The ADS-B chip architecture of integrated radio frequency provided by this embodiment is an a/D mixed mode chip architecture, as shown in fig. 1, and includes an analog circuit portion and a digital circuit portion. The analog circuit part mainly comprises a radio frequency transmitting module, a radio frequency receiving module and a receiving and transmitting switch, wherein the radio frequency transmitting module mainly comprises a second local oscillator circuit and a third filter circuit; the radio frequency receiving circuit mainly comprises a first filter circuit, an LNA circuit, a second filter circuit, a first local oscillator circuit, a mixing circuit and a detection circuit. The digital circuit part mainly comprises: a standard process library: the system comprises a bus controller, a JTAG test unit, a ROM, a memory controller, an SVGA controller, an RAM, an ADC module, a DAC module, a bus bridge, a timer/counter, an external interface controller and a general input/output device; a secondary bus architecture: the system comprises a high-speed bus and a low-speed bus, which are used for connecting and organizing each module in a chip; self-defining an IP kernel: the device comprises a central control unit, a 1090ES interface module, a signal coding and decoding module, a CPR and data coding and decoding module, a GNSS interface module and a system configuration register set; and a power management & reset module, a clock management module, etc.

Analog circuit part

The analog circuit part is mainly used for building a special data chain-1090 ES transmission data chain of ADS-B data. The radio frequency transceiver comprises a radio frequency transmitting module, a radio frequency receiving module and a transceiving switch, and a schematic circuit diagram of the radio frequency transceiver is shown in fig. 2.

The radio frequency emission module: the local oscillator circuit comprises a second local oscillator circuit and a third filter circuit; the second local oscillation circuit generates 1090MHz carrier signals, carries out PPM modulation on the ADS-B message and outputs the ADS-B message to an external power amplifier circuit for power amplification; and the third filter circuit filters the 1090MHz carrier signal after power amplification and outputs the filtered signal to an external antenna.

A radio frequency receiving module: the low-noise amplifier comprises a first filter circuit, an LNA circuit, a second filter circuit, a mixing circuit, a detection circuit and a first local oscillator circuit, wherein the first filter circuit, the LNA circuit, the second filter circuit, the mixing circuit and the detection circuit are sequentially connected, and an output end of the first local oscillator circuit is connected to the mixing circuit. The digital detection circuit is mainly responsible for receiving, filtering, amplifying, frequency converting, detecting and other functions of 1090MHz electromagnetic wave signals transmitted by surrounding airplanes, and sends generated TTL levels of detection signals to the digital circuit part.

A receiving and transmitting switch: used for switching the transceiving state at the current moment so as to reduce the power consumption. The working principle of the transceiving switch is that the control unit of the chip outputs a control signal to the peripheral circuit of the chip according to the working state of the chip, and then the peripheral circuit generates a signal and returns the signal to the transceiving switch through a pin, so that the switching control of the transceiving switch is controlled outside the chip (in the attached figure 2, the pin signal is seen to be connected), and the purpose is to separate the analog circuit part and the digital circuit part as much as possible so as to avoid interference.

Digital circuit part

The digital circuit part mainly comprises three parts: standard process library, secondary bus architecture, and custom IP core. The standard process library is mainly used for building general auxiliary functions in the ADS-B chip and comprises a JTAG test unit, a ROM, a memory controller and other modules; the secondary bus architecture is mainly used for connecting all modules in the system and comprises a high-performance high-clock bus, a peripheral bus and a corresponding bus control module; the self-defined IP core is mainly used for realizing ADS-B data processing core functions of the chip, including situation information acquisition, receiving and sending, data flow control, signal coding and decoding, CPR, data analysis and the like.

Standard process library

The standard process library comprises standard units and corresponding VHDL descriptions, is a series of integrated reusable IP cores specially developed for integrated application, and is used for building a universal functional module in a special chip. The standard modules adopted by the chip are as follows:

JTAG test unit: and performing complete test and discovery on various fault states in the chip.

A ROM unit: and the read-only memory is used for internal table lookup.

An ADC module: and the sampling module is used for sampling 1090ES detection signals input by the radio frequency receiving module to finish A/D conversion.

A DAC module: used for completing D/A conversion to ADS-B information and outputting to the radio frequency emission module.

A bus controller: for coordinating communications between modules on the high speed bus.

The memory controller: for memory access to an internal memory SRAM or an external memory device.

SVGA controller: for driving an external display device.

SRAM: for accomplishing internal data storage.

A bus bridge: the method is used for matching and coordinating the high-speed bus and the low-speed bus.

Timing/counter: for system timing.

An external interface controller: for external interface communication.

General purpose input output device: the chip function operation instruction is used for driving the external port to perform chip function operation instruction.

Two-level bus architecture

(1) High-speed bus: system modules for connecting high performance, high clock frequencies, such as: a central control unit, a memory controller, an internal SRAM, etc.

(2) And the low-speed bus is used for connecting peripheral low-speed devices such as a serial port, a GPIO (general purpose input/output) and the like.

Custom IP Kernel

The customized IP kernel mainly includes a central control unit, a 1090ES interface module, a signal encoding/decoding module, a CPR and data encoding/decoding module, a data flow control module, a GNSS interface module, and a system configuration register set, and its internal structure diagram is shown in fig. 3.

A central control unit: for controlling the state of the various modules on the high speed bus.

1090ES interface module: and receiving TTL level signals of external 1090ES detection signals after being sampled by the ADC module according to the control of the data flow control module, and sending internally generated ADS-B information into the DAC module for conversion and then broadcasting and transmitting.

The signal coding and decoding module: the forward decoding and reverse framing of the ES data are responsible 1090 according to the control of the data flow control module, and the hardware module mainly comprises: the device comprises an uplink decoding and analyzing module, a first control register module, an ES generating module and a downlink framing module. The structure of the signal encoding and decoding module is shown in fig. 2.

The internal functional modules are briefly described as follows:

(1) an uplink decoding and analysis module: the ADS-B data processing method is mainly used for decoding and analyzing 1090ES messages to form ADS-B original data containing airspace airplane addresses, airplane identification codes, positions, states, heights, headings and other flight information.

(2) A first control register module: and controlling and starting the uplink decoding and analyzing module or starting the ES generating module and the downlink framing module according to the data flow control module.

(3) An ES generation module: for generating ES message elements.

(4) A downlink framing module: the method is mainly responsible for embedding information including local longitude, latitude, speed, time, altitude and the like into ES message units, and combining the ES message units into ADS-B message with DF18 format and suitable for 1090ES data chain through framing.

CPR and data coding and decoding module: the module is mainly responsible for forward analysis and reverse transformation of ADS-B original data containing flight information such as airspace airplane address, airplane identification code, position, state, altitude, course and the like, and filtering generated data, and the hardware module mainly comprises: the CPR decoding module, other data decoding modules, an alpha-beta-gamma filtering module, a second control register module, a CPR coding module and other data coding modules. The structure of the CPR and data codec module is shown in fig. 3.

The internal functional modules are briefly described as follows:

(1) a CPR decoding module: mainly responsible for analyzing the position information of other machines in ADS-B original data so as to send the position information to an external monitoring terminal

(2) The other data decoding module: mainly responsible for analyzing other information such as airplane speed, time and the like of other airplanes in ADS-B original data so as to send the information to an external monitoring terminal

(3) An alpha-beta-gamma filtering module: filtering the data (position information of other machine, other information of other machine) after forward analysis and the data (position information of local machine, other information of local machine) after reverse conversion

(4) A second control register module: and starting the CPR decoding module, the other data decoding module and the alpha-beta-gamma filtering module or starting the alpha-beta-gamma filtering module, the CPR coding module and the other data coding module according to the control of the data flow control module.

(5) A CPR encoding module: the method is mainly responsible for converting local position information transmitted from the outside into ADS-B original information.

(6) Other data encoding modules: the method is mainly used for converting other information such as airplane speed, time and the like of a local airplane which is transmitted from the outside into ADS-B original information.

A data flow control module: ADS-B data transceiving and processing are the most main functions of an ADS-B chip, a data flow control module in the ADS-B chip just controls the flow direction of ADS-B data in a system so as to assist the system to complete ADS-B data transceiving and processing, and a hardware module of the ADS-B data transceiving and processing module mainly comprises: the third control register module, the data flow control state machine module and the data flow switching module. The structure of the data flow control module is shown in fig. 4.

The internal functional modules are briefly described as follows:

(1) a third control register: and monitoring the working state of the data flow control module, sampling an external key value, and changing the working state according to the change of the external key value.

(2) A data flow control state machine module: the data flow control module is a core component for changing the working state of the data flow control module according to system setting and user input.

(3) A data stream switching module: the data flow direction is controlled by hard wire connection.

GNSS interface module: the module is mainly responsible for receiving GNSS navigation information which is provided by an external GNSS module and contains the contents of local longitude, latitude, speed, time, altitude and the like.

As a core part of ADS-B data processing, the custom IP core can adopt the following three different implementation forms:

(1) all adopt the way of IP hardcore, namely (central control unit, 1090ES interface module, signal coding and decoding module, CPR and data coding and decoding module, data flow control module, GNSS interface module) all adopt the framework of ASIC solidified hardcore in figure 1, adopt the framework of the solidified hardcore can improve the reliability of the operation of the chip system.

(2) All adopt the mode of IP soft core, namely (central control unit, 1090ES interface module, signal coding and decoding module, CPR and data coding and decoding module, data flow control module, GNSS interface module) all adopt the framework of FPGA soft core in figure 1, adopt the framework of the whole soft core, can start different modules according to the user's needs time sharing on the one hand, help to improve the autonomy based on chip secondary development, can reduce the power consumption of chip operation at the same time.

(3) In the mode of a semi-hard core and a semi-soft core, a DSP (digital signal processor) soft core can be independently adopted in a CPR (CPR and data coding and decoding) module in the figure 1, and a central control unit, a 1090ES (advanced peripheral component interconnect) interface module, a signal coding and decoding module, a data flow control module and a GNSS (global navigation satellite system) interface module adopt an ASIC (application specific integrated circuit) hard core solidified architecture.

In addition, in order to improve the energy utilization rate, reduce the peripheral circuits of the chip, and reduce the power consumption of the chip, a power management & reset module and a clock management module are further included in the internal architecture of the chip, as shown in fig. 4, the power management & reset module provides power to each internal module or external module. The power management and reset module is composed of a built-in voltage stabilizer, and external control is added to enable the internal voltage stabilizer to output different voltage signals. As shown in fig. 5, the clock management module adopts a three-level control mode, and in the first level, there are two clocks: a normal operating clock and a low power consumption clock. The normal working clock can have three realization forms, the low-power consumption clock has two realization forms, the internal part of the system determines when to use the clock as the current clock output through HSCK and LSCK, and the chip can work in a normal state or a low-power consumption standby state. In the second two stages, there are divider & clock management blocks that divide the clock selected in the first stage into different clock frequencies for each IP core of the third stage.

When the ADS-B chip works in the ADS-B OUT function state, the data flow control module starts the GNSS interface module, the CPR and data coding and decoding module, the signal coding and decoding module and the 1090ES interface module in sequence according to internal configuration or sampling external key values, and then the receiving and transmitting switch switches on the radio frequency transmitting module according to external signals. The GNSS interface module receives external GNSS data (navigation information such as local longitude, latitude, speed, time, altitude and the like), the external GNSS data and local barometric altitude signals received by the external interface module flow together, message coding and data filtering are carried out through the CPR and data coding and decoding module to generate ADS-B original data, then data framing is carried out through the signal coding and decoding module to synthesize ADS-B message suitable for 1090ES data chain transmission, the ADS-B message is sent out by the 1090ES interface module and sent to the radio frequency transmitting module through the DAC module, and the radio frequency transmitting module modulates the ADS-B message into 1090MHz carrier signals to complete transmission through an external antenna. The internal data flow diagram is shown in fig. 6.

When the ADS-B chip works IN the ADS-B IN function state, the 1090ES interface module, the signal coding and decoding module, the CPR and data coding and decoding module are sequentially started by the data flow control module according to internal configuration or sampling external key values, and the radio frequency receiving module is switched on by the receiving and transmitting switch according to external signals. The radio frequency receiving module receives ADS-B message electromagnetic waves of other machines received by an external antenna and generates 1090ES detection signals of other machines, 1090ES detection signals of other machines are sampled by an ADC and flow in through a 1090ES interface module, the signals are decoded by the signal coding and decoding module to generate ADS-B original data containing flight information such as airspace airplane addresses, flight identification codes, positions, states, heights, courses and the like, message analysis is carried out through a CPR and data coding and decoding module, data filtering is carried out to generate displayable information, the displayable information is transmitted to an external monitoring terminal through the external interface module, and the internal data flow diagram is shown in figure 7.

Compared with the traditional ADS-B system equipment based on a separation type device, the ADS-B chip architecture integrated with the radio frequency integrates an analog radio frequency 1090ES data chain module and most of digital modules into a single chip, the ADS-B function of the chip is more efficient and special by building related modules, and compared with the traditional ADS-B system based on the separation type device, the chip structure is higher in processing speed, higher in system integration level, smaller in size, lighter in weight and lower in power consumption. Users can conveniently develop corresponding ADS-B microminiaturized products on the basis of the chip, and a wider development space is provided for the application of the ADS-B technology.

While various preferred embodiments of the present invention have been described above with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims

1. An integrated radio frequency ADS-B chip comprises an analog circuit part and a digital circuit part, wherein the analog circuit part comprises a radio frequency transmitting module, a radio frequency receiving module and a transceiving switch, and the digital circuit part comprises a standard process library, a secondary bus architecture, a self-defined IP core and a clock management module;

the standard process library comprises an IP core comprising an ADC module, a DAC module, a bus controller and a bus bridge; the user-defined IP kernel comprises an IP kernel 1090ES interface module, a signal coding and decoding module, a CPR and data coding and decoding module and a data flow control module; the secondary bus architecture comprises a high-speed bus and a low-speed bus, and a bus controller, an ADC (analog-to-digital converter) module, a DAC (digital-to-analog converter) module, a 1090ES (electronic/electronic) interface module, a signal coding and decoding module, a CPR (CPR and data coding and decoding) module and a data flow control module are connected to the high-speed bus; the low-speed bus is used for connecting peripheral low-speed equipment;

the bus bridge is used for matching and coordinating a high-speed bus and a low-speed bus;

the bus controller is used for coordinating communication among modules on the high-speed bus;

the data flow control module includes: the third control register module, the data flow control state machine module and the data flow switching module;

the data flow control state machine module changes the working state according to the change of the internal configuration or the external key value, wherein the working state is an ADS-B IN functional state or an ADS-B OUT functional state;

the data flow switching module is used for sequentially starting the 1090ES interface module, the signal coding and decoding module and the CPR and data coding and decoding module when the data flow control state machine module is IN an ADS-B IN functional state, and sequentially starting the CPR and data coding and decoding module, the signal coding and decoding module and the 1090ES interface module when the data flow control state machine module is IN an ADS-B OUT functional state;

when the ADS-B chip works IN the ADS-B IN function state, the transceiving switch is switched on the radio frequency receiving module, the radio frequency receiving module receives ADS-B message electromagnetic waves of other machines received by an external antenna and generates 1090ES detection signals, and the 1090ES interface module starts the ADC module to receive and sample 1090ES detection signals according to the control of the data flow control module; the data flow control module controls the signal coding and decoding module to decode the sampled data to generate ADS-B original data; the CPR and data coding and decoding module is controlled by the data flow control module to carry out message analysis and data filtering on ADS-B original data to generate displayable information; the data flow control module transmits the displayable information to an external monitoring terminal; wherein, the displayable information comprises flight identification codes, positions, states, heights and headings of other aircrafts;

when the ADS-B chip works in the ADS-B OUT function state, the receiving and transmitting switch is connected with the radio frequency transmitting module, the CPR and data coding and decoding module is controlled by the data flow control module to carry OUT message coding and data filtering on the flight situation information of the chip, and ADS-B original data are generated; the data flow control module controls the signal coding and decoding module to perform data framing on ADS-B original data and synthesize an ADS-B message suitable for 1090ES data chain transmission; 1090ES interface module starts DAC module to send ADS-B message to radio frequency emission module according to control of data flow control module, radio frequency emission module modulates ADS-B message into 1090MHz carrier signal and completes emission through external antenna;

the clock management module comprises a normal working clock, a low-power consumption clock, a frequency divider and a clock management module, wherein the frequency divider and the clock management module select the normal working clock or the low-power consumption clock according to the clock requirements of different IP cores and distribute different working frequencies to the IP cores.

2. An ADS-B chip of claim 1, wherein the rf receiving module comprises a first filter circuit, an LNA circuit, a second filter circuit, a mixer circuit, a detector circuit, and a first local oscillator circuit having an output terminal connected to an input terminal of the mixer circuit.

3. The ADS-B chip of claim 1, wherein the RF transmitting module comprises a second local oscillator circuit and a third filter circuit; the second local oscillation circuit generates 1090MHz carrier signals, carries out PPM modulation on the ADS-B message and outputs the ADS-B message to an external power amplifier circuit for power amplification; and the third filter circuit filters the 1090MHz carrier signal after power amplification and outputs the filtered signal to an external antenna.

4. The ADS-B chip of claim 1, further comprising a GNSS interface module connected to the high-speed bus, wherein the data flow control module combines the received local barometric altitude signal and external GNSS data received by the GNSS interface module to form local flight status information.

5. The ADS-B chip of claim 4, further comprising a central control unit connected to the high-speed bus, the central control unit being configured to perform state control of the ADC module, the DAC module, the 1090ES interface module, the signal codec module, the CPR and data codec module, the data flow control module, and the GNSS interface module.

6. The ADS-B chip of claim 5, wherein the 1090ES interface module, the signal codec module, the CPR and data codec module, the data flow control module, the GNSS interface module and the central control unit are ASIC custom hardmac.

7. The ADS-B chip of claim 1, wherein the 1090ES interface module, the signal codec module, the CPR and data codec module, the data flow control module, the GNSS interface module and the central control unit adopt FPGA-defined soft core.

8. The ADS-B chip of claim 1, wherein the 1090ES interface module, the signal codec module, the data flow control module, the GNSS interface module and the central control unit are in ASIC-defined hard core mode, and the CPR and data codec module is in DSP-defined soft core mode.

9. The ADS-B chip of claim 1, wherein the signal codec module comprises: the device comprises a first control register module, an uplink decoding and analyzing module, an ES data generating module and a downlink framing module;

the uplink decoding and analyzing module is used for decoding 1090ES detection signals to generate ADS-B original data;

and the downlink framing module is used for framing data of ADS-B original data and synthesizing an ADS-B message suitable for 1090ES data chain transmission.

10. The ADS-B chip of claim 1, wherein the CPR and data codec module comprises: the CPR decoding module, the other data decoding module, the alpha-beta-gamma filtering module, the second control register module, the CPR coding module and the other data coding module;

11. The ADS-B chip of claim 1, further comprising a JTAG test unit, a ROM unit, a memory controller, an SVGA controller, and an SRAM connected to the high-speed bus by using ASIC standard hard core; it also includes a timer/counter, an external interface controller, a general input and output device and a system configuration register group which are connected on the low speed bus in the form of ASIC standard hardmac.

12. The ADS-B chip of claim 1, further comprising a power management & reset module, wherein the power management & reset module comprises a built-in regulator module and a power management module, the regulator module samples external key values or internal configuration to output different voltages, and the power management module determines to supply the voltages to different internal or external modules.