CN108009047A - A kind of two-node cluster hot backup model and implementation method - Google Patents

A kind of two-node cluster hot backup model and implementation method Download PDF

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Publication number
CN108009047A
CN108009047A CN201711191345.XA CN201711191345A CN108009047A CN 108009047 A CN108009047 A CN 108009047A CN 201711191345 A CN201711191345 A CN 201711191345A CN 108009047 A CN108009047 A CN 108009047A
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dsp processor
signal
switch
circuit
dsp
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CN108009047B (en
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包涌泉
王小进
乔卿阳
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Wuhan Institute of Marine Electric Propulsion China Shipbuilding Industry Corp No 712 Institute CSIC
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Wuhan Institute of Marine Electric Propulsion China Shipbuilding Industry Corp No 712 Institute CSIC
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1446—Point-in-time backing up or restoration of persistent data
    • G06F11/1458—Management of the backup or restore process
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1446—Point-in-time backing up or restoration of persistent data
    • G06F11/1456—Hardware arrangements for backup

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)

Abstract

The invention discloses a kind of two-node cluster hot backup model, including CPLD chips and the first dsp processor and the second dsp processor that are connected on CPLD chips, the first AD sampling modules and the 2nd AD sampling modules and the first eeprom memory and the second eeprom memory for storing circuit breaker parameters are connected on first dsp processor and the second dsp processor, the CPLD chips include supervisory circuit, logic control circuit and the first choice switch K1 and the second selecting switch K2 being connected with the first dsp processor and the second dsp processor；The invention also discloses a kind of implementation method of two-node cluster hot backup model；The present invention realizes arbitration circuit with piece of CPLD chip, can so simplify hardware design, improve the reliability of whole circuit；The present invention has good electromagnetism interference performance, reliability high, is particularly suitable for applications in the high microsystem of reliability requirement, such as direct current power system peculiar to vessel.

Description

A kind of two-node cluster hot backup model and implementation method
Technical field
The invention belongs to technical field of electricity, and in particular to a kind of two-node cluster hot backup model and implementation method.
Background technology
In the very high occasion of reliability requirement, such as unmanned plane and aviation airborne equipment, managed using various based on faults-tolerant control By the reliability design with hardware fault-tolerant model.
Fault-tolerant design is also referred to as Redundancy Design, it is carried by the parallel connection or stand-by unit number of the same function of increase completion A kind of design method of high reliability；A function module failure is required not cause the incorrect operation of whole device at the same time.
Microcomputer Protection has clear superiority in terms of fault-tolerant design, device various pieces can be carried out using software continuous Monitoring, can also mutually be monitored between each hardware；There is sufficient space in terms of protective redundancy degree, can be in two nested structures The software worked out in identical hardware using different principle realizes protection dual configuration, also can in the same hardware real off the shelf software The redundancy processing in terms of function is carried out, reliability had not only been ensure that but also had added the flexibility of relaying configuration.
Hardware redundancy is used primarily in high reliability occasion, is divided into 3 kinds of hardware redundancy forms such as active and passive, mixed dynamic.Passively Hardware redundancy is also known as static hardware redundancy.It applies the concept of fault masking, that is, refers to redundancy structure not with failure feelings The redundant form of condition change.The structure of generally use is triplication redundancy and two mould redundancy structures.Active hardware redundancy is also known as dynamic State hardware redundancy, is to complete the fault-tolerant processing of system by several steps such as the detection to the system failure, positioning and recovery, so System structure is recombinated afterwards.
This technology usually has 3 kinds of modes, is two-shipper comparison system, spare replacement system and paired back-up system respectively. Wherein spare replacement system be using a module as primary module normal work when export, part in addition is spare module, is adopted The position broken down and corresponding module are determined with various intelligent detecting methods and fault location technology, if primary module occurs Failure, then system will carry out structural rearrangement, make the spare module of normal work become primary module.
Spare part in spare replacement is commonly divided into three kinds of Hot Spare, cold standby and warm spare modes, and cold standby refers to lead When module works, backup module need not power up work；When Hot Spare refers to primary module work, backup module synchronously power-up work； Warm spare refers to the state that only indivedual global facilities are in power-up work, is the improvement to Hot Spare or cold standby.
The content of the invention
It is an object of the invention to deficiency according to prior art, a kind of two-node cluster hot backup model and implementation method are designed, it is special It is not suitably applied in the high system of reliability requirement, guard method is advanced, reliability is high.
The technical solution adopted by the present invention to solve the technical problems is：A kind of two-node cluster hot backup model, including CPLD chips And be connected to the first dsp processor and the second dsp processor on CPLD chips, first dsp processor and The first AD sampling modules and the 2nd AD sampling modules are connected on second dsp processor and for storing circuit breaker parameters The first eeprom memory and the second eeprom memory；The CPLD chips include：Dsp processor, to the AD of connection Sampling module and eeprom memory carry out self-test, output self-test signal ERR；Supervisory circuit, receives the heart that dsp processor is sent Signal HTI is jumped, exports signal HTO to logic control circuit；Logic control circuit, receives the self-test that dsp processor is sent to it Signal ERR, supervisory circuit output signal HTO and MANUAL signal, the switch motion of output signal control selections, output reset signal RSTN is to dsp processor or sends alarm signal A LARM, MANUAL signal for setting output channel；First choice switchs K1 and the second selecting switch K2, is connected respectively the first dsp processor and the second dsp processor.
A kind of two-node cluster hot backup model, its supervisory circuit include frequency dividing circuit, counting and timing circuit, reset timing electricity Road and be connected to reset timing circuit on reverser, the counting and timing circuit include respectively with the first dsp processor and Two counters of the second dsp processor connection；One external timing signal CLKIN input frequency dividing circuit, the signal after frequency dividing It is input in counting and timing circuit and is counted again, while compared with the gate time constant set, when when specified Corresponding counter O reset, counting and timing circuit will be produced one by the heartbeat signal HTI that interior no dsp processor is sent Low level HTO signals, while the stabilization high level for resetting timing circuit generation holding certain time is triggered, and terminate in delay Afterwards by all counter O resets, which will produce a low level reset signal RSTN by reverser and reset DSP processing Device.
A kind of two-node cluster hot backup model, its logic control circuit is done using triple gate selects switching switch defeated to control Go out passage, logic control circuit is according to the self-test signal ERR of dsp processor, output the signal HTO and MANUAL of supervisory circuit Signal carries out Switch Control；When hostdown, triple gate first choice switch K1 is arranged to high-impedance state, and the second selection is opened Pass K2 is low resistance state, and device automatically switches to guest machine and works；When two-shipper, block exports and sends alarm in the event of failure Signal ALARM；Channel selection mode is set, dsp processor output channel is set using MANUAL signals, MANUAL signals are height The first dsp processor is output channel during level, and the second dsp processor is output channel when MANUAL signals are low level, point Bie Duimei roads dsp processor is checked and monitored.
The invention also discloses a kind of implementation method of two-node cluster hot backup model, comprise the following steps：
Step 1, the first dsp processor or the second dsp processor hosted are set by MANUAL signals, MANUAL signals are height The first dsp processor is host during level, and the second dsp processor is host when MANUAL signals are low level；
Step 2, supervisory circuit is sent according to dsp processor heartbeat signal HTI judges the operation conditions of dsp processor, so Result HTO is exported to logic control circuit afterwards；The AD sampling modules and eeprom memory that dsp processor connects it carry out Self-test, then exports self-test signal ERR to logic control circuit；
Step 3, logic control circuit carries out judgement selection according to self-test signal ERR and supervisory circuit output signal HTO.
If the first dsp processor is set as host：
Judge selection one：If the first dsp processor and the equal normal operation of the second dsp processor, by the first dsp processor Operation result is exported as system, i.e., first choice switch K1 closures, the second selecting switch K2 are disconnected；
Judge selection two：The second dsp processor failure if the first dsp processor is normal, i.e., by the fortune of the first dsp processor Row result is exported as system, i.e., first choice switch K1 closures, the second selecting switch K2 are disconnected, while resetted at the 2nd DSP Manage device；
Judge selection three：If the first dsp processor failure, the second dsp processor is normal, then carries out switching operation, i.e., First choice switch K1 is disconnected, the second selecting switch K2 closures, is exported the operation result of the second dsp processor as system, The first dsp processor is resetted at the same time；
Judge selection four：If the first dsp processor and the equal failure of the second dsp processor, are blocked defeated by logic control circuit Go out, i.e., first choice switch K1 is disconnected, the second selecting switch K2 is disconnected, and is simultaneously emitted by alarm signal, is shown that device is unavailable；
If the second dsp processor is set as host：
Judge selection one：If the second dsp processor and the equal normal operation of the first dsp processor, by the second dsp processor Operation result is exported as system, i.e. the second selecting switch K2 closures, first choice switch K1 are disconnected；
Judge selection two：The first dsp processor failure if the second dsp processor is normal, also by the fortune of the second dsp processor Row result is exported as system, i.e. the second selecting switch K2 closures, first choice switch K1 are disconnected, while resetted at the first DSP Manage device；
Judge selection three：If the second dsp processor failure, the first dsp processor is normal, then carries out switching operation, i.e., Second selecting switch K2 is disconnected, first choice switch K1 closures, is exported the operation result of the first dsp processor as system, The second dsp processor is resetted at the same time；
Judge selection four：If the first dsp processor and the equal failure of the second dsp processor, are blocked defeated by logic control circuit Go out, i.e., first choice switch K1 is disconnected, the second selecting switch K2 is disconnected, and is simultaneously emitted by alarm signal, is shown that device is unavailable.
The supervisory circuit includes frequency dividing circuit, counting and timing circuit, resets timing circuit and is connected to reset timing Reverser on circuit, the counting and timing circuit include corresponding with the first dsp processor and the second dsp processor respectively connect Two counters connect；One external timing signal CLKIN input frequency dividing circuit, the signal after frequency dividing are input to counting and timing again Counted in circuit, while compared with the gate time constant set, there is no dsp processor when interior at the appointed time The heartbeat signal HTI of transmission is by corresponding counter O reset, and counting and timing circuit will produce a low level HTO signal, together When triggering reset timing circuit and produce the stabilization high level for being kept for certain time, it is and after delay that all counters are clear Zero, which will produce a low level reset signal RSTN by reverser and reset dsp processor.
The logic control circuit does the selection of switching switch control output channel, logic control circuit using triple gate Switching control is carried out according to output signal HTO and the MANUAL signal of the self-test signal ERR of dsp processor, supervisory circuit System；When hostdown, triple gate first choice switch K1 is arranged to high-impedance state, and the second selecting switch K2 is low resistance state, device Guest machine is automatically switched to work；When two-shipper, block exports and sends alarm signal A LARM in the event of failure；Passage is set Selection mode, dsp processor output channel, the first DSP processing when MANUAL signals are high level are set using MANUAL signals Device is output channel, and the second dsp processor is output channel when MANUAL signals are low level, respectively to every road dsp processor Checked and monitored.
The beneficial effects of the invention are as follows：
The present invention realizes arbitration circuit with piece of CPLD chip, can so simplify hardware design, improve the reliability of whole circuit. The present invention has good electromagnetism interference performance, reliability high, is particularly suitable for applications in the high microsystem of reliability requirement In, such as direct current power system peculiar to vessel.
Brief description of the drawings
Fig. 1 is the principle schematic of two-node cluster hot backup model of the present invention；
Fig. 2 is the supervisory circuit figure of two-node cluster hot backup model of the present invention；
Fig. 3 is the logic control circuitry diagram of two-node cluster hot backup model of the present invention.
Each reference numeral is：11-frequency dividing circuit, 12-counting and timing circuit, 13-reset timing circuit.
Embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.
Embodiment 1
With reference to shown in Fig. 1, the invention discloses a kind of two-node cluster hot backup model, including CPLD chips and CPLD cores are connected to The first dsp processor and the second dsp processor of on piece, it is right respectively on first dsp processor and the second dsp processor The first AD sampling modules and the 2nd AD sampling modules should be connected with and the first EEPROM for storing circuit breaker parameters is stored Device and the second eeprom memory.
The CPLD chips include supervisory circuit, logic control circuit and with the first dsp processor and the 2nd DSP Manage the first choice switch K1 and the second selecting switch K2 that device corresponds to connection；The supervisory circuit receives dsp processor and sends Heartbeat signal HTI, export signal HTO to logic control circuit；The logic control circuit receives dsp processor and is sent out to it Self-test signal ERR, supervisory circuit output signal HTO and the MANUAL signal sent, the switch motion of output signal control selections, output Reset signal RSTN is to dsp processor or sends alarm signal A LARM；The dsp processor samples mould to the AD of connection Block and eeprom memory carry out self-test, output self-test signal ERR；The MANUAL signals are used to set output channel.
The invention also discloses a kind of implementation method of two-node cluster hot backup model, comprise the following steps：
Step 1, the first dsp processor or the second dsp processor hosted are set by MANUAL signals, MANUAL signals are height The first dsp processor is host during level, and the second dsp processor is host when MANUAL signals are low level；
Step 2, supervisory circuit is sent according to dsp processor heartbeat signal HTI judges the operation conditions of dsp processor, so Result HTO is exported to logic control circuit afterwards；The AD sampling modules and eeprom memory that dsp processor connects it carry out Self-test, then exports self-test signal ERR to logic control circuit；
Step 3, logic control circuit carries out judgement selection according to self-test signal ERR and supervisory circuit output signal HTO.
If the first dsp processor is set as host：
Judge selection one：If the first dsp processor and the equal normal operation of the second dsp processor, by the first dsp processor Operation result is exported as system, i.e., first choice switch K1 closures, the second selecting switch K2 are disconnected；
Judge selection two：The second dsp processor failure if the first dsp processor is normal, i.e., by the fortune of the first dsp processor Row result is exported as system, i.e., first choice switch K1 closures, the second selecting switch K2 are disconnected, while resetted at the 2nd DSP Manage device；
Judge selection three：If the first dsp processor failure, the second dsp processor is normal, then carries out switching operation, i.e., First choice switch K1 is disconnected, the second selecting switch K2 closures, is exported the operation result of the second dsp processor as system, The first dsp processor is resetted at the same time；
Judge selection four：If the first dsp processor and the equal failure of the second dsp processor, are blocked defeated by logic control circuit Go out, i.e., first choice switch K1 is disconnected, the second selecting switch K2 is disconnected, and is simultaneously emitted by alarm signal, is shown that device is unavailable；
If the second dsp processor is set as host：
Judge selection one：If the second dsp processor and the equal normal operation of the first dsp processor, by the second dsp processor Operation result is exported as system, i.e. the second selecting switch K2 closures, first choice switch K1 are disconnected；
Judge selection two：The first dsp processor failure if the second dsp processor is normal, also by the fortune of the second dsp processor Row result is exported as system, i.e. the second selecting switch K2 closures, first choice switch K1 are disconnected, while resetted at the first DSP Manage device；
Judge selection three：If the second dsp processor failure, the first dsp processor is normal, then carries out switching operation, i.e., Second selecting switch K2 is disconnected, first choice switch K1 closures, is exported the operation result of the first dsp processor as system, The second dsp processor is resetted at the same time；
Judge selection four：If the first dsp processor and the equal failure of the second dsp processor, are blocked defeated by logic control circuit Go out, i.e., first choice switch K1 is disconnected, the second selecting switch K2 is disconnected, and is simultaneously emitted by alarm signal, is shown that device is unavailable.
With reference to shown in Fig. 2, the supervisory circuit includes frequency dividing circuit 11, counting and timing circuit 12, resets timing circuit 13 and be connected to reset timing circuit 13 on reverser, the counting and timing circuit 12 include respectively with the first DSP processing Device and the second dsp processor correspond to two counters of connection；One external timing signal CLKIN input frequency dividing circuit 11, point Square wave after frequency is input in counting and timing circuit 12 again to be counted, while compared with the gate time constant set, When the heartbeat signal HTI that interior no dsp processor is sent at the appointed time changes CLRN end states by corresponding counter Reset, counting and timing circuit 12 will produce a low level HTO signal, while trigger and reset the generation of timing circuit 13 holding one The stabilization high level fixed time, and a high level is produced by all macroelement counter O resets, height electricity after delay Mean longitude, which crosses reverser, will produce a low level reset signal RSTN reset dsp processor.
With reference to shown in Fig. 3, the logic control circuit does selection switching switch to control output channel using triple gate, Logic control circuit is carried out according to the self-test signal ERR of dsp processor, output signal HTO and the MANUAL signal of supervisory circuit Switch Control；When hostdown, triple gate first choice switch K1 is arranged to high-impedance state, and the second selecting switch K2 is low Resistance state, device automatically switch to guest machine and work；When two-shipper, block exports and sends alarm signal in the event of failure ALARM；Channel selection mode is set, dsp processor output channel is set using MANUAL signals, MANUAL signals are high level When the first dsp processor be output channel, the second dsp processor is output channel when MANUAL signals are low level, right respectively Checked and monitored per road dsp processor.
The present invention with piece of CPLD chip realizes arbitration circuit, can so simplify hardware design, and that improves whole circuit can By property.The present invention has good electromagnetism interference performance, reliability high, is particularly suitable for applications in the high microcomputer of reliability requirement In system, such as direct current power system peculiar to vessel.
The above-described embodiments merely illustrate the principles and effects of the present invention, and the embodiment that part uses, for For those of ordinary skill in the art, without departing from the concept of the premise of the invention, can also make it is some deformation and Improve, these belong to protection scope of the present invention.

Claims (4)

  1. A kind of 1. two-node cluster hot backup model, it is characterised in that：Including CPLD chips and be connected on CPLD chips first Dsp processor and the second dsp processor, are connected to the first AD on first dsp processor and the second dsp processor Sampling module and the 2nd AD sampling modules and the first eeprom memory and the 2nd EEPROM for storing circuit breaker parameters Memory；The CPLD chips include
    Dsp processor, self-test, output self-test signal ERR are carried out to the AD sampling modules and eeprom memory of connection；
    Supervisory circuit, receives the heartbeat signal HTI that dsp processor is sent, exports signal HTO to logic control circuit
    Logic control circuit, receive dsp processor is sent to it self-test signal ERR, supervisory circuit export signal HTO and MANUAL signals, export the switch motion of signal control selections, export reset signal RSTN to dsp processor or send alarm signal Number ALARM, MANUAL signals are used to set output channel；
    First choice switchs K1 and the second selecting switch K2, is connected respectively the first dsp processor and the second dsp processor 's.
  2. 2. a kind of two-node cluster hot backup model according to claim 1, it is characterised in that the supervisory circuit includes frequency dividing electricity Road（11）, counting and timing circuit（12）, reset timing circuit（13）Be connected to reset timing circuit（13）On reverser, institute The counting and timing circuit stated（12）Including two counters being connected respectively with the first dsp processor and the second dsp processor；One A external timing signal CLKIN input frequency dividing circuits（11）, the signal after frequency dividing is input to counting and timing circuit again（12）In into Row counts, while compared with the gate time constant set, when the interior heart without dsp processor transmission at the appointed time Signal HTI is jumped by corresponding counter O reset, counting and timing circuit（12）A low level HTO signal will be produced, will be touched at the same time Hair resets timing circuit（13）The stabilization high level for being kept for certain time is produced, and it is after delay that all counters are clear Zero, which will produce a low level reset signal RSTN by reverser and reset dsp processor.
  3. 3. a kind of two-node cluster hot backup model according to claim 1, it is characterised in that the logic control circuit uses three State door does selection switching switch to control output channel, self-test signal ERR of the logic control circuit according to dsp processor, monitoring Output signal HTO and the MANUAL signal of circuit carry out Switch Control；When hostdown, triple gate first choice switch K1 is arranged to high-impedance state, and the second selecting switch K2 is low resistance state, and device automatically switches to guest machine and works；When two-shipper has Block exports and sends alarm signal A LARM during failure；Channel selection mode is set, DSP processing is set using MANUAL signals Device output channel, the first dsp processor is output channel when MANUAL signals are high level, when MANUAL signals are low level Two dsp processors are output channel, and every road dsp processor is checked and monitored respectively.
  4. 4. a kind of implementation method of two-node cluster hot backup model as claimed in claim 1, it is characterised in that comprise the following steps：
    Step 1, the first dsp processor or the second dsp processor hosted are set by MANUAL signals, MANUAL signals are height The first dsp processor is host during level, and the second dsp processor is host when MANUAL signals are low level；
    Step 2, supervisory circuit is sent according to dsp processor heartbeat signal HTI judges the operation conditions of dsp processor, so Result HTO is exported to logic control circuit afterwards；The AD sampling modules and eeprom memory that dsp processor connects it carry out Self-test, then exports self-test signal ERR to logic control circuit；
    Step 3, logic control circuit carries out judgement selection according to self-test signal ERR and supervisory circuit output signal HTO；
    If the first dsp processor is set as host：
    If the first dsp processor and the equal normal operation of the second dsp processor, the operation result of the first dsp processor is made Exported for system, i.e., first choice switch K1 closures, the second selecting switch K2 are disconnected；
    The second dsp processor failure if the first dsp processor is normal, i.e., using the operation result of the first dsp processor as System exports, i.e., first choice switch K1 closures, the second selecting switch K2 are disconnected, while resetted the second dsp processor；
    If the first dsp processor failure, the second dsp processor is normal, then carries out switching operation, i.e. first choice switchs K1 is disconnected, the second selecting switch K2 closures, is exported the operation result of the second dsp processor as system, while reset first Dsp processor；
    If the first dsp processor and the equal failure of the second dsp processor, blocked and exported by logic control circuit, i.e., the first choosing Switch K1 disconnections, the second selecting switch K2 disconnections are selected, alarm signal is simultaneously emitted by, shows that device is unavailable；
    If the second dsp processor is set as host：
    If the second dsp processor and the equal normal operation of the first dsp processor, the operation result of the second dsp processor is made Exported for system, i.e. the second selecting switch K2 closures, first choice switch K1 are disconnected；
    The first dsp processor failure if the second dsp processor is normal, also using the operation result of the second dsp processor as System exports, i.e. the second selecting switch K2 closures, first choice switch K1 are disconnected, while resetted the first dsp processor；
    If the second dsp processor failure, the first dsp processor is normal, then carries out switching operation, i.e. the second selecting switch K2 is disconnected, first choice switch K1 closures, is exported the operation result of the first dsp processor as system, while reset second Dsp processor；
    If the first dsp processor and the equal failure of the second dsp processor, blocked and exported by logic control circuit, i.e., the first choosing Switch K1 disconnections, the second selecting switch K2 disconnections are selected, alarm signal is simultaneously emitted by, shows that device is unavailable.
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CN111964339A (en) * 2020-08-25 2020-11-20 百尔制冷(无锡)有限公司 Temperature data input method for hot air defrosting group control
CN111964339B (en) * 2020-08-25 2022-02-08 百尔制冷(无锡)有限公司 Temperature data input method for hot air defrosting group control

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