CN107946202B - The three-dimensional storage electric test method and test structure of short process stage - Google Patents
The three-dimensional storage electric test method and test structure of short process stage Download PDFInfo
- Publication number
- CN107946202B CN107946202B CN201711138160.2A CN201711138160A CN107946202B CN 107946202 B CN107946202 B CN 107946202B CN 201711138160 A CN201711138160 A CN 201711138160A CN 107946202 B CN107946202 B CN 107946202B
- Authority
- CN
- China
- Prior art keywords
- dimensional storage
- process stage
- exit
- short process
- exposing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The present invention provides the three-dimensional storage electric test method and test structure of a kind of short process stage, belongs to technical field of semiconductors.The described method includes: providing the three-dimensional storage of short process stage (array area there is no through-hole)；The channel hole in region to be measured in the three-dimensional storage of short process stage is ground to exposing polysilicon plug, and deposited metal forms bit line exit beyond the Great Wall in the polycrystalline silicon of exposing；Stepped region in the three-dimensional storage of short process stage is ground to exposing all grid layers, and deposited metal forms wordline exit on the grid layer of exposing；Bit line exit and wordline exit to formation apply voltage, complete the electrical testing in region to be measured.In the present invention, the electrical testing of the three-dimensional storage to short process stage is realized, can effectively ensure that the feasibility of front-end process, and then provide a strong guarantee to improve the yield of three-dimensional storage finished product.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of three-dimensional storage electrical testing sides of short process stage
Method and test structure.
Background technique
With the continuous development to integrated level and storage capacity requirement, three-dimensional storage comes into being, and is that one kind is based on
The novel product of flat memory, structure is complicated and CT Cycle Time is relatively long.At this stage, in new-product development production process
In, usually there are some short process stages (Short Loop) to need to test to assess leading portion the product device performance of early period
The feasibility of processing procedure.But due to factors such as manufacturing cycle limitations, it can not often wait until complete manufacturing process (Full early period
Process test assessment is done after) being fully completed again, thus brings very big difficulty for the test of early period；, knot high for integrated level
Structure complexity is for three-dimensional storage, the test that short process stage device performance how is carried out to it is then even more extremely difficult；Its
In, the three-dimensional storage of short process stage, structure as shown in Figure 1, top view near its stepped region as shown in Fig. 2, can be with
Find out that its structure is considerably complicated.
Currently, having the device performance test mode of some three-dimensional storages for full processing procedure, usually it is carried out
Positive (Z-direction) is ground to contact hole layer, and grid layer to be tested will be needed to be connected in a manner of circuit mending together, to complete
Electrical testing.But for the three-dimensional storage of short process stage, since its many subsequent level and connection are not yet carried out, therefore
The device performance test mode of the three-dimensional storage of full processing procedure can not ideally be suitable for the three-dimensional storage of short process stage
Device performance test.And the three-dimensional storage of existing short process stage, some arrays as shown in Figure 3 can be usually encountered again
The problems such as area's through-hole does not connect, grid and wing wall short circuit, gate contact does not connect；Therefore, seek a general effective mode
The device performance of the three-dimensional storage of short process stage is tested, to ensure the feasibility of front-end process, and then is ensured complete
The yield for the three-dimensional storage finished product that processing procedure obtains has far reaching significance.
Summary of the invention
To solve the deficiencies in the prior art, the present invention provides a kind of three-dimensional storage electric test method of short process stage
And test structure.
On the one hand, the present invention provides a kind of three-dimensional storage electric test method of short process stage, comprising:
The three-dimensional storage of short process stage is provided；
The channel hole in region to be measured in the three-dimensional storage of the short process stage is ground to exposing polysilicon plug, and
Deposited metal forms bit line exit to the polycrystalline silicon of exposing beyond the Great Wall；
Stepped region in the three-dimensional storage of the short process stage is ground to exposing all grid layers, and in exposing
Deposited metal forms wordline exit on grid layer；
Voltage is applied to the bit line exit and the wordline exit, completes the electrical testing in region to be measured.
Optionally, using chemical mechanical milling tech along the three-dimensional storage that third direction grinds the short process stage
The channel hole in region to be measured is to exposing polysilicon plug；
Optionally, the short process stage is ground along first direction or second direction using chemical mechanical milling tech
Stepped region in three-dimensional storage is to exposing all grid layers.
Optionally, deposited metal forms bit line exit to the polycrystalline silicon in exposing beyond the Great Wall, specifically: pass through focusing
In the polycrystalline silicon of exposing, deposits tungsten forms bit line exit to ion beam beyond the Great Wall；
Optionally, the deposited metal on the grid layer of exposing forms wordline exit, specifically: pass through focused ion
Beam deposits tungsten on the grid layer of exposing forms wordline exit.
Optionally, voltage is applied to the bit line exit and the wordline exit by nano-probe, completed to be measured
The electrical testing in region.
On the other hand, the present invention provides a kind of three-dimensional storage electrical testing structure of short process stage, comprising:
The three-dimensional storage of short process stage；
The bit line exit being formed in the region to be measured of the three-dimensional storage of the short process stage；
The wordline exit being formed in the stepped region of the three-dimensional storage of the short process stage.
Optionally, the bit line exit is formed in the polycrystalline silicon of channel hole exposing in the region to be measured beyond the Great Wall.
Optionally, the wordline exit is formed on the grid layer exposed in stepped region.
Optionally, the bit line exit and the wordline exit are tungsten.
The present invention has the advantages that
In the present invention, carry out being ground to exposing by the channel hole in region to be measured in the three-dimensional storage to short process stage
Polysilicon plug, and deposited metal forms bit line exit beyond the Great Wall in the polycrystalline silicon of exposing；And its stepped region is ground to
Expose all grid layers, and deposited metal forms wordline exit on the grid layer of exposing, the circuit for realizing wordline is repaired
The circuit mending with bit line is mended, and the endpoint by being formed to circuit mending applies voltage, realizes three to short process stage
Tie up the electrical testing of memory；It can effectively ensure the feasibility of front-end process, and then to improve three-dimensional storage finished product
Yield provide a strong guarantee.
Detailed description of the invention
By reading the following detailed description of the preferred embodiment, various other advantages and benefits are common for this field
Technical staff will become clear.The drawings are only for the purpose of illustrating a preferred embodiment, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings:
Attached drawing 1 is the structure birds-eye view of the three-dimensional storage of short process stage；
Attached drawing 2 is the top view near the stepped region of the three-dimensional storage of short process stage；
Attached drawing 3 is the schematic diagram of FAQs in the three-dimensional storage of short process stage；
Attached drawing 4 is a kind of three-dimensional storage electric test method flow chart of short process stage provided by the invention；
Attached drawing 5 is the schematic diagram of bit line exit provided by the invention；
Attached drawing 6 is the schematic diagram of bit line exit and wordline exit provided by the invention；
Attached drawing 7 is the schematic diagram provided by the invention by focused ion beam deposition metal；
Attached drawing 8 is the test mode schematic diagram of bit line exit electric current provided by the invention and voltage.
Specific embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although showing this public affairs in attached drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.It is to be able to thoroughly understand the disclosure on the contrary, providing these embodiments, and can be by this public affairs
The range opened completely is communicated to those skilled in the art.
Embodiment one
Embodiment according to the present invention provides a kind of three-dimensional storage electric test method of short process stage, such as Fig. 4
It is shown, comprising:
The three-dimensional storage (array area there is no through-hole (Via0)) of short process stage is provided；
The channel hole (Channel Hole) in region to be measured in the three-dimensional storage of short process stage is ground to exposing polycrystalline
Silicon plug (Poly Plug), and deposited metal forms bit line exit beyond the Great Wall in the polycrystalline silicon of exposing；
Stepped region in the three-dimensional storage of short process stage is ground to exposing all grid layers (Gate Line), and
Deposited metal forms wordline exit on the grid layer of exposing；
Bit line exit and wordline exit to formation apply voltage, complete the electrical testing in region to be measured.
Embodiment according to the present invention, using chemical mechanical grinding (Chemical Mechanical Polishing,
Abbreviation CMP) technique region to be measured along the three-dimensional storage that third direction grinds short process stage channel hole (Channel
Hole) to exposing polysilicon plug (Poly Plug)；
Embodiment according to the present invention, using chemical mechanical grinding (Chemical Mechanical Polishing,
Abbreviation CMP) the extremely exposing of stepped region of the technique in the three-dimensional storage that first direction or second direction grind short process stage
All grid layers (Gate Line).
Wherein, first direction is X-direction shown in attached drawing 1, and second direction is Y-direction shown in attached drawing 1, third party
To for Z-direction shown in attached drawing 1.
Embodiment according to the present invention, in the polycrystalline silicon bit line exit of deposited metal formation beyond the Great Wall of exposing, specifically
Are as follows: by focused ion beam (Focused Ion Beam, abbreviation FIB), in the polycrystalline silicon of exposing, deposits tungsten (W) is formed beyond the Great Wall
Bit line exit；Wherein, bit line exit is specifically as shown in Figure 5；It needs explanatorily, attached drawing 5 is given for example only explanation, and bit line draws
The position of outlet is not limited to position shown in attached drawing 5.
Embodiment according to the present invention, deposited metal forms wordline exit on the grid layer of exposing, specifically: it is logical
Over-focusing ion beam (Focused Ion Beam, abbreviation FIB) deposits tungsten (W) on the grid layer of exposing forms wordline and draws
End；Wherein, wordline exit is specifically as shown in Figure 6；It needs explanatorily, attached drawing 6 is given for example only explanation, the position of wordline exit
It sets and is not limited to position shown in attached drawing 6.
In the present invention, since the current process of the three-dimensional storage of short process stage adjusts not enough optimization, thus through-hole
(Via0) on not long, as shown in Figure 1, it is currently included substrate, grid layer (Gate Line), channel hole (Channel
Hole), the structures such as common source array (Array Common Source, abbreviation ACS), therefore when carrying out electrical testing to it, it needs
The circuit mending that realize bit line first grinds the channel hole in region to be measured to exposing polysilicon plug in z-direction, and
The channel hole in region to be measured is connected and forms bit line exit the polycrystalline silicon of exposing by deposited metal beyond the Great Wall；It may be noted that
Ground connects the channel hole in region to be measured in the present invention, efficiently avoid the connectivity problem due to channel hole itself and
Cause multiple test problem；
Further, since the process adjustments of the three-dimensional storage of short process stage not enough optimize, contain in stepped region
Contact hole (Contact Hole) is not all just often connected on grid layer very much, thus it is traditional in positive (Z-direction) by institute
The contact hole for having grid layer to connect connects the method tested and cannot be applicable in；In the present invention, by the cross section (side X
To or Y-direction) grinding stepped region to all grid layers expose, and on the grid layer of exposing deposited metal by all grid layers
Exit is connected and formed, the circuit mending of bit line is realized, overcomes the not applicable problem of conventional method；
Further, it in the present invention, is incited somebody to action by what professional equipment observed by focused ion beam deposition tungsten (plating tungsten)
All grid layers connect together, and the virtual condition that channel hole is connected is as shown in Figure 7.
Embodiment according to the present invention, by nano-probe (nano-prober) to the bit line exit and word of formation
Line exit applies voltage, completes the electrical testing in region to be measured；Wherein, as shown in figure 8, after showing progress circuit mending
The electric current of bit line exit and the test mode of voltage.
Embodiment two
Embodiment according to the present invention provides a kind of three-dimensional storage electrical testing structure of short process stage, comprising:
The three-dimensional storage of short process stage (array area there is no through-hole)；
The bit line exit being formed in the region to be measured of the three-dimensional storage of short process stage；
The wordline exit being formed in the stepped region of the three-dimensional storage of short process stage.
Embodiment according to the present invention, bit line exit are formed in the polysilicon plug that channel hole is exposed in region to be measured
On.
Embodiment according to the present invention, wordline exit are formed on the grid layer exposed in stepped region.
Embodiment according to the present invention, bit line exit and wordline exit are tungsten.
In the present invention, carry out being ground to exposing by the channel hole in region to be measured in the three-dimensional storage to short process stage
Polysilicon plug, and deposited metal forms bit line exit beyond the Great Wall in the polycrystalline silicon of exposing；And its stepped region is ground to
Expose all grid layers, and deposited metal forms wordline exit on the grid layer of exposing, the circuit for realizing wordline is repaired
The circuit mending with bit line is mended, and the endpoint by being formed to circuit mending applies voltage, realizes three to short process stage
Tie up the electrical testing of memory；It can effectively ensure the feasibility of front-end process, and then to improve three-dimensional storage finished product
Yield provide a strong guarantee.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Subject to enclosing.
Claims (8)
1. a kind of three-dimensional storage electric test method of short process stage characterized by comprising
The three-dimensional storage of short process stage is provided, the array area of the three-dimensional storage of the short process stage there is no through-hole；
The channel hole in region to be measured in the three-dimensional storage of the short process stage is ground to exposing polysilicon plug, and is being exposed
Polycrystalline silicon beyond the Great Wall deposited metal formed bit line exit；
Stepped region in the three-dimensional storage of the short process stage is ground to exposing all grid layers, and in the grid of exposing
Deposited metal forms wordline exit on layer；
Voltage is applied to the bit line exit and the wordline exit, completes the electrical testing in region to be measured.
2. the method according to claim 1, wherein
Using chemical mechanical milling tech along the three-dimensional storage that third direction grinds the short process stage region to be measured
Channel hole is to exposing polysilicon plug；
The three-dimensional storage of the short process stage is ground along first direction or second direction using chemical mechanical milling tech
In stepped region to exposing all grid layers.
3. the method according to claim 1, wherein
Deposited metal forms bit line exit to the polycrystalline silicon in exposing beyond the Great Wall, specifically: revealed by focused ion beam
Deposits tungsten forms bit line exit to polycrystalline silicon out beyond the Great Wall；
On the grid layer of exposing deposited metal formed wordline exit, specifically: by focused ion beam exposing grid
Deposits tungsten forms wordline exit on layer.
4. the method according to claim 1, wherein by nano-probe to the bit line exit and the word
Line exit applies voltage, completes the electrical testing in region to be measured.
5. a kind of three-dimensional storage electrical testing structure of short process stage characterized by comprising
The three-dimensional storage of short process stage；
The bit line exit being formed in the region to be measured of the three-dimensional storage of the short process stage；
The wordline exit being formed in the stepped region of the three-dimensional storage of the short process stage.
6. structure according to claim 5, which is characterized in that the bit line exit is formed in the region Zhong Gou to be measured
The polycrystalline silicon that road hole is exposed is beyond the Great Wall.
7. structure according to claim 5, which is characterized in that the wordline exit is formed in the grid exposed in stepped region
On the layer of pole.
8. structure according to claim 5, which is characterized in that the bit line exit and the wordline exit are metal
Tungsten.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711138160.2A CN107946202B (en) | 2017-11-16 | 2017-11-16 | The three-dimensional storage electric test method and test structure of short process stage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711138160.2A CN107946202B (en) | 2017-11-16 | 2017-11-16 | The three-dimensional storage electric test method and test structure of short process stage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107946202A CN107946202A (en) | 2018-04-20 |
| CN107946202B true CN107946202B (en) | 2018-12-14 |
Family
ID=61932552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711138160.2A Active CN107946202B (en) | 2017-11-16 | 2017-11-16 | The three-dimensional storage electric test method and test structure of short process stage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107946202B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111243974B (en) * | 2020-01-16 | 2023-01-13 | 长江存储科技有限责任公司 | Method for calibrating short circuit between 3D NAND bit line and word line |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103512508A (en) * | 2012-06-25 | 2014-01-15 | 中国科学院微电子研究所 | Semiconductor device testing method |
| CN106876367A (en) * | 2017-03-07 | 2017-06-20 | 长江存储科技有限责任公司 | Three-dimensional storage test structure and preparation method thereof, method of testing |
| CN106920797A (en) * | 2017-03-08 | 2017-07-04 | 长江存储科技有限责任公司 | Memory construction and preparation method thereof, the method for testing of memory |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6717222B2 (en) * | 2001-10-07 | 2004-04-06 | Guobiao Zhang | Three-dimensional memory |
| JP4302965B2 (en) * | 2002-11-01 | 2009-07-29 | 株式会社日立ハイテクノロジーズ | Semiconductor device manufacturing method and manufacturing system thereof |
-
2017
- 2017-11-16 CN CN201711138160.2A patent/CN107946202B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103512508A (en) * | 2012-06-25 | 2014-01-15 | 中国科学院微电子研究所 | Semiconductor device testing method |
| CN106876367A (en) * | 2017-03-07 | 2017-06-20 | 长江存储科技有限责任公司 | Three-dimensional storage test structure and preparation method thereof, method of testing |
| CN106920797A (en) * | 2017-03-08 | 2017-07-04 | 长江存储科技有限责任公司 | Memory construction and preparation method thereof, the method for testing of memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107946202A (en) | 2018-04-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6225626B1 (en) | Through-the-substrate investigation of flip chip IC's | |
| CN102810492B (en) | Process monitoring method after metal gate CMP | |
| CN102456538B (en) | Method for unsealing plastically-packaged apparatus containing un-passivated metal layer structure | |
| CN102565680B (en) | The failure analysis method of semiconductor device | |
| CN104465400B (en) | Preparation and in-situ characterization method of residue-free optical photoresist graphene FET | |
| CN107946202B (en) | The three-dimensional storage electric test method and test structure of short process stage | |
| CN106298565B (en) | The preparation method and test method of semi-conductor test structure | |
| CN101459207B (en) | Manufacturing process for Au/Cr-CZT combination electrode | |
| CN106449465B (en) | Method for testing single bit on memory chip | |
| CN105334086A (en) | Preparation method of TEM sample and TEM sample | |
| CN106373905A (en) | Locating method for electric leakage point in gate oxide | |
| CN106971952B (en) | Semiconductor device failure analyzes sample and preparation method thereof, failure analysis method | |
| CN105206506B (en) | The processing method of wafer | |
| JP2715288B2 (en) | Method of manufacturing test piece for defect inspection of semiconductor device | |
| CN104317173B (en) | A method of improving stripping technology yield rate | |
| US20120178189A1 (en) | Method for forming an over pad metalization (opm) on a bond pad | |
| CN107993949A (en) | The test method of three-dimensional storage bit line capacitance | |
| CN101908465A (en) | Method for removing residues after chemical mechanical polishing | |
| Gaidis | Magnetic Back‐End Technology | |
| CN105345651B (en) | A kind of chip cross-section burnishing device and polishing method | |
| CN211088241U (en) | Semiconductor structure for improving identification degree of bottom metal and welding pad | |
| JP2003322599A (en) | Method of preparing sample for scanning probe microscope | |
| De Nardi et al. | EEPROM Failure Analysis Methodology: Can Programmed Charges be Measured Directly by Electrical Techniques of Scanning Probe Microscopy (SPM)? | |
| CN105161614A (en) | Magnetic tunnel junction nanometer unit structure and preparation method therefor | |
| CN101521181B (en) | Preparation method of single electron memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |