CN107770464B - Television with multifunctional charge and discharge management system - Google Patents

Television with multifunctional charge and discharge management system Download PDF

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Publication number
CN107770464B
CN107770464B CN201711318762.6A CN201711318762A CN107770464B CN 107770464 B CN107770464 B CN 107770464B CN 201711318762 A CN201711318762 A CN 201711318762A CN 107770464 B CN107770464 B CN 107770464B
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capacitor
resistor
pin
management chip
voltage
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CN107770464A (en
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周源
陈建生
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Huizhou Macc Electronics Co ltd
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Huizhou Macc Electronics Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/63—Generation or supply of power specially adapted for television receivers
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or discharging batteries or for supplying loads from batteries
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or discharging batteries or for supplying loads from batteries
    • H02J7/50—Circuit arrangements for charging or discharging batteries or for supplying loads from batteries acting upon multiple batteries simultaneously or sequentially
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/443—OS processes, e.g. booting an STB, implementing a Java virtual machine in an STB or power management in an STB
    • H04N21/4436—Power management, e.g. shutting down unused components of the receiver

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Direct Current Feeding And Distribution (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Secondary Cells (AREA)

Abstract

本发明涉及一种多功能充电和放电管理系统的电视，其特征在于，所述的电视内设置有电视驱动板，该电视驱动板通过LED照明管理电路驱动LED灯照明,通过手机充电管理电路对手机充电，通过电池充电管理电路对18650电池组充电，通过DC电源管理电路驱动液晶屏模组和喇叭。本发明的优点是：不受市电供电的影响和限制，在停电或者市电供电不稳、紧缺的情况下，产品可以使用太阳能，风力发电组，等外部DC电源给用电器进行充电,从而可以利用用电器内部电池组维持正常工作一定时间。

The invention relates to a TV with a multifunctional charging and discharging management system. It is characterized in that the TV is equipped with a TV driving board. The TV driving board drives LED lighting through an LED lighting management circuit and controls the lighting through a mobile phone charging management circuit. For mobile phone charging, the 18650 battery pack is charged through the battery charging management circuit, and the LCD screen module and speaker are driven through the DC power management circuit. The advantage of the invention is that it is not affected and restricted by the mains power supply. In the case of power outage or unstable or shortage of mains power supply, the product can use solar energy, wind power generation group, and other external DC power sources to charge electrical appliances. The internal battery pack of the electrical appliance can be used to maintain normal operation for a certain period of time.

Description

Television with multifunctional charge and discharge management system
Technical Field
The invention relates to a television with a multifunctional charge and discharge management system.
Background
The traditional television and other electrical appliances only have the basic functions of a television, and do not have the functions of charging a battery by an external power supply, LED illumination, quick charging of a mobile phone (QC 3.0 quick charging protocol) and the like. The function is single, can not satisfy people's actual demand.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a television with a multifunctional charge and discharge management system, which has the following technical scheme:
the television of the multifunctional charging and discharging management system is characterized in that a television driving board is arranged in the television, the television driving board drives an LED lamp to illuminate through an LED illumination management circuit, a mobile phone is charged through a mobile phone charging management circuit, a 18650 battery pack is charged through a battery charging management circuit, and a liquid crystal display module and a loudspeaker are driven through a DC power supply management circuit.
The LED lighting management circuit comprises a power management chip UM1, a 12V standard DC voltage is input to a 1 st pin of the power management chip UM1 after being filtered by a capacitor CM7, one end of the capacitor CM8 is connected to a 2 nd pin of the power management chip UM1, the other end of the capacitor CM8 is connected to a 3 rd pin of the power management chip UM1, one end of the capacitor CM7 is grounded, and a 5 th pin of the power management chip UM1 is grounded after being connected to the ground through a series resistor RM 10; after the resistor RM9, the resistor RM18, the resistor RM11 and the capacitor CM9 are connected in parallel, one end of the resistor RM9 is connected to the 4 th pin of the power management chip UM1, the other end of the resistor RM9 is connected to the STB port of the circuit board, the collector of the NPN transistor QM1 is connected with one end of the resistor RM18, the emitter of the NPN transistor QM is connected with one end of the capacitor CM9 and grounded, the base is connected with one end of the resistor RM11, a resistor RM12 is connected in series between the other end of the resistor RM9 and the other end of the resistor RM18, and the other end of the capacitor CM9 is connected to a button PWR_ON/OFF_A;
the 12V standard DC voltage is input to the 1 st pin of the power management chip UM2 after being filtered by the capacitor CM11, one end of the capacitor CM12 is connected to the 2 nd pin of the power management chip UM2, the other end of the capacitor CM12 is connected to the 3 rd pin of the power management chip UM2, one end of the capacitor CM11 is grounded, and the 5 th pin of the power management chip UM2 is grounded after being connected to the ground through the series resistor RM 14; after the resistor RM13, the resistor RM19, the resistor RM15 and the capacitor CM13 are connected in parallel, one end of the resistor RM13 is connected to the 4 th pin of the power management chip UM2, the other end is connected to the STB port of the circuit board, the collector of the NPN transistor QM2 is connected with one end of the resistor RM19, the emitter is connected with one end of the capacitor CM13 and grounded, the base is connected with one end of the resistor RM15, a resistor RM17 is connected in series between the other end of the resistor RM13 and the other end of the resistor RM19, the other end of the capacitor CM13 is connected to the button PWR_ON/OFF_B, the 6 th pin of the power management chip UM2 outputs voltage, and the voltage is filtered to the socket CN2 after being connected in parallel through the capacitor CM6 and the capacitor CM 51.
The mobile phone charging management circuit comprises a voltage management chip UD4, SYS_VCC standard DC voltage is input to a 3 RD pin of the voltage management chip UD4 after being subjected to capacitance-to-ground filtering through a capacitor CD2 and a capacitor CD59 in parallel connection, one end of a resistor RD27 is connected to the 3 RD pin of the voltage management chip UD4, the other end of the resistor RD27 is connected with a 5 th pin of the voltage management chip UD4 and one end of a resistor RD28, and the other end of the resistor RD28 is connected with a 1 st pin of the voltage management chip UD4 and is grounded at the same time; the capacitor CD32 is connected with the 6 th pin of the voltage management chip UD4, the other end is connected with the 2 nd pin of the voltage management chip UD4 and one end of the resonant inductor L4, the other end of the resonant inductor L4 is connected with one end of the capacitor CD38 and one end of the resistor RD26, the other end of the capacitor CD38 is connected with the 4 th pin of the voltage management chip UD4, one end of the resistor RD29 and one end of the resistor RD30, the other end of the resistor RD29 is connected with the other end of the resistor RD26, the 2 nd pin of the voltage management chip UD4 outputs voltage, the voltage is filtered in parallel through the capacitor CD33, the capacitor CD34 and the polar capacitor ED4 and then outputs 12V/USB voltage, the 12V/USB voltage is connected with the socket CN1B through an electronic wire, the positive electrode of the polar capacitor ED4 is connected with the socket CN1A, the negative electrode is grounded, the 12V/USB voltage is input to the fuse F1 through the socket CN1B, the 12V/USB voltage is filtered in parallel through the polar capacitor CE1 and then input to the power management chip U3, and the positive electrode of the capacitor D4 is connected with the fuse F1 through the cathode 4; the 1 st pin of power management chip U3 is connected with the 3 rd pin of protocol chip U1, resonant inductor L2's one end is connected with the 5 th pin of power management chip U3, 6 th pin and the one end of electric capacity C7, the other end is connected in series between the 2 nd pin of power management chip U3 and 3 rd pin through parallelly connected resistance R2 and resistance R7, the other end of electric capacity C7 is connected with the one end of resistance R11, the other end of resistance R11 links to each other with the 7 th pin of power management chip U3, the 3 rd pin links to each other and ground, the voltage that power management chip U3 output is through parallelly connected polarity electric capacity CE3 and electric capacity C5 to ground filtration before exporting socket USB1, the one end of resistance R8 is connected with the one end of resistance R2 and the positive pole of polarity electric capacity CE3, the negative pole of polarity electric capacity CE3 is grounded through serially connected resistance R9, the one end of resistance R1 is connected with the positive pole of polarity electric capacity CE3 and socket 1, the other end inserts the 5 th pin of power management chip U3, the other end of electric capacity C6 is connected with the ground connection between power management chip U3 and the 7 th pin of power management chip U1, the other end is connected with the USB1, the USB1 and the USB 2 th pin is connected with the USB 2.
The battery charging management comprises a charging chip UD10, wherein a DC power supply outside the charging chip UD10 is connected to a P1 port, the P1 port is connected to a drain electrode of a MOS tube QD7 through a switch CN7, a grid electrode of the MOS tube QD7 is connected IN series with a resistor RD44 and then grounded, and the source electrode is filtered to the ground through a capacitor CD62, a capacitor CD66 and a capacitor CD47 which are connected IN parallel to output DC_IN voltage; the DC_IN voltage outputs stable voltage to the MOS tube QD4, the PDONOFF network is connected with the base electrode of the triode QD6 after passing through a series resistor RD52, the collector electrode of the triode QD6 is connected with one end of a resistor RD40 and one end of a resistor RD42 through a series resistor RD49, the emitter electrode of the triode QD6 is grounded, one end of the resistor RD42 is connected with one end of a capacitor CD37 and the grid electrode of the MOS tube QD4, the drain electrode of the MOS tube QD4 outputs VCC_IN voltage after filtering the ground through a parallel capacitor CD35, and the other end of the resistor RD40 and the other end of the capacitor CD37 are connected with the source electrode of the MOS tube QD 4; after the VCC_IN voltage is connected to the drains of the MOS transistors QD11 and QD10, the gates of the MOS transistors QD11 and QD10 are connected to the 4 th pin of the charging chip UD10 through a series resistor RD55, the 3 RD pin of the charging chip UD10 is connected to the source of the MOS transistor QD11 and the source of the MOS transistor QD10 through a series resistor RD53, the drain of the MOS transistor QD11 is connected to one end of a capacitor CD6, the other end of the capacitor CD6 is grounded, the 1 st pin of the charging chip UD10 is connected to one end of a capacitor CD84 and one end of a resistor RD81, the other end of the resistor RD81 is connected to the drain of the MOS transistor QD10, one end of a capacitor CD83 and the 2 nd pin of the charging chip UD10, the other end of the capacitor CD83 and the other end of the capacitor CD84 are grounded, the polarity capacitor ED5 is connected IN parallel with the capacitor CD65, the positive electrode of the resistor RD81 is grounded, one end of the capacitor CD65 is connected to the drain of the MOS transistor QD12, the gate of the MOS transistor QD12 is connected to the first 18 pin of the charging chip QD10 through a series resistor RD56, the other end of the MOS transistor QD12 is connected to the first end of the capacitor D18 pin of the charging chip QD10, the other end of the capacitor CD13 is connected to the first end of the capacitor CD7, and the first end of the capacitor CD7 is connected to the capacitor CD7; the other end of the resonant inductor LD5 is connected to one end of the resistor RD102 and one end of the resistor RD73, the other end of the resistor RD102 is connected to one end of the capacitor CD86 and the 13 th pin of the charging chip UD10,
the other end of the capacitor CD86 is connected with one end of the capacitor CD87 and then grounded, the other end of the capacitor CD87 is connected with the 12 th pin of the charging chip UD10 and one end of the resistor RD103, the other end of the resistor RD103 is connected with the other end of the resistor RD73, the polarity capacitor ED62, the capacitor CD67 and the capacitor CD57 are connected in parallel, the negative electrode of the polarity capacitor ED62 is grounded, the positive electrode of the polarity capacitor ED62 is connected with the other end of the resistor RD73, the capacitor CD57 is connected with a BARRY_OUT power supply, and the battery pack is charged 18650 after passing through the mechanical switch CN61 and the socket CNB1 in sequence; the 10 th pin of the charging chip UD10 is connected with a resistor RD71 in series and then connected with the port of the STB; the 8 th pin of the charging chip UD10 is connected into an SDA port after passing through a series resistor RD50, the 9 th pin is connected into an SCL port after passing through a series resistor RD86, a capacitor CD49 is connected in parallel with a capacitor CD70, one end of the capacitor CD49 is connected between the 8 th pin of the charging chip UD10 and the resistor RD50, one end of the capacitor CD70 is connected between the 9 th pin of the charging chip UD10 and the resistor RD86, and the other ends of the capacitor CD49 and the capacitor CD70 are grounded; the 6 th pin of the charging chip UD10 is connected to one end of the capacitor CD85, one end of the resistor RD66 and one end of the resistor RD78, the other end of the capacitor CD85 and the other end of the resistor RD66 are connected to one end of the capacitor CD71 and then grounded, the other end of the capacitor CD71 is connected to the 20 th pin of the power chip UD10 and one end of the resistor RD82, the other end of the resistor RD82 is connected to the negative electrode of the diode DD61, the positive electrode of one diode DD61 is connected to vcc_in voltage, the positive electrode of the other diode DD61 is connected to 18650 battery pack, and the other end of the resistor RD78 is connected to vcc_in voltage.
5. The television of the multifunctional charge and discharge management system according to claim 1, wherein the DC power management circuit comprises a power management chip UD1, wherein vcc_in power is connected to the anodes of a diode DD3 and a diode DD7 after being subjected to capacitive filtering by a CD42, is connected to the anodes of the diode DD3 and the diode DD7 after being subjected to capacitive filtering by an electrolytic capacitor ED2, and is output to a sys_vcc power network, the barrey_out power is connected to the anodes of a diode DD4 and a diode DD8 after being subjected to capacitive filtering by a capacitor CD76, and the barrey_out power is output to the sys_vcc power network after being subjected to capacitive filtering by an electrolytic capacitor ED 2; the SYS_VCC voltage is filtered to the ground after passing through the parallel connection of the capacitor CD4, the capacitor CD8 and the capacitor CD9, and is input to the 4 th, 5 th and 6 th pins of the power management chip UD1, the 1 st pin and the 10 th pin of the power management chip UD1 are grounded, one end of the resistor RD2 is connected with the 4 th, 5 th and 6 th pins of the power management chip UD1 and one end of the resistor RD1, the other end is connected with one end of the resistor RD23, one end of the capacitor CD 25, one end of the capacitor CD30, the first 10 th, 12 th pins of the power management chip UD1, one end of the resistor RD18 and one end of the resistor RD3, the other end of the resistor RD23 is connected to an EN port, the other end of the resistor RD3 is connected with one end of the capacitor CD31 and grounded, the other end of the capacitor CD31 is connected to the first pin 8 th pin of the power management chip UD1 and the other end of the electronic RD18, the other end of the resistor RD1 is connected to the first pin 11 th pin of the power management chip UD1, one end of the other end of the capacitor RD3 is connected to the first pin 7 LD 1, the other end of the capacitor RD6 and the other end of the capacitor RD2 is connected to the first pin of the capacitor UD1, the other end of the capacitor RD6 and the capacitor RD2 is connected to the capacitor 3, the other end of the capacitor 3 is connected to the capacitor 3 and the capacitor 3 is connected to the capacitor 3, the capacitor is connected to the capacitor 3 and the capacitor is connected to the capacitor.
The invention has the advantages that: the electric appliance is not influenced and limited by the mains supply, and under the condition of power failure or unstable and shortage of the mains supply, the electric appliance can be charged by external DC power sources such as solar energy, wind power generation sets and the like, so that the battery pack in the electric appliance can be used for maintaining normal operation for a certain time. Meanwhile, when the commercial power is supplied, the battery pack can be automatically charged, the battery pack can be charged while being supported to work, the battery can be automatically cut off from discharging, the service life of the battery is ensured, and the standby charging can also be supported. Under the condition that normal operation of an electric appliance is not affected, the three functions of an LED lighting system, a mobile phone rapid charging system and a battery pack charging are integrated into a whole, and the integrated television is integrated into a television, so that a customer can enjoy the functions of the multifunctional charging and discharging system on the television.
Drawings
Fig. 1 is a block diagram of the main structure of the present invention.
Fig. 2 is a circuit diagram of LED lighting management.
Fig. 3 is a circuit diagram of a mobile phone charging management.
Fig. 4 is a battery charge management circuit diagram.
Fig. 5 is a DC power management circuit diagram.
Detailed Description
The invention will be further described with reference to specific embodiments, and advantages and features of the invention will become apparent from the description. These examples are merely exemplary and do not limit the scope of the invention in any way. It will be understood by those skilled in the art that various changes and substitutions of details and forms of the technical solution of the present invention may be made without departing from the spirit and scope of the present invention, but these changes and substitutions fall within the scope of the present invention.
Referring to fig. 1 to 5, the invention relates to a television with a multifunctional charge and discharge management system, wherein a television driving board is arranged in the television, the television driving board drives an LED lamp to illuminate through an LED illumination management circuit, a mobile phone is charged through a mobile phone charge management circuit, a 18650 battery pack is charged through a battery charge management circuit, and a liquid crystal screen module and a loudspeaker are driven through a DC power management circuit.
The LED lighting management circuit comprises a power management chip UM1, a 12V standard DC voltage is input to a 1 st pin of the power management chip UM1 after being filtered by a capacitor CM7, one end of the capacitor CM8 is connected to a 2 nd pin of the power management chip UM1, the other end of the capacitor CM8 is connected to a 3 rd pin of the power management chip UM1, one end of the capacitor CM7 is grounded, and a 5 th pin of the power management chip UM1 is grounded after being connected to the ground through a series resistor RM 10; after the resistor RM9, the resistor RM18, the resistor RM11 and the capacitor CM9 are connected in parallel, one end of the resistor RM9 is connected to the 4 th pin of the power management chip UM1, the other end of the resistor RM9 is connected to the STB port of the circuit board, the collector of the NPN transistor QM1 is connected with one end of the resistor RM18, the emitter of the NPN transistor QM is connected with one end of the capacitor CM9 and grounded, the base is connected with one end of the resistor RM11, a resistor RM12 is connected in series between the other end of the resistor RM9 and the other end of the resistor RM18, and the other end of the capacitor CM9 is connected to a button PWR_ON/OFF_A;
the 12V standard DC voltage is input to the 1 st pin of the power management chip UM2 after being filtered by the capacitor CM11, one end of the capacitor CM12 is connected to the 2 nd pin of the power management chip UM2, the other end of the capacitor CM12 is connected to the 3 rd pin of the power management chip UM2, one end of the capacitor CM11 is grounded, and the 5 th pin of the power management chip UM2 is grounded after being connected to the ground through the series resistor RM 14; after the resistor RM13, the resistor RM19, the resistor RM15 and the capacitor CM13 are connected in parallel, one end of the resistor RM13 is connected to the 4 th pin of the power management chip UM2, the other end is connected to the STB port of the circuit board, the collector of the NPN transistor QM2 is connected with one end of the resistor RM19, the emitter is connected with one end of the capacitor CM13 and grounded, the base is connected with one end of the resistor RM15, a resistor RM17 is connected in series between the other end of the resistor RM13 and the other end of the resistor RM19, the other end of the capacitor CM13 is connected to the button PWR_ON/OFF_B, the 6 th pin of the power management chip UM2 outputs voltage, and the voltage is filtered to the socket CN2 after being connected in parallel through the capacitor CM6 and the capacitor CM 51.
The mobile phone charging management circuit comprises a voltage management chip UD4, SYS_VCC standard DC voltage is input to a 3 RD pin of the voltage management chip UD4 after being subjected to capacitance-to-ground filtering through a capacitor CD2 and a capacitor CD59 in parallel connection, one end of a resistor RD27 is connected to the 3 RD pin of the voltage management chip UD4, the other end of the resistor RD27 is connected with a 5 th pin of the voltage management chip UD4 and one end of a resistor RD28, and the other end of the resistor RD28 is connected with a 1 st pin of the voltage management chip UD4 and is grounded at the same time; the capacitor CD32 is connected with the 6 th pin of the voltage management chip UD4, the other end is connected with the 2 nd pin of the voltage management chip UD4 and one end of the resonant inductor L4, the other end of the resonant inductor L4 is connected with one end of the capacitor CD38 and one end of the resistor RD26, the other end of the capacitor CD38 is connected with the 4 th pin of the voltage management chip UD4, one end of the resistor RD29 and one end of the resistor RD30, the other end of the resistor RD29 is connected with the other end of the resistor RD26, the 2 nd pin of the voltage management chip UD4 outputs voltage, the voltage is filtered in parallel through the capacitor CD33, the capacitor CD34 and the polar capacitor ED4 and then outputs 12V/USB voltage, the 12V/USB voltage is connected with the socket CN1B through an electronic wire, the positive electrode of the polar capacitor ED4 is connected with the socket CN1A, the negative electrode is grounded, the 12V/USB voltage is input to the fuse F1 through the socket CN1B, the 12V/USB voltage is filtered in parallel through the polar capacitor CE1 and then input to the power management chip U3, and the positive electrode of the capacitor D4 is connected with the fuse F1 through the cathode 4; the 1 st pin of power management chip U3 is connected with the 3 rd pin of protocol chip U1, resonant inductor L2's one end is connected with the 5 th pin of power management chip U3, 6 th pin and the one end of electric capacity C7, the other end is connected in series between the 2 nd pin of power management chip U3 and 3 rd pin through parallelly connected resistance R2 and resistance R7, the other end of electric capacity C7 is connected with the one end of resistance R11, the other end of resistance R11 links to each other with the 7 th pin of power management chip U3, the 3 rd pin links to each other and ground, the voltage that power management chip U3 output is through parallelly connected polarity electric capacity CE3 and electric capacity C5 to ground filtration before exporting socket USB1, the one end of resistance R8 is connected with the one end of resistance R2 and the positive pole of polarity electric capacity CE3, the negative pole of polarity electric capacity CE3 is grounded through serially connected resistance R9, the one end of resistance R1 is connected with the positive pole of polarity electric capacity CE3 and socket 1, the other end inserts the 5 th pin of power management chip U3, the other end of electric capacity C6 is connected with the ground connection between power management chip U3 and the 7 th pin of power management chip U1, the other end is connected with the USB1, the USB1 and the USB 2 th pin is connected with the USB 2.
The 12V/USB voltage is connected in series with a fuse, is filtered by connecting a polar capacitor CE1 and a capacitor C1 in parallel to the ground, and is then input to a 4 th pin of a power management chip U3, is connected in series between a 2 nd pin and a 3 rd pin of the power management chip UM2 after being connected with a resistor R2 in parallel with a resistor R7 through a resonant inductor L2, is used for detecting output current by sampling the pressure difference between the 2 nd pin and the 3 rd pin, is connected in series with a resistor R9 through a resistor R8 to form a voltage feedback circuit, the feedback voltage is provided by a protocol chip U1 (QC 3.0 protocol chip), the voltage output by the power management chip U3 is filtered by connecting the CE3 and the C5 capacitor in parallel to the ground and is then output to the USB1, and the mobile phone is charged through a USB1 socket. The mobile phone with QC3.0 protocol charges to output Q3.0 protocol voltage, and the mobile phone without QC3.0 protocol charges to output standard 5V voltage.
The battery charging management comprises a charging chip UD10, wherein a DC power supply outside the charging chip UD10 is connected to a P1 port, the P1 port is connected to a drain electrode of a MOS tube QD7 through a switch CN7, a grid electrode of the MOS tube QD7 is connected IN series with a resistor RD44 and then grounded, and the source electrode is filtered to the ground through a capacitor CD62, a capacitor CD66 and a capacitor CD47 which are connected IN parallel to output DC_IN voltage; the DC_IN voltage outputs stable voltage to the MOS tube QD4, the PDONOFF network is connected with the base electrode of the triode QD6 after passing through a series resistor RD52, the collector electrode of the triode QD6 is connected with one end of a resistor RD40 and one end of a resistor RD42 through a series resistor RD49, the emitter electrode of the triode QD6 is grounded, one end of the resistor RD42 is connected with one end of a capacitor CD37 and the grid electrode of the MOS tube QD4, the drain electrode of the MOS tube QD4 outputs VCC_IN voltage after filtering the ground through a parallel capacitor CD35, and the other end of the resistor RD40 and the other end of the capacitor CD37 are connected with the source electrode of the MOS tube QD 4; after the VCC_IN voltage is connected to the drains of the MOS transistors QD11 and QD10, the gates of the MOS transistors QD11 and QD10 are connected to the 4 th pin of the charging chip UD10 through a series resistor RD55, the 3 RD pin of the charging chip UD10 is connected to the source of the MOS transistor QD11 and the source of the MOS transistor QD10 through a series resistor RD53, the drain of the MOS transistor QD11 is connected to one end of a capacitor CD6, the other end of the capacitor CD6 is grounded, the 1 st pin of the charging chip UD10 is connected to one end of a capacitor CD84 and one end of a resistor RD81, the other end of the resistor RD81 is connected to the drain of the MOS transistor QD10, one end of a capacitor CD83 and the 2 nd pin of the charging chip UD10, the other end of the capacitor CD83 and the other end of the capacitor CD84 are grounded, the polarity capacitor ED5 is connected IN parallel with the capacitor CD65, the positive electrode of the resistor RD81 is grounded, one end of the capacitor CD65 is connected to the drain of the MOS transistor QD12, the gate of the MOS transistor QD12 is connected to the first 18 pin of the charging chip QD10 through a series resistor RD56, the other end of the MOS transistor QD12 is connected to the first end of the capacitor D18 pin of the charging chip QD10, the other end of the capacitor CD13 is connected to the first end of the capacitor CD7, and the first end of the capacitor CD7 is connected to the capacitor CD7; the other end of the resonant inductor LD5 is connected to one end of the resistor RD102 and one end of the resistor RD73, the other end of the resistor RD102 is connected to one end of the capacitor CD86 and the 13 th pin of the charging chip UD10,
the other end of the capacitor CD86 is connected with one end of the capacitor CD87 and then grounded, the other end of the capacitor CD87 is connected with the 12 th pin of the charging chip UD10 and one end of the resistor RD103, the other end of the resistor RD103 is connected with the other end of the resistor RD73, the polarity capacitor ED62, the capacitor CD67 and the capacitor CD57 are connected in parallel, the negative electrode of the polarity capacitor ED62 is grounded, the positive electrode of the polarity capacitor ED62 is connected with the other end of the resistor RD73, the capacitor CD57 is connected with a BARRY_OUT power supply, and the battery pack is charged 18650 after passing through the mechanical switch CN61 and the socket CNB1 in sequence; the 10 th pin of the charging chip UD10 is connected with a resistor RD71 in series and then connected with the port of the STB; the 8 th pin of the charging chip UD10 is connected into an SDA port after passing through a series resistor RD50, the 9 th pin is connected into an SCL port after passing through a series resistor RD86, a capacitor CD49 is connected in parallel with a capacitor CD70, one end of the capacitor CD49 is connected between the 8 th pin of the charging chip UD10 and the resistor RD50, one end of the capacitor CD70 is connected between the 9 th pin of the charging chip UD10 and the resistor RD86, and the other ends of the capacitor CD49 and the capacitor CD70 are grounded; the 6 th pin of the charging chip UD10 is connected to one end of the capacitor CD85, one end of the resistor RD66 and one end of the resistor RD78, the other end of the capacitor CD85 and the other end of the resistor RD66 are connected to one end of the capacitor CD71 and then grounded, the other end of the capacitor CD71 is connected to the 20 th pin of the power chip UD10 and one end of the resistor RD82, the other end of the resistor RD82 is connected to the negative electrode of the diode DD61, the positive electrode of one diode DD61 is connected to vcc_in voltage, the positive electrode of the other diode DD61 is connected to 18650 battery pack, and the other end of the resistor RD78 is connected to vcc_in voltage.
The PDONOFF network gives a high level, a switching circuit is formed by RD52 resistor and triode QD6, a low level is reversely output, MOS tube QD4 is controlled by limiting current of series resistor RD49 and resistor RD42, and a time sequence is controlled by parallel connection of resistor RD40 and capacitor CD37, so that MOS tube QD4 is conducted to output VCC_IN voltage. The VCC_IN voltage is input into the MOS tube QD11, the MOS tube QD11 is controlled by a UD10 charging chip, the battery charging voltage is output through a circuit formed by a resistor RD4 and a capacitor CD68 and a resonant inductor LD5, the battery charging voltage is output through a power supply filter circuit formed by a series current limiting resistor RD73 and an electrolytic capacitor ED62, a capacitor CD67 and a capacitor CD57, a mechanical switch CN61 is conducted, and the battery pack is charged through a socket CNB 1. In the charging process, charging indication prompts in two states are generated, and in the state 1, the electric appliance is turned on, charging lightning icon prompts can be generated on a screen, and charging saturation icon prompts can also be generated. And 2, turning off the electric appliance, prompting the charging of the electric appliance by the LED indicator lamp, turning off the charging indicator lamp when the charging is saturated, and turning on the saturation indicator lamp.
The DC power management circuit comprises a power management chip UD1, wherein a VCC_IN power supply is connected to the anodes of a diode DD3 and a diode DD7 after being subjected to capacitance filtering of a CD42, is connected to the cathodes of the diode DD3 and the diode DD7 and is output to a SYS_VCC power supply network after being subjected to capacitance filtering of an electrolytic capacitor ED2, a BARREY_OUT power supply is connected to the anodes of a diode DD4 and a diode DD8 after being subjected to capacitance filtering of a capacitor CD76, and the BARREY_OUT power supply is output to the SYS_VCC power supply network after being subjected to capacitance filtering of an electrolytic capacitor ED 2; the SYS_VCC voltage is filtered to the ground after passing through the parallel connection of the capacitor CD4, the capacitor CD8 and the capacitor CD9, and is input to the 4 th, 5 th and 6 th pins of the power management chip UD1, the 1 st pin and the 10 th pin of the power management chip UD1 are grounded, one end of the resistor RD2 is connected with the 4 th, 5 th and 6 th pins of the power management chip UD1 and one end of the resistor RD1, the other end is connected with one end of the resistor RD23, one end of the capacitor CD 25, one end of the capacitor CD30, the first 10 th, 12 th pins of the power management chip UD1, one end of the resistor RD18 and one end of the resistor RD3, the other end of the resistor RD23 is connected to an EN port, the other end of the resistor RD3 is connected with one end of the capacitor CD31 and grounded, the other end of the capacitor CD31 is connected to the first pin 8 th pin of the power management chip UD1 and the other end of the electronic RD18, the other end of the resistor RD1 is connected to the first pin 11 th pin of the power management chip UD1, one end of the other end of the capacitor RD3 is connected to the first pin 7 LD 1, the other end of the capacitor RD6 and the other end of the capacitor RD2 is connected to the first pin of the capacitor UD1, the other end of the capacitor RD6 and the capacitor RD2 is connected to the capacitor 3, the other end of the capacitor 3 is connected to the capacitor 3 and the capacitor 3 is connected to the capacitor 3, the capacitor is connected to the capacitor 3 and the capacitor is connected to the capacitor.
The SYS_VCC power supply network comprises a voltage dividing circuit of a switch control pin of the power management chip UD1, and an electronic R23 and a capacitor CD30 respectively form a current limiting resistor and a filter circuit of the switch control pin of the power management chip UD 1. The resistor RD3, the resistor RD18 and the capacitor CD31 form a power management chip UD1 management accounting and timing circuit, the SYS_VCC voltage is processed by the power management chip UD1 to output a voltage, and the voltage is filtered in parallel by the capacitor CD18, the capacitor CD19, the capacitor CD20 and the electrolytic capacitor ED3 to output a standard 12V voltage.

Claims (3)

1.多功能充电和放电管理系统的电视，其特征在于，所述的电视内设置有电视驱动板，该电视驱动板通过LED照明管理电路驱动LED灯照明,通过手机充电管理电路对手机充电，通过电池充电管理电路对18650电池组充电，通过DC电源管理电路驱动液晶屏模组和喇叭；1. A TV with a multifunctional charging and discharging management system, characterized in that the TV is equipped with a TV drive board, which drives LED lighting through an LED lighting management circuit and charges the mobile phone through a mobile phone charging management circuit. Charge the 18650 battery pack through the battery charging management circuit, and drive the LCD screen module and speaker through the DC power management circuit; 所述的LED照明管理电路包括电源管理芯片UM1,12V标准DC电压通过电容CM7滤波后输入到电源管理芯片UM1的第1脚，电容CM8的一端接入电源管理芯片UM1的第2脚，另一端接入电源管理芯片UM1的第3脚、电容CM7的一端并接地，电源管理芯片UM1的第5脚通过串联电阻RM10后接地；电阻RM9、电阻RM18、电阻RM11和电容CM9并联后，电阻RM9的一端接入电源管理芯片UM1的第4脚，另一端接入电路板的STB端口，NPN型晶体管QM1的集电极与电阻RM18的一端连接，发射极与电容CM9的一端连接并接地，基级与电阻RM11的一端连接，在电阻RM9的另一端与电阻RM18另一端之间串联一电阻电阻RM12，所述电容CM9的另一端接入按键PWR_ON/OFF_A;电源管理芯片UM1的第6脚输出电压，通过电容CM6和电容CM51并联对地滤波后输出到插座CN2；The LED lighting management circuit includes a power management chip UM1. The 12V standard DC voltage is filtered by the capacitor CM7 and then input to the first pin of the power management chip UM1. One end of the capacitor CM8 is connected to the second pin of the power management chip UM1, and the other end Connect the 3rd pin of the power management chip UM1 and one end of the capacitor CM7 to the ground. The 5th pin of the power management chip UM1 is connected to the ground through the series resistor RM10. After the resistor RM9, the resistor RM18, the resistor RM11 and the capacitor CM9 are connected in parallel, the resistor RM9 One end is connected to the 4th pin of the power management chip UM1, and the other end is connected to the STB port of the circuit board. The collector of the NPN transistor QM1 is connected to one end of the resistor RM18, the emitter is connected to one end of the capacitor CM9 and grounded, and the base is connected to the ground. One end of the resistor RM11 is connected, and a resistor RM12 is connected in series between the other end of the resistor RM9 and the other end of the resistor RM18. The other end of the capacitor CM9 is connected to the button PWR_ON/OFF_A; the pin 6 of the power management chip UM1 outputs the voltage. The capacitor CM6 and the capacitor CM51 are connected in parallel to the ground to filter and then output to the socket CN2; 12V标准DC电压通过电容CM11滤波后输入到电源管理芯片UM2的第1脚，电容CM12的一端接入电源管理芯片UM2的第2脚，另一端接入电源管理芯片UM2的第3脚、电容CM11的一端并接地，电源管理芯片UM2的第5脚通过串联电阻RM14后接地；电阻RM13、电阻RM19、电阻RM15和电容CM13并联后，电阻RM13的一端接入电源管理芯片UM2的第4脚，另一端接入电路板的STB端口，NPN型晶体管QM2的集电极与电阻RM19的一端连接，发射极与电容CM13的一端连接并接地，基级与电阻RM15的一端连接，在电阻RM13的另一端与电阻RM19另一端之间串联一电阻电阻RM17，所述电容CM13的另一端接入按键PWR_ON/OFF_B;电源管理芯片UM2的第6脚输出电压，通过电容CM6和电容CM51并联对地滤波后输出到插座CN2；The 12V standard DC voltage is filtered by the capacitor CM11 and then input to the first pin of the power management chip UM2. One end of the capacitor CM12 is connected to the second pin of the power management chip UM2, and the other end is connected to the third pin of the power management chip UM2 and the capacitor CM11. One end of the resistor is connected to the ground, and the fifth pin of the power management chip UM2 is connected to the ground through the series resistor RM14; after the resistor RM13, the resistor RM19, the resistor RM15 and the capacitor CM13 are connected in parallel, one end of the resistor RM13 is connected to the fourth pin of the power management chip UM2, and the other end is connected to the ground. One end is connected to the STB port of the circuit board, the collector of NPN transistor QM2 is connected to one end of resistor RM19, the emitter is connected to one end of capacitor CM13 and grounded, the base is connected to one end of resistor RM15, and the other end of resistor RM13 is connected to A resistor RM17 is connected in series between the other ends of the resistor RM19, and the other end of the capacitor CM13 is connected to the button PWR_ON/OFF_B; the output voltage of pin 6 of the power management chip UM2 is filtered by the capacitor CM6 and the capacitor CM51 in parallel and then output to the ground. Socket CN2; 所述的手机充电管理电路包括电压管理芯片UD4，SYS_VCC标准DC电压通过电容CD2和电容CD59电容并联对地滤波后输入到电压管理芯片UD4第3脚，电阻RD27的一端接入电压管理芯片UD4的第3脚，另一端与电压管理芯片UD4的第5脚以及电阻RD28的一端连接，该电阻RD28的另一端与电压管理芯片UD4的第1脚连接，并同时接地；电容CD32与电压管理芯片UD4的第6脚连接，另一端与电压管理芯片UD4的第2脚以及谐振电感L4的一端连接，该谐振电感L4的另一端与电容CD38的一端以及电阻RD26的一端连接，电容CD38的另一端与电压管理芯片UD4的第4脚、电阻RD29的一端以及电阻RD30的一端连接，电阻RD29的另一端与电阻RD26的另一端连接，电压管理芯片UD4的第2脚输出电压，电压通过电容CD33、电容CD34以及极性电容 ED4并联滤波后输出12V/USB电压，12V/USB电压通过插座CN1A用电子线连通插座CN1B，极性电容ED4的正极与插座CN1A连接，负极接地，12V/USB电压通过插座CN1B输入到保险丝F1，12V/USB电压经过串联保险丝F1，再通过极性电容CE1和电容C1并联对地滤波后再输入到电源管理芯片U3的第4脚，极性电容CE1的正极接入保险丝F1与电源管理芯片U3的第4脚之间，负极接地；电源管理芯片U3的第1脚与协议芯片U1的第3脚连接，谐振电感L2的一端与电源管理芯片U3的第5脚、第6脚以及电容C7的一端连接，另一端通过并联的电阻R2和电阻R7后在串联在电源管理芯片U3的第2脚和第3脚之间，电容C7的另一端与电阻R11的一端连接，电阻R11的另一端与电源管理芯片U3的第7脚、第3脚相连并接地，电源管理芯片U3输出的电压经过并联的极性电容CE3和电容C5对地滤波后再输出到插口USB1，电阻R8的一端与电阻R2的一端以及极性电容CE3的正极连接，另一端通过串联的电阻R9接地，极性电容CE3的负极接地，电阻R1的一端与极性电容CE3的正极以及插口USB1连接，另一端接入电源管理芯片U3的第5脚，电容C6的一端接地，另一端接入电源管理芯片U3的第5脚和电阻R1之间，电源管理芯片U3的第1脚、第2脚以及第6脚与插口USB1连接，该电源管理芯片U3的第2脚同时接地。The mobile phone charging management circuit includes a voltage management chip UD4. The SYS_VCC standard DC voltage is filtered by the capacitor CD2 and the capacitor CD59 in parallel to the ground and then input to the third pin of the voltage management chip UD4. One end of the resistor RD27 is connected to the voltage management chip UD4. The other end of pin 3 is connected to pin 5 of voltage management chip UD4 and one end of resistor RD28. The other end of resistor RD28 is connected to pin 1 of voltage management chip UD4 and grounded at the same time; capacitor CD32 is connected to voltage management chip UD4. Connect the 6th pin of The 4th pin of the voltage management chip UD4 is connected to one end of the resistor RD29 and one end of the resistor RD30. The other end of the resistor RD29 is connected to the other end of the resistor RD26. The 2nd pin of the voltage management chip UD4 outputs the voltage. The voltage passes through the capacitor CD33 and the capacitor CD34 and polar capacitor ED4 are filtered in parallel and output 12V/USB voltage. The 12V/USB voltage passes through socket CN1A and is connected to socket CN1B with an electronic wire. The positive pole of polar capacitor ED4 is connected to socket CN1A, and the negative pole is grounded. The 12V/USB voltage passes through socket CN1B. Input to fuse F1, the 12V/USB voltage passes through the series fuse F1, and then is filtered to ground through the polar capacitor CE1 and capacitor C1 in parallel, and then input to the 4th pin of the power management chip U3. The positive pole of the polar capacitor CE1 is connected to the fuse F1 and the 4th pin of the power management chip U3, the negative pole is connected to ground; the 1st pin of the power management chip U3 is connected to the 3rd pin of the protocol chip U1, and one end of the resonant inductor L2 is connected to the 5th and 6th pins of the power management chip U3. pin and one end of the capacitor C7, the other end is connected in series between the 2nd and 3rd pins of the power management chip U3 through the parallel resistor R2 and the resistor R7, the other end of the capacitor C7 is connected to one end of the resistor R11, the resistor The other end of R11 is connected to the 7th and 3rd pins of the power management chip U3 and grounded. The voltage output by the power management chip U3 is filtered to the ground by the parallel polarity capacitor CE3 and capacitor C5 and then output to the socket USB1, resistor R8 One end of the resistor R2 is connected to one end of the resistor R2 and the positive electrode of the polar capacitor CE3, the other end is connected to the ground through the series resistor R9, the negative electrode of the polar capacitor CE3 is connected to the ground, one end of the resistor R1 is connected to the positive electrode of the polar capacitor CE3 and the socket USB1, and the other end is connected to the positive electrode of the polar capacitor CE3 and the socket USB1. One end is connected to the 5th pin of the power management chip U3, one end of the capacitor C6 is connected to ground, the other end is connected between the 5th pin of the power management chip U3 and the resistor R1, the 1st, 2nd and 2nd pins of the power management chip U3 Pin 6 is connected to the socket USB1, and pin 2 of the power management chip U3 is connected to ground at the same time. 2.根据权利要求1所述的多功能充电和放电管理系统的电视，其特征在于，所述的电池充电管理包括充电芯片UD10，充电芯片UD10外部DC电源接入P1端口，该P1端口通过开关CN7接入MOS管QD7的漏极，该MOS管QD7的栅极串联电阻RD44后接地，源极通过并联的电容CD62、电容CD66和电容CD47后对地滤波输出DC_IN电压；DC_IN电压输出稳定电压到MOS管QD4，PDONOFF网络通过串联电阻RD52后与三极管QD6的基极连接，该三极管QD6的集电极通过串联电阻RD49与电阻RD40的一端、电阻RD42的一端连接，三极管QD6的发射极接地，电阻RD42的一端与电容CD37的一端以及MOS管QD4的栅极连接，MOS管QD4的漏极通过并联电容CD35对地滤波后输出VCC_IN电压，电阻RD40的另一端以及电容CD37的另一端均接入MOS管QD4的源极；VCC_IN电压接入至MOS管QD11、MOS管QD10的漏极后，MOS管QD11、MOS管QD10的栅极通过串联电阻RD55接入充电芯片UD10的第4脚，充电芯片UD10的第3脚通过串联电阻RD53接入MOS管QD11的源极以及MOS管QD10源极，该MOS管QD11的漏极与电容CD6的一端连接，电容CD6的另一端接地，充电芯片UD10的第1脚与电容CD84的一端以及电阻RD81的一端连接，电阻RD81的另一端与MOS管QD10的漏极、电容CD83的一端以及充电芯片UD10的第2脚相连，电容CD83的另一端以及电容CD84的另一端接地，极性电容ED5与电容CD65并联，极性电容的正极与电阻RD81的一端，负极接地，电容CD65的一端与MOS管QD12的漏极连接，MOS管QD12的栅极通过串联电阻RD56接入充电芯片UD10的第18脚，MOS管QD12的源极与MOS管QD13的漏极连接，该MOS管QD13的栅极通过串联电阻RD77接入充电芯片UD10的第15脚，MOS管QD13的源极与电容CD69的一端、充电芯片UD10的第14脚、电容CD68的一端连接并接地，电容CD68的另一端与电阻RD4连接，电阻RD4的另一端谐振电感LD5的一端、充电芯片UD10的第19脚以及电容CD64的一端连接，电容CD64的另一端接入充电芯片UD10的第17脚；谐振电感LD5的另一端与电阻RD102的一端、电阻RD73的一端连接，电阻RD102的另一端与电容CD86的一端以及充电芯片UD10的第13脚连接，2. The TV with a multifunctional charging and discharging management system according to claim 1, characterized in that the battery charging management includes a charging chip UD10, and the external DC power supply of the charging chip UD10 is connected to the P1 port, and the P1 port is connected through a switch. CN7 is connected to the drain of MOS tube QD7. The gate of MOS tube QD7 is connected in series with resistor RD44 and then connected to ground. The source is filtered to ground through parallel capacitors CD62, CD66 and CD47 and outputs DC_IN voltage; the DC_IN voltage outputs a stable voltage to The MOS tube QD4 and PDONOFF network are connected to the base of the transistor QD6 through the series resistor RD52. The collector of the transistor QD6 is connected to one end of the resistor RD40 and one end of the resistor RD42 through the series resistor RD49. The emitter of the transistor QD6 is grounded, and the resistor RD42 One end of the resistor is connected to one end of the capacitor CD37 and the gate of the MOS tube QD4. The drain of the MOS tube QD4 is filtered to the ground through the parallel capacitor CD35 and then outputs the VCC_IN voltage. The other end of the resistor RD40 and the other end of the capacitor CD37 are connected to the MOS tube. The source of QD4; after the VCC_IN voltage is connected to the drains of MOS tube QD11 and MOS tube QD10, the gates of MOS tube QD11 and MOS tube QD10 are connected to the 4th pin of the charging chip UD10 through the series resistor RD55. The third pin is connected to the source of MOS tube QD11 and the source of MOS tube QD10 through the series resistor RD53. The drain of the MOS tube QD11 is connected to one end of the capacitor CD6. The other end of the capacitor CD6 is connected to the ground. The first pin of the charging chip UD10 Connect one end of capacitor CD84 and one end of resistor RD81, the other end of resistor RD81 is connected to the drain of MOS tube QD10, one end of capacitor CD83 and the second pin of charging chip UD10, the other end of capacitor CD83 and the other end of capacitor CD84 The polar capacitor ED5 is connected to the ground in parallel with the capacitor CD65. The positive electrode of the polar capacitor is connected to one end of the resistor RD81 and the negative electrode is connected to the ground. One end of the capacitor CD65 is connected to the drain of the MOS tube QD12. The gate of the MOS tube QD12 is connected through the series resistor RD56. The 18th pin of the charging chip UD10 and the source of the MOS tube QD12 are connected to the drain of the MOS tube QD13. The gate of the MOS tube QD13 is connected to the 15th pin of the charging chip UD10 and the source of the MOS tube QD13 through the series resistor RD77. Connect one end of the capacitor CD69, the 14th pin of the charging chip UD10, and one end of the capacitor CD68 to ground. The other end of the capacitor CD68 is connected to the resistor RD4. The other end of the resistor RD4 is connected to one end of the resonant inductor LD5 and the 19th pin of the charging chip UD10. And one end of the capacitor CD64 is connected, and the other end of the capacitor CD64 is connected to the 17th pin of the charging chip UD10; the other end of the resonant inductor LD5 is connected to one end of the resistor RD102 and one end of the resistor RD73, and the other end of the resistor RD102 is connected to one end of the capacitor CD86 And the 13th pin connection of charging chip UD10, 电容CD86的另一端接入电容CD87的一端后接地，该电容CD87的另一端与充电芯片UD10的第12脚以及电阻RD103的一端连接，电阻RD103的另一端与电阻RD73的另一端连接，极性电容ED62、电容CD67以及电容CD57并联，该极性电容ED62的负极接地，正极与电阻RD73的另一端连接，电容CD57接入BARRERY_OUT电源，并依次经过机械开关CN61和插座CNB1后给18650电池组进行充电；充电芯片UD10的第10脚串联电阻RD71后接入STB端口；充电芯片UD10的第8脚通过串联电阻RD50后接入SDA端口，第9脚通过串联电阻RD86后接入SCL端口，电容CD49与电容CD70并联，该电容CD49的一端接入充电芯片UD10的第8脚与电阻RD50之间，电容CD70的一端接入充电芯片UD10第9脚和电阻RD86之间，电容CD49以及电容CD70的另一端接地；充电芯片UD10的第6脚与电容CD85的一端、电阻RD66的一端以及电阻RD78的一端连接，电容CD85的另一端以及电阻RD66的另一端与电容CD71的一端连接后接地，电容CD71的另一端与电源芯片UD10的第20脚、电阻RD82的一端连接，该电阻RD82的另一端与二极管DD61的负极连接，其中一二极管DD61的正极接入VCC_IN电压，另一二极管DD61的正极接入18650电池组，电阻RD78的另一端接入VCC_IN电压。The other end of capacitor CD86 is connected to one end of capacitor CD87 and then grounded. The other end of capacitor CD87 is connected to pin 12 of charging chip UD10 and one end of resistor RD103. The other end of resistor RD103 is connected to the other end of resistor RD73. The polarity Capacitor ED62, capacitor CD67 and capacitor CD57 are connected in parallel. The negative electrode of the polar capacitor ED62 is connected to the ground, and the positive electrode is connected to the other end of the resistor RD73. The capacitor CD57 is connected to the BARRERY_OUT power supply, and passes through the mechanical switch CN61 and the socket CNB1 in turn to the 18650 battery pack. Charging; the 10th pin of the charging chip UD10 is connected to the STB port through a series resistor RD71; the 8th pin of the charging chip UD10 is connected to the SDA port through a series resistor RD50, and the 9th pin is connected to the SCL port through a series resistor RD86, and the capacitor CD49 In parallel with the capacitor CD70, one end of the capacitor CD49 is connected between the 8th pin of the charging chip UD10 and the resistor RD50. One end of the capacitor CD70 is connected between the 9th pin of the charging chip UD10 and the resistor RD86. The other end of the capacitor CD49 and the capacitor CD70 One end is grounded; the 6th pin of the charging chip UD10 is connected to one end of the capacitor CD85, one end of the resistor RD66 and one end of the resistor RD78. The other end of the capacitor CD85 and the other end of the resistor RD66 are connected to one end of the capacitor CD71 and then grounded. The other end is connected to the 20th pin of the power chip UD10 and one end of the resistor RD82. The other end of the resistor RD82 is connected to the cathode of the diode DD61. The anode of one diode DD61 is connected to the VCC_IN voltage, and the anode of the other diode DD61 is connected to the 18650 For the battery pack, the other end of the resistor RD78 is connected to the VCC_IN voltage. 3.根据权利要求1所述的多功能充电和放电管理系统的电视，其特征在于，所述的DC电源管理电路包括电源管理芯片UD1，VCC_IN电源经过CD42电容滤波后接入二极管DD3和二极管DD7的正极，经过二极管DD3和二极管DD7的负极，并通过电解电容ED2后输出到SYS_VCC电源网络，BARRERY_OUT电源经过电容CD76滤波，将BARRERY_OUT电源连接二极管DD4和二极管DD8的正极，BARRERY_OUT电源通过电解电容ED2滤波输出到SYS_VCC电源网络；SYS_VCC电压经过并联的电容CD4、电容CD8和电容CD9后对地滤波，输入到电源管理芯片UD1的第4、5、6脚，该电源管理芯片UD1的第1脚和第10脚接地，电阻RD2的一端与电源管理芯片UD1的第4、5、6脚以及电阻RD1的一端连接，另一端与电阻RD23的一端、电阻RD25的一端、电容CD30的一端、电源管理芯片UD1的第10、12脚、电阻RD18的一端以及RD3的一端连接，该电阻RD23的另一端接入EN端口，电阻RD3的另一端与电容CD31的一端连接并接地，电容CD31的另一端接入电源管理芯片UD1的第8脚和电子RD18的另一端，电阻RD1的另一端接入电源管理芯片UD1的第11脚，电容CD3的一端接入电源管理芯片UD1的第7脚，另一端接入谐振电感LD6的一端以及电源管理芯片UD1的第2脚，谐振电感LD6的另一端与电容CD27的一端、电阻RD11的一端连接，电容CD27的另一端接入电源管理芯片UD1的第9脚、电阻RD11的另一端以及电阻RD24的一端连接，电阻RD24的另一端接地，SYS_VCC电压通过并联电容CD18、电容CD19、电容CD20和电解电容ED3滤波输出标准的12V电压。3. The TV with a multifunctional charging and discharging management system according to claim 1, characterized in that the DC power management circuit includes a power management chip UD1, and the VCC_IN power supply is filtered by the CD42 capacitor and then connected to the diode DD3 and the diode DD7. The positive electrode passes through the cathode of diode DD3 and diode DD7, and is output to the SYS_VCC power supply network through the electrolytic capacitor ED2. The BARRERY_OUT power supply is filtered by the capacitor CD76. The BARRERY_OUT power supply is connected to the anode of the diode DD4 and diode DD8. The BARRERY_OUT power supply is filtered by the electrolytic capacitor ED2. Output to the SYS_VCC power supply network; the SYS_VCC voltage is filtered to ground after passing through the parallel capacitors CD4, CD8 and CD9, and then input to the 4th, 5th and 6th pins of the power management chip UD1. The 1st and 2nd pins of the power management chip UD1 Pin 10 is connected to ground. One end of the resistor RD2 is connected to the 4th, 5th and 6th pins of the power management chip UD1 and one end of the resistor RD1. The other end is connected to one end of the resistor RD23, one end of the resistor RD25, one end of the capacitor CD30 and the power management chip UD1. Pins 10 and 12 are connected to one end of the resistor RD18 and one end of RD3. The other end of the resistor RD23 is connected to the EN port. The other end of the resistor RD3 is connected to one end of the capacitor CD31 and grounded. The other end of the capacitor CD31 is connected to the power supply. The 8th pin of the management chip UD1 and the other end of the electronic RD18, the other end of the resistor RD1 is connected to the 11th pin of the power management chip UD1, one end of the capacitor CD3 is connected to the 7th pin of the power management chip UD1, and the other end is connected to the resonance One end of the inductor LD6 is connected to the 2nd pin of the power management chip UD1. The other end of the resonant inductor LD6 is connected to one end of the capacitor CD27 and one end of the resistor RD11. The other end of the capacitor CD27 is connected to the 9th pin of the power management chip UD1 and the resistor RD11. The other end of the resistor is connected to one end of the resistor RD24, and the other end of the resistor RD24 is connected to ground. The SYS_VCC voltage is filtered through the parallel capacitor CD18, CD19, CD20 and electrolytic capacitor ED3 to output a standard 12V voltage.
CN201711318762.6A 2017-12-12 2017-12-12 Television with multifunctional charge and discharge management system Active CN107770464B (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61177879A (en) * 1985-02-04 1986-08-09 Matsushita Electric Ind Co Ltd LCD TV receiver lighting equipment
CN201388072Y (en) * 2009-03-17 2010-01-20 天津三星电子显示器有限公司 Television with universal charging function
CN201846423U (en) * 2010-10-26 2011-05-25 康佳集团股份有限公司 LED backlight television and power source used for same
CN206559503U (en) * 2017-02-17 2017-10-13 昆山康佳电子有限公司 A kind of TV with storage battery power supply function
CN207603788U (en) * 2017-12-12 2018-07-10 铭薪电子（深圳）有限公司 The multi-functional TV for being charged and discharged management system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61177879A (en) * 1985-02-04 1986-08-09 Matsushita Electric Ind Co Ltd LCD TV receiver lighting equipment
CN201388072Y (en) * 2009-03-17 2010-01-20 天津三星电子显示器有限公司 Television with universal charging function
CN201846423U (en) * 2010-10-26 2011-05-25 康佳集团股份有限公司 LED backlight television and power source used for same
CN206559503U (en) * 2017-02-17 2017-10-13 昆山康佳电子有限公司 A kind of TV with storage battery power supply function
CN207603788U (en) * 2017-12-12 2018-07-10 铭薪电子（深圳）有限公司 The multi-functional TV for being charged and discharged management system

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