CN107729642A - Signal source board design based on OMAPL138 core boards - Google Patents

Signal source board design based on OMAPL138 core boards Download PDF

Info

Publication number
CN107729642A
CN107729642A CN201710940070.9A CN201710940070A CN107729642A CN 107729642 A CN107729642 A CN 107729642A CN 201710940070 A CN201710940070 A CN 201710940070A CN 107729642 A CN107729642 A CN 107729642A
Authority
CN
China
Prior art keywords
module
signal source
source board
fpga
dsp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710940070.9A
Other languages
Chinese (zh)
Inventor
王立群
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Haiying Enterprise Group Co Ltd
Original Assignee
Haiying Enterprise Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Haiying Enterprise Group Co Ltd filed Critical Haiying Enterprise Group Co Ltd
Priority to CN201710940070.9A priority Critical patent/CN107729642A/en
Publication of CN107729642A publication Critical patent/CN107729642A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level

Abstract

The present invention relates to the design field of signal source board.In the embodiment of the present invention, signal source board includes, core board module, receives the order that host computer is sent by serial ports and network interface, and order is parsed, and the control to FPGA module, AD/DA modules, power clock module is realized by different functional requirements;FPGA module, communicated by EMIFA buses with DSP, receive the order that DSP is sent, and the signal according to corresponding to described order generation;A/D module in AD/DA modules can carry out AD samplings to 4 road signals, and the D/A module in AD/DA modules can carry out DA samplings to 4 road signals;Interface driver module is used to be isolated output drive signal caused by FPGA with late-class circuit, and carries out 3.3V~5V level conversion;Power clock module, for other module for power supply for signal source board, and provide the external clock of dsp chip, fpga chip.The present invention can save the substantial amounts of time, reduce the design difficulty of bottom plate.

Description

Signal source board design based on OMAPL138 core boards
Technical field
The present invention relates to the design field of signal source board, especially DSP, FPGA development and application field.
Background technology
Signal source board is typically designed by the way of DSP (or single-chip microcomputer)+FPGA, to be carried out about 10 years during design Time be expected, the signal source board design time of 10 years needs to put into substantial amounts of human and material resources, but spends and so set for a long time Count achievement, it is likely that after design is completed, that is, be faced with superseded risk.
Therefore, in order to meet demand for development that current demand signal source plate quickly designs, needing development one kind badly can be rapidly completed The signal source board of design.
The content of the invention
The purpose of the present invention is overcome the deficiencies in the prior art, there is provided a kind of new signal source board, the signal source board use Designed using core board, reduce the design difficulty of signal source board.Only with consideration fpga chip on the signal source board using 6u Designed with the position of power supply chip etc. and cabling, PCB design can be completed with 6 laminates;Secondly, the software of signal source board is accelerated Desin speed.
In order to solve the above-mentioned technical problem, the invention provides following technical scheme:
The embodiment of the present invention provides a kind of signal source board, and the signal source board includes, core board module, FPGA module, electricity Source clock module, AD/DA modules and interface driver module;
Wherein, the core board module, it is the Master Control Center of signal source board, receives host computer and sent by serial ports and network interface Order, and order is parsed, realized by different functional requirement to FPGA module, AD/DA modules, power clock module Control;The FPGA modules, communicated by EMIFA buses with DSP, receive the order that DSP is sent, and according to described Order generation corresponding to signal;A/D module in the AD/DA modules can carry out AD samplings to 4 road signals, in AD/DA modules D/A module can carry out DA samplings to 4 road signals;Power clock module, for other module for power supply for signal source board, and carry For dsp chip, the external clock of fpga chip.
Preferably, the processor in the core board, is integrated with 300MHz kernel and 300MHz DSP core;Core board Whole Peripheral Interfaces by DIMM Interface Expandings, MMC/SDIO, SATA, UART, USB HOST, USB OTG2.0,10M/ 100M Ethernets, GPIO, jtag interface.
Preferably, the power clock module is that DSP and FPGA powers, and the power supply of wherein DSP parts is by the outer of 5V Power convert is connect into interface voltage 3.3V, core voltage 1.2V, internal memory supply voltage 1.8V;The power supply of FPGA portion is to pass through 5V External power supply be converted into interface voltage 3.3V, core voltage 1.2V, operating voltage 2.5V.
Preferably, the AD sampling A/D chips in the A/D module are posted from 4/8 passage, 16, Charge scaling Approach by inchmeal Storage (SAR) type analog-to-digital converter;DA sampling A/D chips in the D/A module select 4 passages of TI companies, 12 voltage outputs Digital analog converter.
Preferably, the chip of the interface driver module selects 8 pairs with configurable voltage conversion and ternary output Power bus transceiver, the level conversion function between 3.3V and 5V can be achieved.
The present invention uses core board modelled signal source plate.First, DSP chips and its external interface are included on core board, But because the appearance and size of core board is only about 67mm × 44mm, it need to be interconnected by the bottom plate of DIMM-200 interfaces and 6U. So in the carry out hardware circuit design of signal source board, the substantial amounts of time can be saved, reduces the design difficulty of bottom plate;Its Secondary, the software platform basic building of general core board is good, reduces the difficulty of signal source board Software for Design, the cycle of software development Also shorten.3rd, reduce the cost of signal source board.In addition, the peripheral interface aboundresources of core board, can also be carried out multi-party The Redundancy Design in face.Because signal source board is powerful, signal acquisition, signal transacting etc. are also applied to, it is portable strong.
Brief description of the drawings
Technical scheme in order to illustrate the embodiments of the present invention more clearly, make required in being described below to embodiment Accompanying drawing is briefly introduced, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this For the those of ordinary skill in field, without having to pay creative labor, it can also be obtained according to these accompanying drawings His accompanying drawing.
Fig. 1 is the system design block diagram of signal source board of the present invention.
Embodiment
In order that the object, technical solutions and advantages of the present invention are clearer, the present invention is made below in conjunction with accompanying drawing into One step it is described in detail, it is clear that the described embodiment only a part of embodiment of the present invention, rather than whole implementation Example.Based on the embodiment in the present invention, what those of ordinary skill in the art were obtained under the premise of creative work is not made All other embodiment, belongs to the scope of protection of the invention.
The invention will be further described below in conjunction with the accompanying drawings.
Fig. 1 is the system design block diagram of signal source board.OMAPL138 core boards are as signal source board Master Control Center, in reception The order that position machine is sent by serial ports and network interface, and being parsed to order, by different functional requirements realize to FPGA, AD, The control of the functional modules such as DA.Signal source board be broadly divided into OMAPL138 core board modules, FPGA module, power clock module, AD/DA modules, communication module and interface driver module etc..FPGA module is used for the formation of various concrete signals;Power clock mould Block is used for the power supply of the devices such as dsp chip, fpga chip and provides dsp chip, the external clock of fpga chip;Communication module is used Communicated between signal source board and host computer;A/D module can carry out AD samplings to 4 road signals in AD/DA modules, and D/A module can be to 4 Road signal carries out DA samplings;Interface driver module is used to be isolated output drive signal caused by FPGA with late-class circuit, And carry out 3.3V~5V level conversion.
Wherein, OMAPL138 core board modules are integrated with 300MHz ARM926EJ-S kernels and 300MHz C6748VLIW DSP core, and abundant Peripheral Interface is provided:
CPU:300MHz ARM926EJ-S+300MHz C6748VLIW DSP
Memory:DDR 64MB;NAND 512MB
Peripheral Interface:Onboard ethernet PHY, RTC real-time clocks, power supply and reset system
Expansion bus:Whole Peripheral Interfaces by DIMM Interface Expandings, MMC/SDIO, SATA, UART, USB HOST, USB OTG2.0,10M/100M Ethernets, GPIO, jtag interface
DIMM-200 interfaces, lock hole design, high-strength mechanical connection
Core board is connected with bottom plate by DIMM-200 interfaces.
Wherein, the chip in FPGA module selected the extensive of the series of Stratix II of altera corp, high density, The PLD EP2S30F484 of high bandwidth.Its main performance is shown in Table 1.
The performance table of the series of table 1Stratix II
FPGA is communicated by EMIFA buses with DSP.DSP sends order to FPGA, is realized by FPGA specific Function, the simple signal of specific frequency is for example produced, the linear positive and negative FM signal in specific bandwidth, the pulse of specific width Signal etc..FPGA is programmed and configured in the PLDs of the Quartus II exploitation software that altera corp releases, Downloaded to by USB-Blaster download cables with JTAG mode in supporting Flashrom (EPCS16).
Wherein, power clock module is broadly divided into the power supply of DSP parts and the power supply of FPGA portion.Chip has selected TI public The power conversion chip TPS65053RGE of department.
The power supply of DSP parts is to be converted into interface voltage 3.3V, core voltage 1.2V, internal memory by 5V external power supply Supply voltage 1.8V.
The power supply of FPGA portion is to be converted into interface voltage 3.3V, core voltage 1.2V by 5V external power supply, work Voltage 2.5V.
Wherein, signal source board communicates with host computer two ways:Serial communication and network interface communication.
A) serial communication
Signal source board is communicated with host computer using the RS-422 serial ports of high speed full duplex.Serial port chip selects Maxim The MAX488E of company.
B) network interface communicates
Network interface communication uses Ethernet (TCP/IP and UDP/IP 100,000,000 fidonetFidos).Network interface hardware selects RJ45.
AD/DA modules therein, including AD sampling modules and DA sampling modules.
AD sampling A/D chips select 4/8 passage, 16, Charge scaling successive approximation register (SAR) pattern of TI companies Number converter AD7689.AD7689 realizes the write-in of configuration register and the reception of transformation result using simple SPI interfaces. Differential Input or bipolarity input can be used.Signal source board input signal is ± 5V single-ended signal.Input signal AD_INx is passed through Enter AD7689 after ADA4841 drivings, signal SPI1_CS, SPI1_CLK, SPI1_MISO and SPI1_MOSI are sent in DSP Sampled under control.Position U38 is the output reference level that 2.5V is provided for AD7689.
DA sampling A/D chips select 4 passages, the 12 voltage output digital analog converter DAC7725 of TI companies.In DSP control Data EMA_D [0..11] is changed under system, forms 4 tunnels output DAC_OUT1~DAC_OUT4.
Wherein, the chip of interface driver module has selected the 8 with configurable voltage conversion and ternary output of TI companies Position dual power supply bus transceiver SN74LVC8T245.The level conversion function between 3.3V and 5V can be achieved.
Although preferred embodiments of the present invention have been described, but those skilled in the art once know basic creation Property concept, then can make other change and modification to these embodiments.So appended claims be intended to be construed to include it is excellent Select embodiment and fall into having altered and changing for the scope of the invention.
Obviously, those skilled in the art can carry out the essence of various changes and modification without departing from the present invention to the present invention God and scope.So, if these modifications and variations of the present invention belong to the scope of the claims in the present invention and its equivalent technologies Within, then the present invention is also intended to comprising including these changes and modification.

Claims (5)

  1. A kind of 1. signal source board, it is characterised in that:
    The signal source board includes, and core board module, FPGA module, power clock module, AD/DA modules, communication module and connects Mouth drive module;
    Wherein, the core board module, it is the Master Control Center of signal source board, receives the life that host computer is sent by serial ports and network interface Order, and order is parsed, realize the control to FPGA module, AD/DA modules, power clock module by different functional requirements System;
    The FPGA module, communicated by EMIFA buses with DSP, receive the order that DSP is sent, and according to described life Signal corresponding to order generation;
    A/D module in the AD/DA modules can carry out AD samplings to 4 road signals, and the D/A module in AD/DA modules can be believed 4 roads Number carry out DA samplings;
    Interface driver module is used to be isolated output drive signal caused by FPGA with late-class circuit, and carries out 3.3V~5V Level conversion;
    Described communication module is used to communicate between signal source board and host computer;
    Power clock module, for other module for power supply for signal source board, and when providing the outside of dsp chip, fpga chip Clock.
  2. 2. signal source board according to claim 1, it is characterised in that:
    Processor in described core board, it is integrated with 300MHz kernel and 300MHz DSP core;Core board is connect by DIMM Mouth extends whole Peripheral Interfaces, MMC/SDIO, SATA, UART, USB HOST, USB OTG2.0,10M/100M Ethernet, GPIO, jtag interface.
  3. 3. signal source board according to claim 2, it is characterised in that:
    The power clock module is that DSP and FPGA powers, and the power supply of wherein DSP parts is converted into by 5V external power supply Interface voltage 3.3V, core voltage 1.2V, internal memory supply voltage 1.8V;
    The power supply of FPGA portion is to be converted into interface voltage 3.3V, core voltage 1.2V, operating voltage by 5V external power supply 2.5V。
  4. 4. signal source board according to claim 3, it is characterised in that:
    AD sampling A/D chips in the A/D module are from 4/8 passage, 16, Charge scaling successive approximation register(SAR)Type Analog-digital converter;
    DA sampling A/D chips in the D/A module select 4 passages, the 12 voltage output digital analog converters of TI companies.
  5. 5. signal source board according to claim 4, it is characterised in that:
    The chip of the interface driver module selects 8 dual power supply buses transmitting-receiving with configurable voltage conversion and ternary output Device, the level conversion function between 3.3V and 5V can be achieved.
CN201710940070.9A 2017-10-11 2017-10-11 Signal source board design based on OMAPL138 core boards Pending CN107729642A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710940070.9A CN107729642A (en) 2017-10-11 2017-10-11 Signal source board design based on OMAPL138 core boards

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710940070.9A CN107729642A (en) 2017-10-11 2017-10-11 Signal source board design based on OMAPL138 core boards

Publications (1)

Publication Number Publication Date
CN107729642A true CN107729642A (en) 2018-02-23

Family

ID=61210198

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710940070.9A Pending CN107729642A (en) 2017-10-11 2017-10-11 Signal source board design based on OMAPL138 core boards

Country Status (1)

Country Link
CN (1) CN107729642A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108923778A (en) * 2018-06-22 2018-11-30 比飞力(深圳)科技有限公司 A kind of logic level converting circuit and integrated circuit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102175917A (en) * 2011-01-19 2011-09-07 西安交通大学 Online nonlinear spectrum analysis and fault diagnosis instrument
CN103901293A (en) * 2013-12-05 2014-07-02 国家电网公司 Power quality monitoring device based on intelligent substation
CN105181117A (en) * 2015-09-10 2015-12-23 西安翔迅科技有限责任公司 Program control charge type vibration sensor simulation signal source
CN204945697U (en) * 2015-07-17 2016-01-06 应叶丰 A kind of river course intelligence Bottle & Can gripping device system
CN205123923U (en) * 2015-11-20 2016-03-30 杭州电子科技大学 Many information fusion's old man monitor system equipment

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102175917A (en) * 2011-01-19 2011-09-07 西安交通大学 Online nonlinear spectrum analysis and fault diagnosis instrument
CN103901293A (en) * 2013-12-05 2014-07-02 国家电网公司 Power quality monitoring device based on intelligent substation
CN204945697U (en) * 2015-07-17 2016-01-06 应叶丰 A kind of river course intelligence Bottle & Can gripping device system
CN105181117A (en) * 2015-09-10 2015-12-23 西安翔迅科技有限责任公司 Program control charge type vibration sensor simulation signal source
CN205123923U (en) * 2015-11-20 2016-03-30 杭州电子科技大学 Many information fusion's old man monitor system equipment

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
刘威: "基于OMAP_L138处理器的轨道信号处理平台的设计与实现", 《中国优秀硕士学位论文全文数据库 工程科技Ⅱ辑》 *
左旭辉: "基于双核OMAPL138和FPGA的嵌入式数控系统研究与开发", 《中国优秀硕士学位论文全文数据库 工程科技I辑》 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108923778A (en) * 2018-06-22 2018-11-30 比飞力(深圳)科技有限公司 A kind of logic level converting circuit and integrated circuit

Similar Documents

Publication Publication Date Title
CN103885919B (en) A kind of many DSP and FPGA parallel processing system (PPS)s and implementation method
CN104865457B (en) A kind of general detection board
CN103023505B (en) A kind of analog to digital converter of configurable with multi-channel successive approximation structure
CN105468568B (en) Efficient coarseness restructurable computing system
CN107066200A (en) A kind of collecting method and data collecting system based on FPGA
CN106487372A (en) Device including one-wire interface and the data handling system with the device
CN105118441A (en) LED display screen control card for asynchronous control system
CN205318373U (en) Wireless real -time signal handles integrated circuit board based on VPX structure
CN107729642A (en) Signal source board design based on OMAPL138 core boards
CN206920978U (en) A kind of high-speed type Signal transacting board analysis
CN201774507U (en) Multipath digital pulse generator
CN201018471Y (en) Phase-lock loop all-channel multimode frequency divider
CN203167288U (en) Internet of Things gateway development platform facing heterogeneous network environments
CN103984263B (en) A kind of compatible ISA, the general dsp module of pci bus interface and collocation method
CN107704407A (en) A kind of system and method for being used for data processing between SPI and UART
CN201918981U (en) Dual-phase harvard code bus signal coding-decoding circuit
CN104915313A (en) FMC board card for realizing level transformation by using FPGA (field programmable gate array)
CN111274187A (en) 1553B and serial port communication module based on FPGA
CN206757603U (en) 8 tunnel full duplex RS232 serial ports expansion modules
CN206835066U (en) Short-wave signal intermediate frequency acquisition process recovery card
CN201184970Y (en) Embedded board for acquiring data of watercraft engine compartment
CN101286181A (en) On site programmable gate array on-chip programmable system based on DW8051 core
CN203217298U (en) Parallel data port AD sampling system based on DSP
CN201111724Y (en) Built-in priority signal controller for facing quick public transport system
CN108304339A (en) A kind of serial expanded circuit and its working method of dynamic managing and control system

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination