CN107728707A - A kind of method that Vectoring VDSL2 business is realized in VDSL2 systems - Google Patents

A kind of method that Vectoring VDSL2 business is realized in VDSL2 systems Download PDF

Info

Publication number
CN107728707A
CN107728707A CN201710888620.7A CN201710888620A CN107728707A CN 107728707 A CN107728707 A CN 107728707A CN 201710888620 A CN201710888620 A CN 201710888620A CN 107728707 A CN107728707 A CN 107728707A
Authority
CN
China
Prior art keywords
clock
kiosk
circuit
dsp module
disk
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710888620.7A
Other languages
Chinese (zh)
Other versions
CN107728707B (en
Inventor
王瑞波
张前进
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fiberhome Telecommunication Technologies Co Ltd
Original Assignee
Fiberhome Telecommunication Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fiberhome Telecommunication Technologies Co Ltd filed Critical Fiberhome Telecommunication Technologies Co Ltd
Priority to CN201710888620.7A priority Critical patent/CN107728707B/en
Publication of CN107728707A publication Critical patent/CN107728707A/en
Application granted granted Critical
Publication of CN107728707B publication Critical patent/CN107728707B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators

Abstract

The invention discloses a kind of method that Vectoring VDSL2 business is realized in VDSL2 systems, including：Respectively every piece of VD32 kiosk disk is equipped with clock circuit and clock control circuit, and VD32 kiosk disks number is one piece or two pieces；One DSP module is arranged to vectoring processors, the DSP module receives control signal by the clock control circuit of same kiosk disk to the clock control circuit tranmitting data register of different business machine disk, controls corresponding clock circuit to receive clock signal；And send control signal to the clock circuit tranmitting data register of same kiosk disk；Vectoring processors receive the clock signal to other DSP module tranmitting data register signals, other DSP modules by the clock circuit of this kiosk disk by the clock circuit on this kiosk disk, realize that all DSP module clocks in system are synchronous.The present invention reduces by one piece of central vector calculus disk, reduces the manufacturing cost and overall power of VDSL2 systems, reduces energy waste, realizes that green energy conservation communicates.

Description

A kind of method that Vectoring VDSL2 business is realized in VDSL2 systems
Technical field
The present invention relates to the VDSL fields with vector calculus, and in particular to one kind is realized in VDSL2 systems Vectoring VDSL2 operational approaches.
Background technology
In recent years, with the propulsion of broadband speed acceleration project, many cells have carried out the transformation of light entering and copper back, but pass through practice It has been found that many copper cables access old cell, due to property coordinate and user be reluctant change house ornamentation the problems such as, cause The difficult point and more than 75% cost entirely transformed all are registered one's residence section in optical cable；According to statistics, the cell that so uncomfortable closing light changes accounts for changing More than the 50% of cell total amount is made, and in domestic copper cable existing network storage, the 82.6% copper cable time limit≤20 year, wherein, 70% copper cable Length≤1000 meter, use state and environment are good, therefore utilize original copper networks, are realized using the copper wire technology of innovation old Old partial wideband speed-raising, it is clear that have more advantage than laying optical cable again.VDSL2 is effective to family by the hybrid fiber of high performance-price ratio Ground solves above-mentioned last mile of problem, and up to now, VDSL2 existing network commercializations have broken through million lines, covering China Telecom, 20 multiple provinces of CHINAUNICOM and northern Tie Tong, wherein province more than newly-built 100,000 line alreadys exceed ten.
Enhanced Technologies of the Vectoring as VDSL2, can be with by way of crosstalk is offset in the superposition of vector matrix Realize that 100M is accessed in 500 meters, 150M accesses supported in 300 meters, meet household person broadband access long term object, not only with FTTH bandwidth ability is equal to, and compared with FTTH construction mode, Vectoring VDSL2, which register one's residence, need not transform cable, Engineering is simple, business is laid soon, and most of VDSL terminals laid in the recent period are only needed to carry out software upgrading, does not increase hardware Cost, there is absolute cost advantage.
Both traditional 32 road VDSL2 business had been supported, have supported distal end ONU equipment (such as the beacon of Vectoring VDSL2 business again The AN5006-20 card insert type MDU of fire) 4 pieces of VD32 kiosk disks can be supported, each piece of VD32 kiosk disk includes 2 DSP cores Piece, each dsp chip can provide the VDSL signal access capabilities that 16 tunnels meet 17A templates, wherein, dsp chip is as every The core devices of block machine disk, it is main to complete encoding and decoding algorithm and vectoring algorithm process, and in order to open 4 pieces of VD32 business The vectoring VDSL business of machine disk, it is also necessary to one piece of central vector calculus is installed above the main control unit of distal end ONU equipment Disk, the Vector operation of 4 pieces of road vectoring VDSL business of VD32 kiosk Pan 128 is handled, so the central vector calculus Disk needs are powerful, and corresponding power consumption is also higher.
In most of engineer applied scene, a said distal ends ONU equipment can only assemble 2 pieces or 1 piece of VD32 business Machine disk, but in order to open vectoring VDSL business, still have to configure one piece of central vector calculus disk, in this case, The increase of equipment cost and power consumption will be caused, it is contemplated that, it is necessary to open vectoring VDSL industry in Practical Project at this stage Business, and the equipment application quantity that can only assemble 2 pieces or 1 piece VD32 kiosk disks is more, will bring larger energy waste, with The energy-saving and emission-reduction policy that country advocates is disagreed, and is not inconsistent with the target for energy-saving and emission-reduction of three big telecom operators
The content of the invention
The technical problems to be solved by the invention are to support traditional 32 road VDSL2 business and Vectoring at the same time In the VDSL2 equipment of VDSL2 business, in the case of only 2 pieces or 1 piece of VD32 kiosk disk is assembled, to open Vectoring VDSL business, it is also necessary to configure one piece of central vector calculus disk processing organic disk vectoring VDSL industry The problem of Vector operation of business.
In order to solve the above-mentioned technical problem, it is real in VDSL2 systems to be to provide one kind for the technical solution adopted in the present invention The method of existing Vectoring VDSL2 business, comprises the following steps：
Respectively every piece of VD32 kiosk disk is equipped with clock circuit and clock control circuit, and VD32 kiosk disks number is one Block or two pieces；
First DSP module in an above VD32 kiosk disk is arranged to vectoring processors, the DSP moulds Clock control circuit tranmitting data register of the block by the clock control circuits of place VD32 kiosk disks to different VD32 kiosk disks Control signal is received, controls corresponding clock circuit to receive clock signal；And to same D32 kiosk disk clock circuit send when Clock sends control signal；
The DSP module for being set as vectoring processors is same to being sent with the DSP module on a VD32 kiosk disk Step clock signal, and sent by the DSP module of the clock circuit of this kiosk disk into system on other VD32 kiosk disks Synchronizing clock signals, the clock circuit that the DSP module on other VD32 kiosk disks passes through on the VD32 kiosk disks of place receive The synchronizing clock signals, realize that all DSP module clocks in system are synchronous.
In the above-mentioned methods, the logic control circuit of the clock circuit is made up of the first gate and the second gate；
The input of first gate is single ended clock transmitting terminal, enables control terminal to send enabled control terminal；Institute The output end for stating the second gate is single ended clock receiving terminal, enables control terminal to receive enabled control terminal；
First output end of first gate is connected with the second input of the second gate, output or input first Electric signal；3rd output end of first gate is connected with the 4th input of the second gate, output or input second Electric signal；First electric signal and the second electric signal form clock signal；
3rd output end is anti-phase output, and the 4th input is anti-phase input.
In the above-mentioned methods, the logic control of the clock circuit is specially：
Direction is received in clock signal：
When it is low level to receive enabled control terminal, input clock signal is low level, and the output of single ended clock receiving terminal is low Level；When it is low level to receive enabled control terminal, input clock signal is high level, and the output of single ended clock receiving terminal is high electric It is flat；When it is high level to receive enabled control terminal, clock circuit sends state and closed, and single ended clock receiving terminal is in high resistant all the time State；Wherein, the input clock signal is that to subtract the 4th input defeated for the first electric signal of second input input The second electric signal entered；
In clock signal sending direction：
When it is high level to send enabled control terminal, single ended clock transmitting terminal input low level, the first output end exports low Level, the 3rd output end output high level；When it is high level to send enabled control terminal, the high electricity of single ended clock transmitting terminal input It is flat, the first output end output high level, the 3rd output end output low level；When it is low level to send enabled control terminal, clock Circuit reception state is closed, and the first output end and the 3rd output end are in high-impedance state all the time.
In the above-mentioned methods, the acp chip of the clock circuit uses SN65MLVD205ADR clock chips.
In the above-mentioned methods, VD32 kiosk disk number is two pieces in VDSL2 systems, respectively the first VD32 kiosk Disk and the 2nd VD32 kiosk disks；Wherein,
When the first VD32 kiosk disk is including the first DSP module, the 3rd DSP module, the first clock circuit and first Clock control circuit；
When the 2nd VD32 kiosk disk is including the second DSP module, the 4th DSP module, second clock circuit and second Clock control circuit；
First DSP module is to be in first DSP module of the first VD32 kiosk disks above,
First DSP module sends synchronizing clock signals to the DSP module of prime number the 3rd；First clock control circuit Control first clock circuit to be sent to the synchronised clock passage of backboard to open, close receiving channel, and control to second clock Circuit, which is sent, receives control signal；The second clock control circuit controls the second clock circuit according to control signal is received Backplane Sync clock receiving channel open, close sendaisle；First DSP module is sent to the back of the body by the first clock circuit The synchronised clock passage of plate sends synchronizing clock signals, and second DSP module and the 4th DSP module pass through the second clock The backplane Sync clock receiving channel of circuit receives the synchronizing clock signals.
In the above-mentioned methods, in the case where not enabling Vectoring VDSL2 business, first, second clock control electricity Road acquiescence closes first, second clock circuit, and reception is enabled and is arranged to high level, and transmission is enabled to be arranged to low level, when Clock signal output, input end are in high-impedance state.
In the above-mentioned methods, in the case where enabling Vectoring VDSL2 service conditions, all DSP module clocks in system Synchronously specifically include following steps：
When select the first DSP module for vectoring processors when,
Step S10, the first clock control circuit, which enables the transmission of the first clock circuit, is arranged to high, the hair of clock circuit Send state to open, receive direction and keep high-impedance state；
Step S20, the first clock control circuit sends what control second clock circuit received to second clock control circuit Clock receives control signal；
Step S30, second clock control circuit receives control signal according to clock and closes the transmission state of clock circuit, Open reception state；
Step S40, the first DSP module directly sends synchronizing clock signals to the first DSP module, passes through the first clock circuit Synchronizing clock signals are sent to the second DSP module and the 4th DSP module；
Step S50, second clock circuit receives clock signal by backboard；
Step S60, the clock signal received is sent to the second, the 4th DSP module by second clock circuit, is realized between disk Clock is synchronous；
When the 2nd VD32 kiosk disk is an above kiosk disk, the 2nd first conduct of VD32 kiosk disk is selected Vectoring processors, processing mode are identical with above-mentioned principle.
The present invention is by the case where only assembling the application scenarios of 1 piece or 2 pieces VD32 kiosk disk, selecting one of DSP cores Piece completes the vectoring computings of whole system, reduces by one piece of central vector calculus disk, and by being respectively every piece of VD32 business Machine disk is equipped with clock circuit and clock control circuit, realizes the transmission of clock signal and the change of direction of transfer between machine disk, complete It is synchronous into the clock between machine disk, the final complete vector quantization VDSL functions of realizing plate level, reduce entirely while support tradition 32 The manufacturing cost of the VDSL2 systems (such as AN5006-20 systems) of road VDSL2 business and support Vectoring VDSL2 business And overall power, energy waste is reduced, realizes that green energy conservation communicates.
Brief description of the drawings
Fig. 1 provides a kind of method that Vectoring VDSL2 business is realized in VDSL2 systems for the present invention and works as VD32 industry Structural representation is realized when business machine disk number is two pieces；
Fig. 2 is that a kind of method that Vectoring VDSL2 business is realized in VDSL2 systems provided by the invention works as VD32 Flow chart when kiosk disk number is two pieces；
Fig. 3 is the logic control circuit schematic diagram of clock circuit in the present invention.
Embodiment
In the VDSL2 systems for supporting traditional 32 road VDSL2 business and support Vectoring VDSL2 business at the same time, by In two dsp chips that every piece of VD32 kiosk disk includes, the vectoring processors in each dsp chip can be same The vectoring calculation process of the road VDSL2 business of Shi Jinhang 64, so only assembling the application of 1 piece or 2 pieces VD32 kiosk disk Under scene, as long as one dsp chip can of selection completes the vectoring computings of whole system, save central vector calculus Disk, reach the purpose of energy-conservation reducing power consumption.
In order to realize such scheme, therefore, to assure that the clock of 4 dsp chips of two pieces of VD32 kiosk disks is synchronous, that is, works as When selecting a dsp chip in one of VD32 kiosk disk as vectoring processors, dsp chip needs pair Outer output clock signal, remaining three dsp chips receive the synchronizing clock signals；When another VD32 kiosk disk of selection During as vectoring processors, clock signal direction of transfer is opposite.
The present invention is described in detail with reference to Figure of description and specific embodiment.
A kind of method that Vectoring VDSL2 business is realized in VDSL2 systems provided by the invention, it is specific as follows：
In the VDSL2 systems that VD32 kiosk disks number is one piece or two pieces, respectively every piece of VD32 kiosk disk is matched somebody with somebody Standby clock circuit and clock control circuit, to realize the transmission of clock signal and the change of direction of transfer between machine disk；
First DSP module (dsp chip) in an above VD32 kiosk disk is arranged to by user as needed Vectoring processors；The DSP module is by the clock control circuits of place VD32 kiosk disks to different VD32 kiosk disks Clock control circuit tranmitting data register receive control signal, control corresponding clock circuit (different from vectoring processors On VD32 kiosk disks) receive clock signal；And send control letter to the clock circuit tranmitting data register of same D32 kiosk disk Number；
The DSP module for being arranged to vectoring processors is sent to the DSP module on a VD32 kiosk disk Synchronizing clock signals, by the clock circuit on VD32 kiosk disks where it into system on other VD32 kiosk disks DSP module sends synchronizing clock signals, the DSP module on other VD32 kiosk disks by the VD32 kiosk disks of place when Clock circuit receives the synchronizing clock signals, realizes that all DSP module clocks in system are synchronous.
Below using the VDSL2 systems with two pieces of VD32 kiosk disks as specific embodiment, implementation process of the present invention is entered Row describes in detail, as shown in figure 1, the present embodiment includes the first VD32 kiosk disk 10 and the 2nd VD32 kiosk disk 20, its In, the first VD32 kiosk disk 10 includes the first DSP module 11, the 3rd DSP module 12, the first clock circuit 13 and the first clock Control circuit 14；2nd VD32 kiosk disk 20 includes the second DSP module 21, the 4th DSP module 22, the and of second clock circuit 23 Second clock control circuit 24；For the VDSL2 systems of two pieces of VD32 kiosk disks, above kiosk disk can only be selected First DSP module is as clock source；Second DSP of each VD32 machine disks cannot function as clock source.
First DSP module of first DSP module 11 as an above VD32 kiosk disk 10 of kiosk disk the first, the One DSP module 11 directly sends synchronizing clock signals to the 3rd DSP module 12；First clock control circuit 14 controls the first clock The synchronised clock passage that circuit 13 is sent to backboard is opened, and closes receiving channel, and send accordingly to second clock control circuit 24 Control information；Second clock control circuit 24 controls the backplane Sync clock of second clock circuit 23 to connect according to corresponding control information Receive passage to open, sendaisle is closed, to realize the VD32 industry of second clock circuit 23 and the first of the 2nd VD32 kiosk disk 20 Business machine disk 10 keeps clock signal synchronization；The synchronised clock that first DSP module 11 is sent to backboard by the first clock circuit 13 leads to Road is sent out synchronizing clock signals；Second DSP module 21 and the 4th DSP module 22 are same by the backboard of second clock circuit 23 Walk clock receiving channel and receive the synchronizing clock signals that the first DSP module 11 is sent.
(1) in the case where not enabling Vectoring VDSL2 business, clock is not needed to pass between VD32 kiosk disks Pass, now first, second clock control circuit acquiescence closes first, second clock circuit, and reception is enabled and is arranged to high electricity Flat, transmission is enabled to be arranged to low level, and now differential clocks output is in high-impedance state.
(2) it is vectoring processing when selecting the first DSP module in the case where enabling Vectoring VDSL2 business During device, as shown in Fig. 2 realizing that all DSP module clocks in system synchronously specifically include following steps：
Step S10, the transmission of the first clock circuit is enabled and set by the first clock control circuit of the first VD32 kiosk disks Height is set to, the transmission state of clock circuit is opened, and is received direction and is kept high-impedance state.
Step S20, the first clock control circuit sends what control second clock circuit received to second clock control circuit Clock receives control signal.
Step S30, second clock control circuit receives control signal according to clock and closes the transmission state of clock circuit, Open reception state.
Step S40, the first DSP module of the first VD32 kiosk disks directly sends synchronised clock letter to the first DSP module Number, synchronizing clock signals are sent to other DSP modules (the second DSP module and the 4th DSP module) by the first clock circuit.
Step S50, the second clock circuit of the 2nd VD32 kiosk disks receives opposite end (the first clock circuit) by backboard The clock signal of hair.
Step S60, the clock signal received is sent to the second, the 4th DSP module by second clock circuit, is realized between disk Clock is synchronous.
When the 2nd VD32 kiosk disk is an above kiosk disk, the 2nd first conduct of VD32 kiosk disk is selected Vectoring processors, processing mode is identical with above-mentioned principle, will not be repeated here.
As shown in figure 3, being the logic control circuit schematic diagram of clock circuit in the present invention, the logic control of clock circuit is electric The first gate S1 and the second gate S2 compositions are route, the first gate S1 input is single ended clock transmitting terminal D, is enabled Control terminal is high level when sending enabled control terminal DE, clock circuit opens transmission state to send enabled control terminal DE；Second Gate S2 output end is single ended clock receiving terminal R, enables control terminal to receive enabled control terminalControl is enabled when receiving EndFor low level, clock circuit opens reception state；First gate S1 the first output end Y's and the second gate S2 Second input A connections, the first electric signal of output or input；First gate S1 the 3rd output end Z and the second gate S2 The 4th input B connections, the second electric signal of output or input, the first electric signal and the second electric signal form LVDS differential clocks Signal (clock signal), the 3rd output end Z are anti-phase output, and the 4th input B is anti-phase input.
The specific logic control of clock circuit is (as shown in the logic control explanation of the clock circuit of table 1)：
Direction is received in clock signal：
Control terminal is enabled when receivingFor low level when, input clock signal VIDFirst electricity of the=the second input A inputs Signal VASecond electric signal V of the-the four input B inputsBFor low level, single ended clock receiving terminal R output low levels；Work as reception Enabled control terminalFor low level when, input clock signal VIDFor high level, single ended clock receiving terminal R output high level；When connecing Receive enabled control terminalFor high level when, clock circuit send state close, input clock signal VIDNo matter input high level or Low level, high-impedance state is all in all the time without processing, single ended clock receiving terminal R.
In clock signal sending direction：
When it is high level to send enabled control terminal DE, single ended clock transmitting terminal D input low levels, the first output end Y is defeated Go out low level, the 3rd output end Z output high level；When it is high level to send enabled control terminal DE, single ended clock transmitting terminal D is defeated Enter high level, the first output end Y output high level, the 3rd output end Z output low levels；It is low electricity when sending enabled control terminal DE Usually, clock circuit reception state close, single ended clock transmitting terminal D no matter input high level or low level, all without processing, First output end Y and the 3rd output end Z are in high-impedance state all the time.
Table 1：The logic control explanation of clock circuit.
Wherein, X represents not handle input signal, whenFor high level, when DE is low level, single ended clock receiving terminal R, the first output end Y and the 3rd output end Z is in high-impedance state, and the first clock circuit and second clock circuit are closed mode, Vectoring VDSL2 business is not open-minded.
In the present invention, the acp chip of clock circuit uses SN65MLVD205ADR clock chips, and the chip can be real The now isolation shut-off of clock signal, control clock signal sending direction change and realized turn of single ended clock and differential clocks Change.
Obviously, those skilled in the art can carry out the essence of various changes and modification without departing from the present invention to the present invention God and scope.So, if these modifications and variations of the present invention belong to the scope of the claims in the present invention and its equivalent technologies Within, then the present invention is also intended to comprising including these changes and modification.

Claims (7)

  1. A kind of 1. method that Vectoring VDSL2 business is realized in VDSL2 systems, it is characterised in that comprise the following steps：
    Respectively every piece of VD32 kiosk disk is equipped with clock circuit and clock control circuit, VD32 kiosk disks number be one piece or Two pieces；
    First DSP module in an above VD32 kiosk disk is arranged to vectoring processors, the DSP module is led to The clock control circuit of VD32 kiosk disks where crossing receives to the clock control circuit tranmitting data register of different VD32 kiosk disks Control signal, corresponding clock circuit is controlled to receive clock signal；And sent out to the clock circuit tranmitting data register of same D32 kiosk disk Send control signal；
    The DSP module of vectoring processors is set as to when the DSP module on a VD32 kiosk disk sends synchronous Clock signal, and sent by the DSP module of the clock circuit of this kiosk disk into system on other VD32 kiosk disks synchronous Clock signal, it is same that DSP module on other VD32 kiosk disks by the clock circuit on the VD32 kiosk disks of place receives this Step clock signal, realize that all DSP module clocks in system are synchronous.
  2. 2. the method as described in claim 1, it is characterised in that the logic control circuit of the clock circuit is by the first gate Formed with the second gate；
    The input of first gate is single ended clock transmitting terminal, enables control terminal to send enabled control terminal；Described The output end of two gates is single ended clock receiving terminal, enables control terminal to receive enabled control terminal；
    First output end of first gate is connected with the second input of the second gate, the first telecommunications of output or input Number；3rd output end of first gate is connected with the 4th input of the second gate, the second telecommunications of output or input Number；First electric signal and the second electric signal form clock signal；
    3rd output end is anti-phase output, and the 4th input is anti-phase input.
  3. 3. method as claimed in claim 2, it is characterised in that the logic control of the clock circuit is specially：
    Direction is received in clock signal：
    When it is low level to receive enabled control terminal, input clock signal is low level, and single ended clock receiving terminal exports low level； When it is low level to receive enabled control terminal, input clock signal is high level, and single ended clock receiving terminal exports high level；When connecing When the enabled control terminal of receipts is high level, clock circuit sends state and closed, and single ended clock receiving terminal is in high-impedance state all the time；Its In, the input clock signal is that the first electric signal of second input input subtracts the of the 4th input input Two electric signals；
    In clock signal sending direction：
    When it is high level to send enabled control terminal, single ended clock transmitting terminal input low level, the first output end output low level, 3rd output end exports high level；When it is high level to send enabled control terminal, single ended clock transmitting terminal input high level, first Output end exports high level, the 3rd output end output low level；When it is low level to send enabled control terminal, clock circuit receives State is closed, and the first output end and the 3rd output end are in high-impedance state all the time.
  4. 4. method as claimed in claim 3, it is characterised in that the acp chip of the clock circuit uses SN65MLVD205ADR clock chips.
  5. 5. the method as described in claim 1, it is characterised in that VD32 kiosk disk number is two pieces in VDSL2 systems, point Wei not the first VD32 kiosk disk and the 2nd VD32 kiosk disks；Wherein,
    Clock when the first VD32 kiosk disk is including the first DSP module, the 3rd DSP module, the first clock circuit and first Circuit processed；
    The 2nd VD32 kiosk disk includes the second DSP module, the 4th DSP module, second clock circuit and second clock control Circuit processed；
    First DSP module is to be in first DSP module of the first VD32 kiosk disks above,
    First DSP module sends synchronizing clock signals to the DSP module of prime number the 3rd；The first clock control circuit control The synchronised clock passage that first clock circuit is sent to backboard is opened, and closes receiving channel, and to second clock control circuit Send and receive control signal；The second clock control circuit controls the back of the body of the second clock circuit according to control signal is received Plate synchronised clock receiving channel is opened, and closes sendaisle；First DSP module is sent to backboard by the first clock circuit Synchronised clock passage sends synchronizing clock signals, and second DSP module and the 4th DSP module pass through the second clock circuit Backplane Sync clock receiving channel receive the synchronizing clock signals.
  6. 6. method as claimed in claim 5, it is characterised in that in the case where not enabling Vectoring VDSL2 business, the First, second clock control circuit acquiescence closes first, second clock circuit, and reception is enabled and is arranged to high level, transmission makes Low level can be arranged to, clock signal output, input end are in high-impedance state.
  7. 7. method as claimed in claim 5, it is characterised in that in the case where enabling Vectoring VDSL2 service conditions, in system All DSP module clocks synchronously specifically include following steps：
    When select the first DSP module for vectoring processors when,
    Step S10, the first clock control circuit, which enables the transmission of the first clock circuit, is arranged to high, the transmission shape of clock circuit State is opened, and is received direction and is kept high-impedance state；
    Step S20, the first clock control circuit sends the clock of control second clock circuit reception to second clock control circuit Receive control signal；
    Step S30, second clock control circuit receives control signal according to clock and closes the transmission state of clock circuit, opens Reception state；
    Step S40, the first DSP module directly sends synchronizing clock signals to the first DSP module, by the first clock circuit to the Two DSP modules and the 4th DSP module send synchronizing clock signals；
    Step S50, second clock circuit receives clock signal by backboard；
    Step S60, the clock signal received is sent to the second, the 4th DSP module by second clock circuit, realizes clock between disk It is synchronous；
    When the 2nd VD32 kiosk disk is an above kiosk disk, the 2nd first conduct of VD32 kiosk disk is selected Vectoring processors, processing mode are identical with above-mentioned principle.
CN201710888620.7A 2017-09-27 2017-09-27 Method for realizing vectored VDS L2 service in VDS L2 system Active CN107728707B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710888620.7A CN107728707B (en) 2017-09-27 2017-09-27 Method for realizing vectored VDS L2 service in VDS L2 system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710888620.7A CN107728707B (en) 2017-09-27 2017-09-27 Method for realizing vectored VDS L2 service in VDS L2 system

Publications (2)

Publication Number Publication Date
CN107728707A true CN107728707A (en) 2018-02-23
CN107728707B CN107728707B (en) 2020-08-04

Family

ID=61206977

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710888620.7A Active CN107728707B (en) 2017-09-27 2017-09-27 Method for realizing vectored VDS L2 service in VDS L2 system

Country Status (1)

Country Link
CN (1) CN107728707B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103048978A (en) * 2013-01-08 2013-04-17 中国石油天然气集团公司 Underground high-speed interconnection bus
CN103218331A (en) * 2012-12-07 2013-07-24 浙江大学 Bus device and method by adopting synchronous mode switching and automatic adjustment of frame priority
US8693557B1 (en) * 2009-07-02 2014-04-08 Integrated Device Technology Inc. AC coupled clock receiver with common-mode noise rejection
CN105009465A (en) * 2013-04-12 2015-10-28 华为技术有限公司 Performing upstream symbol alignment under fext
CN105406984A (en) * 2015-10-22 2016-03-16 上海斐讯数据通信技术有限公司 System and method of realizing main/standby switching backboard clock

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8693557B1 (en) * 2009-07-02 2014-04-08 Integrated Device Technology Inc. AC coupled clock receiver with common-mode noise rejection
CN103218331A (en) * 2012-12-07 2013-07-24 浙江大学 Bus device and method by adopting synchronous mode switching and automatic adjustment of frame priority
CN103048978A (en) * 2013-01-08 2013-04-17 中国石油天然气集团公司 Underground high-speed interconnection bus
CN105009465A (en) * 2013-04-12 2015-10-28 华为技术有限公司 Performing upstream symbol alignment under fext
CN105406984A (en) * 2015-10-22 2016-03-16 上海斐讯数据通信技术有限公司 System and method of realizing main/standby switching backboard clock

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
李彩霞: ""采用双层仲裁机制的网络式仪器总线关键技术研究"", 《中国优秀硕士学位论文全文数据库信息科技辑》 *

Also Published As

Publication number Publication date
CN107728707B (en) 2020-08-04

Similar Documents

Publication Publication Date Title
CN103199617A (en) Representing method of corresponding relationship between virtual circuits and physical ports in secondary circuit graph
CN106375010B (en) A kind of fiber optic local area network CAN bus control device and networking
CN105099954A (en) Transformer substation process layer message networking-sharing port-sharing transmission system
CN107666139A (en) A kind of Control protection system for flexible direct current power transmission system
CN105610555B (en) A kind of practical system-level redundancy communication network framework
CN105162514B (en) Optical fiber ring network communication system and method
CN107167887B (en) A kind of polarity management method of wildcard fiber optic tap module
CN107728707A (en) A kind of method that Vectoring VDSL2 business is realized in VDSL2 systems
CN203554447U (en) Gigabit intelligent type optical fiber transceiver
CN103067795B (en) Multi-chassis cascading system, Cluster Central Chassis and realize the method for exchanges data
CN204615838U (en) A kind of electric power application optical communication network structure
CN204795108U (en) Integrative device of light cat with WIFI routing function expands net gape
CN103716258B (en) High-density line card, switching device, cluster system and electric signal type configuration method
CN105743580A (en) Data center internal network interconnection structure based on multiple arrayed waveguide gratings
CN101778267B (en) Video optical multiplexer, video transmission system and method for controlling video signal transmission
CN108599850A (en) Storage optical interconnection system and communication means towards multinuclear based on broadband micro-loop
CN106950670A (en) It is a kind of that there is the wildcard fiber optic tap module and pre-terminated system for overturning generic polar
CN108519763B (en) Control circuit and apparatus control method
CN205862794U (en) A kind of digital network audio frequency broadcast system
CN106301665A (en) A kind of electric power application optical communication network structure
CN103997628A (en) Method and communication structure for optimizing thermal power plant information system
CN203933842U (en) The communication structure that a kind of thermal power plant information system is optimized
CN207908956U (en) A kind of pure electric vehicle ship Distributed Control System device
CN209462412U (en) Network synthesis based on multimode optical cable controls equipment
CN104852767B (en) A kind of optical network system and transmission method towards sampled value business in substation

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant