CN107688518A - More multiplexing test circuits and Related product - Google Patents

More multiplexing test circuits and Related product Download PDF

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Publication number
CN107688518A
CN107688518A CN201710770649.5A CN201710770649A CN107688518A CN 107688518 A CN107688518 A CN 107688518A CN 201710770649 A CN201710770649 A CN 201710770649A CN 107688518 A CN107688518 A CN 107688518A
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test point
switch
circuit
resistor
change
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CN201710770649.5A
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CN107688518B (en
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李路路
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Guangdong Oppo Mobile Telecommunications Corp Ltd
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Guangdong Oppo Mobile Telecommunications Corp Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D21/00—Measuring or testing not otherwise provided for
    • G01D21/02—Measuring two or more variables by means not covered by a single other subclass
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Telephone Function (AREA)

Abstract

The disclosure provides a kind of more multiplexing test circuits and Related product, including：More multiplexing test circuits, it is characterised in that including：First test point, the second test point, the 3rd test point, the 4th test point, the 5th test point and switching switch；Wherein, the switching switch switchs for triple channel, first test point is connected with the first control mouth of the switching switch, two common ports of second test point and the 3rd test point respectively with the switching switch are connected, the 4th test point ground connection, a GPIO connection of the 5th test point and central processing unit.Technical scheme provided by the invention has the advantages of improving circuit level and reducing cost.

Description

Multi-multiplexing test circuit and related product
Technical Field
The invention relates to the technical field of communication, in particular to a multi-multiplexing test circuit and a related product.
Background
With the increase of complexity of the smart phone, hardware circuits and software designs become more complex, software downloading and various application tests need to be completed in the development and production process, automation equipment needs to be used for testing, and meanwhile, the stability of production line manufacturing process needs to be considered. The current designs are all independent designs, and the designs have not reached a better state.
Disclosure of Invention
The embodiment of the invention provides a multi-multiplexing test circuit and a related product, which can realize the combined design of the test circuit so as to achieve the advantage of better state.
In a first aspect, an embodiment of the present invention provides a multi-multiplexing test circuit, including: the test device comprises a first test point, a second test point, a third test point, a fourth test point, a fifth test point and a change-over switch; wherein,
the change-over switch is a three-channel switch, the first test point is connected with a first control port of the change-over switch 301, the second test point and the third test point are respectively connected with two common ports of the change-over switch 301, the fourth test point is grounded, the fifth test point is connected with an input output port of a central processing unit, the other GPIO of the central processing unit is connected with a second control port of the change-over switch, one channel of the change-over switch is connected with a Universal Asynchronous Receiver Transmitter (UART) interface of the central processing unit, the second channel of the change-over switch is connected with a Universal Serial Bus (USB) of the central processing unit, and the three channels of the change-over switch are connected with a reserved channel;
one GPIO of the central processing unit is synchronous with another GPIO signal;
the change-over switch is connected with a channel when the first control port is at a low level, connected with two channels when the first control port is at a high level, and connected with three channels when the second control port is at a high level.
Optionally, the multi-multiplexing test circuit further includes: the first anti-static circuit is connected with the first test point, the other end of the first anti-static circuit is connected with the first control port of the change-over switch, one end of the second anti-static circuit is connected with the second test point, the other end of the second anti-static circuit is connected with a public port of the change-over switch, one end of the third anti-static circuit is connected with the third test point, the other end of the third anti-static circuit is connected with another public port of the change-over switch, one end of the fourth anti-static circuit is connected with the fifth test point, and the other end of the fourth anti-static circuit is connected with a GPIO of the central processing unit.
Optionally, the multi-multiplexing test circuit further includes: the circuit comprises a first switch and a third resistor, wherein one end of the first switch is connected with the fifth test point, the other end of the first switch is connected with one end of the third resistor, and the other end of the third resistor is connected with one GPIO of the central processing unit.
Optionally, the multi-multiplexing test circuit further includes: the voltage dividing circuit comprises a first resistor and a second resistor, wherein one end of the first resistor is connected with the other end of the second switch, one end of the second switch is connected with a fifth test point, the other end of the first resistor is connected with one GPIO port of the central processing unit and one end of the second resistor, and the other end of the second resistor is grounded.
In a second aspect, a smart device is provided, the device comprising: a motherboard, one or more processors, memory, a transceiver, and one or more programs stored in the memory and configured to be executed by the one or more processors, the processor comprising: a modem and an application processor AP;
the main board includes: the test device comprises a first test point, a second test point, a third test point, a fourth test point, a fifth test point and a change-over switch; wherein,
the change-over switch is a three-channel switch, the first test point is connected with a first control port of the change-over switch 301, the second test point and the third test point are respectively connected with two common ports of the change-over switch 301, the fourth test point is grounded, the fifth test point is connected with an input output port GPIO of the processor, the other GPIO of the processor is connected with a second control port of the change-over switch, one channel of the change-over switch is connected with a Universal Asynchronous Receiver Transmitter (UART) interface of the processor, the two channels of the change-over switch are connected with a Universal Serial Bus (USB) of the processor, and the three channels of the change-over switch are connected with a reserved channel;
one GPIO of the processor is synchronous with another GPIO signal;
the change-over switch is connected with a channel when the first control port is at a low level, connected with two channels when the first control port is at a high level, and connected with three channels when the second control port is at a high level.
Optionally, the smart device further includes: the first anti-static circuit is connected with the first test point, the other end of the first anti-static circuit is connected with the first control port of the change-over switch, one end of the second anti-static circuit is connected with the second test point, the other end of the second anti-static circuit is connected with a public port of the change-over switch, one end of the third anti-static circuit is connected with the third test point, the other end of the third anti-static circuit is connected with another public port of the change-over switch, one end of the fourth anti-static circuit is connected with the fifth test point, and the other end of the fourth anti-static circuit is connected with a GPIO (general purpose input/output) of the processor.
Optionally, the smart device further includes: the device comprises a first switch and a third resistor, wherein one end of the first switch is connected with the fifth test point, the other end of the first switch is connected with one end of the third resistor, and the other end of the third resistor is connected with one GPIO of the processor.
Optionally, the smart device further includes: the voltage dividing circuit comprises a first resistor and a second resistor, wherein one end of the first resistor is connected with the other end of the second switch, one end of the second switch is connected with a fifth test point, the other end of the first resistor is connected with one GPIO port of the processor and one end of the second resistor, and the other end of the second resistor is grounded.
Optionally, the intelligent device is: a smart phone, a tablet computer, or a smart watch.
In a third aspect, a motherboard is provided, the motherboard comprising a multiplexing test circuit according to any of claims 1-4.
The embodiment of the invention has the following beneficial effects:
it can be seen that, by the embodiment of the invention, the detection of the UART, the USB and the reserved channel is realized, so that the method and the device have the advantages of high integration level and cost reduction.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a USB download circuit and a fixture system.
Fig. 2 is a schematic diagram of a UART serial port circuit and a fixture system.
FIG. 3 is a schematic diagram of a multi-multiplexing test circuit according to an embodiment of the invention.
FIG. 4 is a schematic diagram of another multi-plexer test circuit provided by an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of an intelligent terminal disclosed in the embodiment of the present invention.
Fig. 6 is a schematic structural diagram of another intelligent terminal disclosed in the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," and "fourth," etc. in the description and claims of the invention and in the accompanying drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
The Mobile terminal in the present invention may include a smart phone (e.g., an Android phone, an iOS phone, a windows phone, etc.), a tablet computer, a palm computer, a notebook computer, a Mobile internet device (MID, Mobile internet devices), or a wearable device, and the Mobile terminal is merely an example, but not an exhaustive list, and includes but is not limited to the Mobile terminal, and for convenience of description, the Mobile terminal is referred to as a User Equipment (UE) in the following embodiments. Of course, in practical applications, the user equipment is not limited to the above presentation form, and may also include: intelligent vehicle-mounted terminal, computer equipment and the like.
For the platform chip solution, UART (Universal Asynchronous Receiver/Transmitter, english) is a port for a production line to test, a test point needs to communicate with a PC (personal computer, english), and a TVS (diode) protector also needs to be added; USB (Universal Serial Bus) is an OTG (On-The-Go) device and a port for communicating with a host, and after downloading software, a test point and a TVS device are also required.
Referring to fig. 1, fig. 1 is a USB download circuit and fixture system, referring to fig. 1, the system includes: the main board corresponds to the test point 10, the production line downloading jig 11, the program control power supply 12 and the software 13.
The main board corresponding test point 10 may include: VBUS, USB DM, USB DP and GND, this production line download jig 11 may include: the product downloading jig 11 is further connected with the program control power supply 12 through a VBAT (power supply voltage) thimble, and the product downloading jig 11 is further connected with the software 13.
The specific implementation manner of the connection between the product download jig 11 and the software 13 may be that the personal computer is connected to provide the software corresponding to the USB, or in practical applications, the software may be connected to the USB in other manners
The main flow of the test is that test points VBUS, USB DM, USB DP and GND corresponding to the terminal mainboard are respectively connected with a production line download jig: the VBUS thimble, the DM thimble, the DP thimble and the GND thimble are connected, and after the connection, the software 12 controls the mainboard to execute software downloading or updating flow through the USB so as to test whether the USB of the mainboard is normal.
Referring to fig. 2, fig. 2 provides a UART serial port circuit and fixture system, which includes: the main board corresponds to the test point 20, the production line downloading jig 21, the program control power supply 22 and the software 23.
The main board corresponding test point 20 may include: UARX, and GND, the production line download jig 21 may include: the product downloading jig 21 is further connected with a program control power supply 22 through a VBAT (power supply voltage) thimble, and the product downloading jig 21 is further connected with software 23.
The main flow of the test is that test points UATX, UARX and GND corresponding to a terminal mainboard are respectively downloaded to a production line in a jig: the UATX thimble, the UARX thimble and the GND thimble are connected, and after the connection, the software 23 controls the main board to execute UART transmission data so as to test whether the UART of the main board is normal or not.
Through the above description, the USB test and the UART test are both tested by different production line download tools, and the USB and the UART of the motherboard are tested by different circuits.
At present, three-in-one or even more switches cannot be realized through hardware. The current design does not need to consider multiplexing situations since the complexity of the circuit design is not so high.
Referring to fig. 3, fig. 3 provides a multi-multiplexing test circuit, which is shown in fig. 3 and includes: a first test point 1, a second test point 2, a third test point 3, a fourth test point 4, a fifth test point 5, a selector switch 301 and a central processing unit 302; the switch 301 may be a three-channel switch, each having two output ports. The first test point is connected with a first control port 3010 of the switch 301, the second test point and the third test point are respectively connected with two common ports 3018 of the switch 301, the fourth test point is grounded, the fifth test point is connected with an input/output port GPIO of the central processing unit 302, another GPIO of the central processing unit 302 is connected with a second control port 3017 of the switch 301, a channel 3011 of the switch 301 is connected with a UART interface of the central processing unit 302, a two channel 3012 of the switch 301 is connected with a USB of the central processing unit 302, and a three channel 3013 of the switch 301 is connected with a reserved channel.
The central processor 302 may integrate a modem (modem) and an application processor AP, with one GPIO of the central processor 302 synchronized with signals of another GPIO.
The switch 301 is connected to the two channel 3012 when the first control port is at a high level, to the one channel 3011 when the first control port is at a low level, and to the three channel 3013 when the second control port is at a high level.
The multi-multiplexing test circuit shown in fig. 3 can implement detection of UART and USB, and the specific principle may be as follows: for USB detection, the first test point may be connected to VBUS of USB, the second test point may be connected to USB DM, the third test point is connected to USB DP, and the fourth test point is connected to GND. Since the first test point is connected to VBUS, and the level of the first test point is a high level of 5V, the switch at this time is switched to another channel 3012 due to the high level input by the first control port, the multi-multiplexing test circuit at this time is equivalent to the USB download circuit and the fixture system shown in fig. 1, and the central processing unit 302 controls the motherboard to execute a software download or update process through the USB to test whether the USB of the motherboard is normal.
The multi-multiplexing test circuit shown in fig. 3 is used to detect the UART, at this time, the first test point is suspended, the second test point can be connected to the UART, the third test point is connected to the UARX, the fourth test point is connected to the GND, the multi-multiplexing test circuit is equivalent to the UART serial circuit and the fixture system shown in fig. 2, and at this time, the central processing unit 302 controls the main board to execute UART transmission data to test whether the UART of the main board is normal.
The multi-multiplexing test circuit shown in fig. 3 is used to detect a reserved channel (e.g., a video channel), which is generally performed after the one-channel or two-channel test is completed, and after the one-channel or two-channel test is completed, the reserved channel, e.g., the video channel, is switched to the three-channel to detect the reserved channel, so as to detect the reserved channel.
Through the description, the multi-multiplexing test circuit realizes the test of the USB, the UART and the reserved channel, so the multi-multiplexing test circuit has the advantages of reducing the redundancy of the circuit, reducing the cost and reducing the test points.
For the system shown in fig. 1 and fig. 2, the test points required for detecting USB and UART are, respectively, 4 test points for USB shown in fig. 1, 3 test points for UART shown in fig. 2, and 2 test points for reserved channel, and only 5 test points for the multi-multiplexing test circuit shown in fig. 3 are required to complete testing USB, UART and reserved channel, so that it has the advantage of reducing test points. In addition, the circuit shown in fig. 1, the circuit shown in fig. 2 and the system of the reserved channel are integrated, so that the integration level of the circuit is improved, and the redundancy of the circuit is reduced.
Optionally, the multiplex test circuit further includes a plurality of anti-static circuits, one end of the first anti-static circuit is connected to the first test point, the other end of the first anti-static circuit is connected to the first control port of the switch, one end of the second anti-static circuit is connected to the second test point, the other end of the second anti-static circuit is connected to a common port of the switch, one end of the third anti-static circuit is connected to the third test point, the other end of the third anti-static circuit is connected to another common port of the switch, one end of the fourth anti-static circuit is connected to the fifth test point, and the other end of the fourth anti-static circuit is connected to a GPIO of the central processing unit.
The static electricity of test point can be avoided to mainboard and central processing unit's influence, the basic physical characteristic of static to the setting antistatic circuit: the force of attraction and repulsion; a potential difference exists between the base and the ground; generation of discharge current due to these characteristics, electrostatic discharge may cause the following damage to a semiconductor device: the thin oxide layer is broken down; the leakage current density is high, causing the conductor to be fused; leakage current, which causes premature failure, increases and breakdown voltage becomes high. Therefore, static electricity of the test point can easily cause the thin insulating layer of the mainboard to be damaged and lose efficacy, and further the quality of the mainboard is influenced, so that the service life of the mainboard can be prolonged by adding the anti-static circuit. In addition, the leakage current of the chip is increased by static electricity, which affects the service life of the central processing unit, so the method has the advantage of prolonging the service life of the central processing unit.
Referring to fig. 4, the fifth test point may be connected to a high level, and the voltage value of the high level is between the high level and the low level.
Optionally, the multi-multiplexing test circuit further includes: a first switch K1 and a third resistor R3, wherein one end of the first switch K1 is connected to the fifth test point, the other end of the first switch K1 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to a GPIO port of the cpu 302.
Optionally, the multi-multiplexing test circuit further includes a second switch K2 and a voltage divider circuit, the voltage divider circuit includes a first resistor R1 and a second resistor R2, wherein one end of the first resistor R1 is connected to the other end of the second switch K2, one end of the second switch K2 is connected to the fifth test point, the other end of the first resistor R1 is connected to another GPIO port of the central processing unit 302 and one end of the second resistor R2, and the other end of the second resistor R2 is grounded.
The switches K1 and K2 may realize a second control port for accessing the fifth test point, so as to realize the access to the reserved channel to realize the detection of the reserved channel, the switches K1 and K2 may specifically be switching tubes, such as Thin Film Transistors (TFTs), and the control port of the switch may be connected to other GPIOs of the central processing unit.
The voltage divider circuit performs voltage division operation on the battery voltage through the values of R1 and R2, thus reducing the input level of the CPU 302 and protecting the CPU.
The present invention further provides a motherboard, where the motherboard includes a multi-multiplexing test circuit shown in fig. 3 or fig. 4, and the multi-multiplexing test circuit may specifically refer to the description of fig. 3 or fig. 4, which is not described herein again.
Referring to fig. 5, fig. 5 provides a smart device comprising a motherboard 509, one or more processors 501, a memory 502, a transceiver 503, and one or more programs stored in the memory 502 and configured to be executed by the one or more processors, in particular, the processor 501 comprising: a modem and an application processor AP,
the main board 509 includes: a first test point, a second test point, a third test point, a fourth test point, a fifth test point, a change-over switch and a processor 501; the switch 3 may be a three-channel switch, each having two output ports. The first test point is connected with a first control port of the switch, the second test point and the third test point are respectively connected with two public ports of the switch, the fourth test point is grounded, the fifth test point is connected with an input/output port GPIO of the processor 501, the other GPIO of the processor 501 is connected with a second control port of the switch, one channel of the switch is connected with a UART interface of the processor 501, two channels of the switch are connected with a USB of the processor 501, and three channels of the switch are connected with a reserved channel.
The processor 501 may integrate a modem (modem) and an application processor AP, with one GPIO of the processor 501 synchronizing signals of another GPIO.
The change-over switch is connected with the two channels when the first control port is at a high level, is connected with the one channel when the first control port is at a low level, and is connected with the three channels when the second control port is at a high level.
The mainboard further comprises a plurality of anti-static circuits, one end of the first anti-static circuit is connected with the first test point, the other end of the first anti-static circuit is connected with the first control port of the change-over switch, one end of the second anti-static circuit is connected with the second test point, the other end of the second anti-static circuit is connected with a public port of the change-over switch, one end of the third anti-static circuit is connected with the third test point, the other end of the third anti-static circuit is connected with another public port of the change-over switch, one end of the fourth anti-static circuit is connected with the fifth test point, and the other end of the fourth anti-static circuit is connected with a GPI.
The Processor 501 may be a Processor or a controller, such as a Central Processing Unit (CPU), a general-purpose Processor, a Digital Signal Processor (DSP), an Application-Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a transistor logic device, a hardware component, or any combination thereof. Which may implement or perform the various illustrative logical blocks, modules, and circuits described in connection with the disclosure. The processor may also be a combination of computing functions, e.g., comprising one or more microprocessors, DSPs, and microprocessors, among others. The transceiver 503 may be a communication interface, a transceiver circuit, etc., wherein the communication interface is a generic term and may include one or more interfaces.
This mainboard still includes: a first switch K1 and a third resistor R3, wherein one end of the first switch K1 is connected to the fifth test point, the other end of the first switch K1 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to another GPIO port of the cpu 302.
Optionally, the motherboard further includes a second switch K2 and a voltage dividing circuit, the voltage dividing circuit includes a first resistor R1 and a second resistor R2, wherein one end of the first resistor R1 is connected to the other end of the second switch K2, one end of the second switch K2 is connected to the fifth test point, the other end of the first resistor R1 is connected to another GPIO port of the central processing unit 302 and one end of the second resistor R2, and the other end of the second resistor R2 is grounded.
Fig. 6 is a block diagram illustrating a partial structure of a server, which is an intelligent device provided by an embodiment of the present invention. Referring to fig. 6, the server includes: radio Frequency (RF) circuit 910, memory 920, input unit 930, sensor 950, audio circuit 960, Wireless Fidelity (WiFi) module 970, application processor AP980, motherboard 810, and power supply 990. Those skilled in the art will appreciate that the smart device architecture shown in FIG. 6 does not constitute a limitation of smart devices and may include more or fewer components than shown, or some components in combination, or a different arrangement of components.
The main board 509 includes: the test system comprises a first test point, a second test point, a third test point, a fourth test point, a fifth test point, a change-over switch and an application processor AP 980; the switch 3 may be a three-channel switch, each having two output ports. The first test point is connected with a first control port of the change-over switch, the second test point and the third test point are respectively connected with two public ports of the change-over switch, the fourth test point is grounded, the fifth test point is connected with an input output port GPIO of an application processor AP980, the other GPIO of the application processor AP980 is connected with a second control port of the change-over switch, one channel of the change-over switch is connected with a UART interface of the application processor AP980, the two channels of the change-over switch are connected with a USB of the application processor AP980, and the three channels of the change-over switch are connected with a reserved channel.
The application processor AP980 may integrate a modem (modem) and an application processor AP, with one GPIO of the application processor AP980 synchronized with signals of another GPIO.
The change-over switch is connected with the two channels when the first control port is at a high level, is connected with the one channel when the first control port is at a low level, and is connected with the three channels when the second control port is at a high level.
The mainboard further comprises a plurality of anti-static circuits, one end of the first anti-static circuit is connected with the first test point, the other end of the first anti-static circuit is connected with the first control port of the change-over switch, one end of the second anti-static circuit is connected with the second test point, the other end of the second anti-static circuit is connected with a public port of the change-over switch, one end of the third anti-static circuit is connected with the third test point, the other end of the third anti-static circuit is connected with another public port of the change-over switch, one end of the fourth anti-static circuit is connected with the fifth test point, and the other end of the fourth anti-static circuit is connected with a GPIO of the.
The following describes each component of the smart device in detail with reference to fig. 6:
the input unit 930 may be used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the smart device. Specifically, the input unit 930 may include a touch display 933, a handwriting pad 931, and other input devices 932. The input unit 930 may also include other input devices 932. In particular, other input devices 932 may include, but are not limited to, one or more of physical keys, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and the like.
The AP980 is a control center of the smart device, connects various parts of the entire smart device using various interfaces and lines, and performs various functions of the smart device and processes data by running or executing software programs and/or modules stored in the memory 920 and calling data stored in the memory 920, thereby integrally monitoring the smart device. Optionally, AP980 may include one or more processing units; alternatively, the AP980 may integrate an application processor that handles primarily the operating system, user interface, and applications, etc., and a modem processor that handles primarily wireless communications. It will be appreciated that the modem processor described above may not be integrated into the AP 980.
Further, the memory 920 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.
RF circuitry 910 may be used for the reception and transmission of information. In general, the RF circuit 910 includes, but is not limited to, an antenna, at least one Amplifier, a transceiver, a coupler, a Low Noise Amplifier (LNA), a duplexer, and the like. In addition, the RF circuit 910 may also communicate with networks and other devices via wireless communication. The wireless communication may use any communication standard or protocol, including but not limited to Global System for mobile communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), email, Short Messaging Service (SMS), and the like.
The smart device may also include at least one sensor 950, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor may include an ambient light sensor and a proximity sensor, wherein the ambient light sensor may adjust the brightness of the touch display screen according to the brightness of ambient light, and the proximity sensor may turn off the touch display screen and/or the backlight when the mobile phone moves to the ear. As one of the motion sensors, the accelerometer sensor can detect the magnitude of acceleration in each direction (generally, three axes), can detect the magnitude and direction of gravity when stationary, and can be used for applications of recognizing the posture of a mobile phone (such as horizontal and vertical screen switching, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer and tapping), and the like; as for other sensors such as a gyroscope, a barometer, a hygrometer, a thermometer, and an infrared sensor, which can be configured on the mobile phone, further description is omitted here.
The audio circuitry 960, speaker 961, microphone 962 may provide an audio interface between the user and the smart device. The audio circuit 960 may transmit the electrical signal converted from the received audio data to the speaker 961, and the audio signal is converted by the speaker 961 to be played; on the other hand, the microphone 962 converts the collected sound signal into an electrical signal, and the electrical signal is received by the audio circuit 960 and converted into audio data, and the audio data is processed by the audio playing AP980, and then sent to another mobile phone via the RF circuit 910, or played to the memory 920 for further processing.
WiFi belongs to short-distance wireless transmission technology, and the mobile phone can help a user to receive and send e-mails, browse webpages, access streaming media and the like through the WiFi module 970, and provides wireless broadband Internet access for the user. Although fig. 6 shows the WiFi module 970, it is understood that it does not belong to the essential constitution of the smart device and can be omitted entirely as needed within the scope not changing the essence of the invention.
The smart device also includes a power supply 990 (e.g., a battery or a power module) for supplying power to various components, and optionally, the power supply may be logically connected to the AP980 via a power management system, so that functions of managing charging, discharging, and power consumption are implemented via the power management system.
It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the invention. Further, those skilled in the art should also appreciate that the embodiments described in the specification are exemplary embodiments and that the acts and modules illustrated are not necessarily required to practice the invention.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may be implemented in the form of a software program module.
The integrated units, if implemented in the form of software program modules and sold or used as stand-alone products, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a memory and includes several instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash Memory disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.
The above embodiments of the present invention are described in detail, and the principle and the implementation of the present invention are explained by applying specific embodiments, and the above description of the embodiments is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims (10)

1. A multi-plexer test circuit comprising: the test device comprises a first test point, a second test point, a third test point, a fourth test point, a fifth test point and a change-over switch; wherein,
the change-over switch is a three-channel switch, the first test point is connected with a first control port of the change-over switch, the second test point and the third test point are respectively connected with two common ports of the change-over switch, the fourth test point is grounded, the fifth test point is connected with an input output port of a central processing unit (GPIO), the other GPIO of the central processing unit is connected with a second control port of the change-over switch, one channel of the change-over switch is connected with a Universal Asynchronous Receiver Transmitter (UART) interface of the central processing unit, the second channel of the change-over switch is connected with a Universal Serial Bus (USB) of the central processing unit, and the three channels of the change-over switch are connected with a reserved channel;
one GPIO of the central processing unit is synchronous with another GPIO signal;
the change-over switch is connected with a channel when the first control port is at a low level, connected with two channels when the first control port is at a high level, and connected with three channels when the second control port is at a high level.
2. The circuit of claim 1, wherein the multi-plexer test circuit further comprises: the first anti-static circuit is connected with the first test point, the other end of the first anti-static circuit is connected with the first control port of the change-over switch, one end of the second anti-static circuit is connected with the second test point, the other end of the second anti-static circuit is connected with a public port of the change-over switch, one end of the third anti-static circuit is connected with the third test point, the other end of the third anti-static circuit is connected with another public port of the change-over switch, one end of the fourth anti-static circuit is connected with the fifth test point, and the other end of the fourth anti-static circuit is connected with a GPIO of the central processing unit.
3. The circuit of claim 1, wherein the multi-plexer test circuit further comprises: the circuit comprises a first switch and a third resistor, wherein one end of the first switch is connected with the fifth test point, the other end of the first switch is connected with one end of the third resistor, and the other end of the third resistor is connected with one GPIO of the central processing unit.
4. The circuit of claim 1, wherein the multi-plexer test circuit further comprises: the voltage dividing circuit comprises a first resistor and a second resistor, wherein one end of the first resistor is connected with the other end of the second switch, one end of the second switch is connected with a fifth test point, the other end of the first resistor is connected with one GPIO port of the central processing unit and one end of the second resistor, and the other end of the second resistor is grounded.
5. A smart device, the device comprising: a motherboard, one or more processors, memory, a transceiver, and one or more programs stored in the memory and configured to be executed by the one or more processors, the processor comprising: a modem and an application processor AP;
the main board includes: the test device comprises a first test point, a second test point, a third test point, a fourth test point, a fifth test point and a change-over switch; wherein,
the switch is a three-channel switch, the first test point is connected with a first control port of the switch, the second test point and the third test point are respectively connected with two common ports of the switch, the fourth test point is grounded, the fifth test point is connected with an input output port of the processor, the other GPIO of the processor is connected with a second control port of the switch, one channel of the switch is connected with a Universal Asynchronous Receiver Transmitter (UART) interface of the processor, the two channels of the switch are connected with a Universal Serial Bus (USB) of the processor, and the three channels of the switch are connected with a reserved channel;
one GPIO of the processor is synchronous with another GPIO signal;
the change-over switch is connected with a channel when the first control port is at a low level, connected with two channels when the first control port is at a high level, and connected with three channels when the second control port is at a high level.
6. The smart device of claim 5, further comprising: the first anti-static circuit is connected with the first test point, the other end of the first anti-static circuit is connected with the first control port of the change-over switch, one end of the second anti-static circuit is connected with the second test point, the other end of the second anti-static circuit is connected with a public port of the change-over switch, one end of the third anti-static circuit is connected with the third test point, the other end of the third anti-static circuit is connected with another public port of the change-over switch, one end of the fourth anti-static circuit is connected with the fifth test point, and the other end of the fourth anti-static circuit is connected with a GPIO (general purpose input/output) of the processor.
7. The smart device of claim 5, further comprising: the device comprises a first switch and a third resistor, wherein one end of the first switch is connected with the fifth test point, the other end of the first switch is connected with one end of the third resistor, and the other end of the third resistor is connected with one GPIO of the processor.
8. The smart device of claim 5, further comprising: the voltage dividing circuit comprises a first resistor and a second resistor, wherein one end of the first resistor is connected with the other end of the second switch, one end of the second switch is connected with a fifth test point, the other end of the first resistor is connected with one GPIO port of the processor and one end of the second resistor, and the other end of the second resistor is grounded.
9. The smart device of any one of claims 5-8, wherein the smart device is: a smart phone, a tablet computer, or a smart watch.
10. A motherboard comprising a multiplexing test circuit according to any of claims 1-4.
CN201710770649.5A 2017-08-31 2017-08-31 Multi-multiplexing test circuit and related product Expired - Fee Related CN107688518B (en)

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CN205725735U (en) * 2016-04-14 2016-11-23 科立讯通信股份有限公司 Communication interface multiplexing switching circuit, device and digital handset
CN106919529A (en) * 2017-03-06 2017-07-04 南京新联电子股份有限公司 The wireless communication module method for designing for supporting USB and UART serial ports compatible

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* Cited by examiner, † Cited by third party
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US20160236637A1 (en) * 2015-02-18 2016-08-18 Siddhartha Gopal Krishna Input signal mismatch detection circuit
CN105404211A (en) * 2015-12-17 2016-03-16 中国电子信息产业集团有限公司第六研究所 Coupling communication plate based on EtherCAT technology
CN205725735U (en) * 2016-04-14 2016-11-23 科立讯通信股份有限公司 Communication interface multiplexing switching circuit, device and digital handset
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