CN107678337A - A kind of main control unit structure for being used to control track traffic signal - Google Patents

Abstract

The present invention relates to a kind of main control unit structure for being used to control track traffic signal, the structure provides a series of daughter card of communications and control port for one to motherboard, two sets of symmetrically the same circuit structures are integrated with described daughter card, respectively passage A and passage B, described passage A and passage B respectively include a CPU minimum system, interface and power circuit.Compared with prior art, the present invention on power supply and data processing have deeper into monitoring and verifying function, there is more preferable independence and reliability.

Description

A main control unit structure for controlling rail traffic signals

technical field

The invention relates to the field of rail traffic signals, in particular to a main control unit structure for controlling rail traffic signals.

Background technique

In the field of rail transit signals, the control board of the signal usually realizes the control function by a relatively simple executive circuit or a simple single-chip microcomputer. These existing circuits have reliability loopholes to varying degrees, including: CPU minimum system The operation results of the CPU lack effective monitoring, the CPU software running process lacks hardware monitoring and verification, the CPU working power supply system lacks monitoring and reliability assurance, and the CPU communication and control interfaces are not rich enough.

After retrieval, the Chinese Patent Publication No. CN205541437U discloses an intelligent traffic signal machine, including a main control unit installed in the signal cabinet body and a power supply for power supply, the main control unit includes a main board and a processor arranged on the main board, processing There is a built-in clock unit in the device, and the processor is connected with a data acquisition unit, a vehicle video detection unit, a traffic light control unit, a memory, and an alarm through its communication interface. Specifically, the data acquisition unit includes a water level sensor, a spark sensor, and a temperature sensor. The sensor, the spark sensor and the temperature sensor are connected to the communication interface through the signal conditioning circuit. The invention has excellent cost performance, high integration, high reliability, strong control function, low power consumption during operation, and standardized system expansion and system configuration. But this invention is aimed at urban traffic roads, not rail transit, and the processor in the signal machine is just a simple single-chip microcomputer, which cannot solve the loophole in reliability.

Contents of the invention

The purpose of the present invention is to provide a kind of main control unit structure for controlling rail traffic signal in order to overcome the defective that above-mentioned prior art exists

The purpose of the present invention can be achieved through the following technical solutions:

A main control unit structure for controlling rail traffic signals, the structure is a daughter board that provides a series of communication and control ports to the motherboard, and the daughter board integrates two sets of symmetrical and identical circuit structures , are channel A and channel B respectively, and said channel A and channel B each include a CPU minimum system, an interface and a power supply circuit.

Preferably, the asynchronous communication UART interface on CPU A is connected to the asynchronous communication UART interface on CPU B to realize the communication between the two channel CPUs.

Preferably, the channel A uses the asynchronous communication UART0 interface of CPU A, and the channel B uses the asynchronous communication UART1 interface of CPU B.

Preferably, a 1206-packaged resistor with a resistance value of 3.16K is connected in series on all asynchronous communication UART signal lines.

Preferably, each of the two CPUs is connected to an external watchdog circuit, and when any one of the CPU software runs away, the external watchdog circuit corresponding to the CPU will automatically place the CPU in the RESET state .

Preferably, each of the two CPUs has a voltage monitoring circuit, and when any one of the CPUs is detected to be undervoltage, the voltage monitoring circuit corresponding to the CPU will automatically put the CPU in a RESET state.

Preferably, a general-purpose I/O port GPIO of CPU A is connected to the interrupt Interrupt interface of CPU B, and a general-purpose I/O port GPIO of CPU B is connected to the interrupt Interrupt interface of CPU A;

The RESET port of CPU A is connected to the Interrupt port of CPU B, and the RESET port of CPU B is connected to the Interrupt port of CPU A.

Preferably, the motherboard provides two differentiated 3.3V power supplies, which are provided to the two channels through an independent connector;

The two 3.3V power supplies are respectively converted into two CPU core power supplies, a memory chip power supply, SD_REF power supply and SD_VTT power supply through two channel power supply circuits.

Preferably, the 1.2V power supply of the core power supply of CPU A is generated by the 3.3V power supply of channel A through a Buck circuit; the 1.8V power used by the memory chip DDR2 of CPUA is generated by the 3.3V power supply of channel A through another Buck circuit.

Preferably, the chips of the two CPUs are MCF54418 chips of NXP; the storage devices of the two CPUs are NorFlash; the memory of the two CPUs is a 1Gbit DDR2 chip.

Compared with the prior art, the present invention has the following advantages:

1. The high-reliability main control unit module is composed of two CPUs, and has a communication port for exchanging data, and then compares the key calculation results. It has more in-depth monitoring and verification functions than the general dual-channel architecture technology.

2. The high-reliability main control unit module uses an external watchdog circuit, which has better independence and reliability than the built-in watchdog or even soft watchdog used in general main control unit modules, and can monitor failures. possibility is further reduced.

3. The general main control module lacks the monitoring and inspection of the CPU’s operating power supply. Usually, when the power supply voltage of the CPU exceeds the range of the manual, the device manufacturer cannot guarantee that the CPU’s function is normal, and the failure mode and failure rate are greatly increased. Some exceptions lead to false results that may not even be detectable.

4. The high-reliability main control unit module uses a heterogeneous power supply design for the two CPUs, which greatly reduces the possibility of simultaneous power failures, and the power monitoring function also complements the general main control module for CPU power supply voltage monitoring the gap.

Description of drawings

Fig. 1 is an example diagram of the structure of the present invention;

Figure 2 is a communication port connection diagram between two channel CPUs;

Fig. 3 is the example diagram of the power tree of CPU A of the present invention;

FIG. 4 is an example diagram of a power tree of CPU B of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described below, obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

As shown in Figure 1-4, a main control unit structure for controlling rail transit signals is a daughter board that provides a series of communication and control ports to the motherboard. The daughter board integrates two A set of symmetrical and identical circuit structures are respectively channel A and channel B, and each of said channel A and channel B includes a CPU minimum system, several interfaces and power supply circuits.

The asynchronous communication UART interface on the CPU A is connected to the asynchronous communication UART interface on the CPU B to realize the communication between the two channel CPUs.

The channel A uses the asynchronous communication UART0 interface of CPU A, and the channel B uses the asynchronous communication UART1 interface of CPU B.

A 1206-packaged resistor with a resistance value of 3.16K is connected in series on all the asynchronous communication UART signal lines.

Each of the two CPUs is connected to an external watchdog circuit. When the software of any one of the CPUs runs away, the external watchdog circuit corresponding to the CPU will automatically place the CPU in the RESET state .

Each of the two CPUs has a voltage monitoring circuit. When any one of the CPUs is detected to be undervoltage, the voltage monitoring circuit corresponding to the CPU will automatically place the CPU in a RESET state.

A general-purpose I/O port GPIO of the CPU A is connected to the interrupt Interrupt interface of the CPU B, and a general-purpose I/O port GPIO of the CPU B is connected to the interrupt Interrupt interface of the CPU A. The reset RESET interface of CPU A is connected to the interrupt Interrupt interface of CPU B, and the reset RESET interface of CPU B is connected to the interrupt Interrupt interface of CPU A.

The motherboard provides two differentiated 3.3V power supplies, which are respectively provided to the two channels through an independent connector.

The two 3.3V power supplies are respectively converted into two CPU core power supplies, a memory chip power supply, SD_REF power supply and SD_VTT power supply through two channel power supply circuits. The structures of the power supply circuits of the two channels are different. The 1.2V power supply of the core power supply of CPU A is generated by the 3.3V power supply of channel A through a Buck circuit. The 1.8V power supply used by the memory chip DDR2 of CPU A is generated by the 3.3V power supply 3.3V of channel A through another Buck circuit.

The Buck circuit described above is built using TI's LM3671. The chips of the two CPUs are MCF54418 chips of NXP Company. The storage devices of the two CPUs are NorFlash. The memories of the two CPUs are 1Gbit DDR2 chips.

The main control CPU of this embodiment has used the MCF54418 chip of NXP Company, and this chip is the CPU of industrial-grade Coldfire architecture, and the storage device uses NorFlash to ensure the valid data storage time of 20 years, and the memory uses the DDR2 chip of 1Gbit.

As shown in Figure 2, there are several communication ports between the CPUs of the two channels, and a UART interface with flow control for communication between the two channels. Channel A uses UART0 of the CPU, and channel B uses UART1 of the CPU, and a certain difference is maintained between the two. A 1206-packaged 3.16K resistance resistor is connected in series on all UART signal lines. These resistors can prevent the IO current of the normal working side channel from being powered off when one channel loses power and the other channel has normal working power. After the channel is powered on, the circuit of the de-energized channel is falsely activated. The UART interface can realize the interactive comparison of the calculation results between the two channel CPUs, and provide a deeper dual-channel verification function than the general design.

In addition, each channel has a GPIO connected to the interrupt signal of the other channel, which can trigger the interrupt of the CPU of the other channel through the GPIO to notify the other party in real time. The RESET signal of each channel will also be connected to the interrupt signal of another channel. When one channel enters the reset state, the other CPU can know it in time.

As shown in Figure 3, the power supply system on the board is also divided into two channels according to the minimum system of the CPU it serves. The motherboard needs to provide two differentiated 3.3V power supplies to two channels through an independent connector. channel used. In this embodiment, the 3.3V power supply of each channel is converted into 1.2V, 1.8V, SD_REF and SD_VTT power supply through differentiated power supply circuits.

The 1.2V power supply of the core power supply of the CPU is generated by 3.3V through a Buck circuit, and the Buck circuit is built using TI's LM3671. The 1.8V power supply used by DDR2 is generated by another Buck circuit from 3.3V.

CPU controls NorFlash through the FlexBUS bus. Since NorFlash needs to store startup information, the chip select space CS0 is allocated to NorFlash. The interface of NorFlash is asynchronous and works in 8-bit data bus mode. Set it to 8bit data bus mode by pulling the BYTE# signal of NorFlash low. In this mode, the data bus is DQ0 ~ DQ7, and A-1 ~ A22 are used as the address bus. Similarly, a 22 ohm resistor is connected in series with each signal line of the FlexBUS interface to improve signal integrity. WP#/ACC is pulled high to disable the write protection function.

The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person familiar with the technical field can easily think of various equivalents within the technical scope disclosed in the present invention. Modifications or replacements shall all fall within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (10)

1. A main control unit structure for controlling rail traffic signals, the structure is a sub-board that provides a series of communication and control ports to the motherboard, it is characterized in that: the described sub-board integrates two A set of symmetrical and identical circuit structures are respectively channel A and channel B, and each of said channel A and channel B includes a CPU minimum system, an interface and a power supply circuit. 2. a kind of main control unit structure that is used to control rail traffic signal according to claim 1 is characterized in that: wherein the asynchronous communication UART interface on the CPU A connects the asynchronous communication UART interface on the CPU B, realizes described Communication between two channel CPUs. 3. A kind of main control unit structure that is used to control rail traffic signal according to claim 2, it is characterized in that: described passage A uses the asynchronous communication UART0 interface of CPU A, and described passage B uses the UART0 interface of CPU B Asynchronous communication UART1 interface. 4. A kind of main control unit structure that is used to control rail traffic signal according to claim 2, it is characterized in that: all the resistances of 1206 encapsulation 3.16K resistances are connected in series on all asynchronous communication UART signal lines. 5. a kind of master control unit structure that is used to control rail transit signal according to claim 1 is characterized in that: two CPUs are respectively connected with an external watchdog circuit, when any one of described CPU software runs away When the CPU is active, the external watchdog circuit corresponding to the CPU will automatically put the CPU in the RESET state. 6. a kind of main control unit structure that is used to control rail traffic signal according to claim 1 is characterized in that: two CPUs respectively have a voltage monitoring circuit, when detecting described any one CPU undervoltage, The voltage monitoring circuit corresponding to the CPU will automatically place the CPU in a RESET state. 7. A kind of main control unit structure that is used to control rail traffic signal according to claim 1, it is characterized in that: a general I/O port GPIO of CPU A is connected to the interruption Interrupt interface of CPU B, one of CPU B The general-purpose I/O port GPIO is connected to the interrupt Interrupt interface of CPU A; The RESET port of CPU A is connected to the Interrupt port of CPU B, and the RESET port of CPU B is connected to the Interrupt port of CPU A. 8. A kind of main control unit structure that is used to control rail traffic signal according to claim 1, it is characterized in that: the 3.3V power supply of two-way differentiation is provided on the described motherboard, respectively through an independent connector Provided for two channels; The two 3.3V power supplies are respectively converted into two CPU core power supplies, a memory chip power supply, SD_REF power supply and SD_VTT power supply through two channel power supply circuits. 9. a kind of main control unit structure that is used to control rail traffic signal according to claim 8 is characterized in that: the nuclear power supply 1.2V power supply of CPU A is generated by the 3.3V power supply of channel A by a Buck circuit; CPU A The 1.8V power supply used by the memory chip DDR2 is generated by the 3.3V power supply of channel A through another Buck circuit. 10. a kind of main control unit structure that is used to control rail transit signal according to claim 1 is characterized in that: the chip of two CPUs is the MCF54418 chip of NXP company; The storage device of two CPUs is NorFlash; The memory of the CPU is a 1Gbit DDR2 chip.