CN107464843A - 半导体结构、hemt结构及其形成方法 - Google Patents

半导体结构、hemt结构及其形成方法 Download PDF

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CN107464843A
CN107464843A CN201710407585.2A CN201710407585A CN107464843A CN 107464843 A CN107464843 A CN 107464843A CN 201710407585 A CN201710407585 A CN 201710407585A CN 107464843 A CN107464843 A CN 107464843A
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layer
active layer
hemt
exposure
iii
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CN107464843B (zh
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张耀中
陈柏智
余俊磊
蔡俊琳
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本揭露提供一种半导体结构、HEMT结构及其形成方法。所述半导体结构包含沟道层；位于所述沟道层上方的有源层，其中所述有源层经配置以形成二维电子气体2DEG，所述二维电子气体沿着所述沟道层与所述有源层之间的界面形成在所述沟道层中；形成在所述有源层的顶表面上方的栅极电极；以及位于所述有源层的所述顶表面上方的源极/漏极电极；其中所述有源层包含从所述顶表面到所述有源层的底表面依序堆栈的第一层与第二层，相较于所述第二层，所述第一层具有较高的铝(Al)原子浓度。

Description

半导体结构、HEMT结构及其形成方法
技术领域
本揭露涉及一种半导体结构、HEMT结构及其形成方法。
背景技术
由于高电流密度、高崩溃电压以及低OB阻抗，高电子移动性晶体管(HighElectron Mobility Transistors，HEMT)适合用于电力应用。HEMT结构包含沟道层与有源层。二维电子气体(two-dimensional electron gas，2DEG)在沟道层中产生，所述沟道层与有源层的界面相邻。2DEG用于HEMT结构中作为电荷载体。HEMT结构的问题为电荷落入栅极的漏极侧，其可造成已知为在高电压操作之下的“电流崩塌(current collapse)”现象。因此，需要具有低开启阻抗与低电流崩塌以及改进的界面捕捉密度(interface trapdensity)与线性漏极电流退化的装置。本揭露的实施例至少响应这些需求。
发明内容
本揭露的一些实施例提供一种半导体结构，所述半导体结构包含沟道层；位于所述沟道层上方的有源层，其中所述有源层经配置以形成二维电子气体(two-dimensionalelectron gas，2DEG)，所述二维电子气体沿着所述沟道层与所述有源层之间的界面形成在所述沟道层中；形成在所述有源层的顶表面上方的栅极电极；以及位于所述有源层的所述顶表面上方的源极/漏极电极；其中所述有源层包含从所述顶表面到所述有源层的底表面依序堆栈的第一层与第二层，相较于所述第二层，所述第一层具有较高的铝(Al)原子浓度。
附图说明
为协助读者达到最佳理解效果，建议在阅读本揭露时同时参考附件图标及其详细文字叙述说明。请注意为遵循业界标准作法，本专利说明书中的图式不一定按照正确的比例绘制。在某些图式中，尺寸可能刻意放大或缩小，以协助读者清楚了解其中的讨论内容。
图1到8(b)是根据本揭露的一些实施例说明各种阶段所制造的III-V HEMT结构的剖面示意图。
图9是根据本揭露的一些实施例说明Ga原子与Al原子的X射线能量散射分析(energy dispersive X-ray，EDX)。
图10是根据本揭露的一些实施例说明发明人进行的实验结果的图表，说明在不同深度有或没有高Al扩散层所制造的III-V HEMT上测量的界面捕捉密度Dit的值。
图11是根据本揭露的一些实施例说明发明人所进行的实验结果的图表，说明线性漏极电流(linear drain current(Idlin))退化为有或没有高Al扩散层所制造的III-VHEMT上测量的应力时间(stress time)的函数。
图12是根据本揭露的实施例说明发明人所进行的实验结果的图表，说明动态最小“开启(on)”阻抗(Rdson)比例为有或没有高Al扩散层所制造的III-V HEMT群组上测量的应力电压的函数。
具体实施方式
本揭露提供了数个不同的实施方法或实施例，可用于实现本揭露的不同特征。为简化说明起见，本揭露也同时描述了特定零组件与布置的范例。请注意提供这些特定范例的目的仅在于示范，而非予以任何限制。举例来说，在以下说明第一特征如何在第二特征上或上方的叙述中，可能会包括某些实施例，其中第一特征与第二特征为直接接触，而叙述中也可能包括其它不同实施例，其中第一特征与第二特征中间另有其它特征，以致于第一特征与第二特征并不直接接触。此外，本揭露中的各种范例可能使用重复的参考数字和/或文字注记，以使文件更加简单化和明确，这些重复的参考数字与注记不代表不同的实施例与/或配置之间的关联性。
另外，本揭露在使用与空间相关的叙述词汇，如“在…之下”，“低”，“下”，“上方”，“之上”，“下”，“顶”，“底”和类似词汇时，为便于叙述，其用法均在于描述图标中一个组件或特征与另一个(或多个)组件或特征的相对关系。除了图标中所显示的角度方向外，这些空间相对词汇也用来描述所述装置在使用中以及操作时的可能角度和方向。所述装置的角度方向可能不同(旋转90度或其它方位)，而在本揭露所使用的这些空间相关叙述可以同样方式加以解释。
尽管本揭露的广范围所要求的数值范围与参数是约略值，但在特定范例中所阐述的数值尽可能精准。然而，任何数值本质上含有在个别测试测量中得到的标准偏差所必然造成的一些误差。再者，在本文中，“约”通常是指在给定值或范围的10％、5％、1％或0.5％内。或者，“约”是指所属领域的技术人员可接受的平均的标准偏差内。在操作/工作范例之外，除非特别指名，否则本文所揭露的所有的数值范围、数量、值、与比例，例如材料的量、时间期间、温度、操作条件、数量的比例、及其类似者应被理解为受到“约”字修饰。据此，除非有相反的指示，本揭露以及所附随的权利要求书所阐述的数值参数是约略数，其可视需要而变化。至少，应根据所报导的有意义的位数数目并且使用通常的进位技术，解读各个数值参数。本文中，范围可表示为从一端点到另一端点，或是在两个端点之间。除非特别声明，否则本文揭露的所有范围都包含端点。
本揭露涉及III-V高电子移动性晶体管(HEMT)及其制造方法。虽然本揭露是以特定实施例描述，然而由权利要求书所定义的本揭露的原理显然可应用于本揭露所述的本揭露的特定实施例之外。再者，在本揭露的说明中，为了不模糊本揭露的发明方面，故忽略一些细节。所忽略的细节为所属领域的技术人员的知识范围的内。
硅衬底上的III-V HEMT是作为电压转换器应用的功率切换晶体管。相较于硅功率晶体管，III-V HEMT因宽带隙性质而有低开启状态阻抗与低切换损失的特征。在本揭露中，“III-V族半导体(group III-V semiconductor)”是指包含至少一III族元素与至少一V族元素的化合物半导体，例如但不限于氮化镓(GaN)、氮化铝镓(AlGaN)、砷化镓(GaAs)、氮化铟铝镓(InAlGaN)、氮化铟镓(InGaN)、以及类似物。在类似的方式中，“III-氮化物半导体”是指包含氮与至少一III族元素的化合物半导体，例如但不限于GaN、AlGaN、氮化铟(InN)、氮化铝(AlN)、氮化铟镓(InGaN)、氮化铟铝镓(InAlGaN)、以及类似物。
图1到8(b)是根据本揭露的一些实施例说明不同阶段所制造的III-V HEMT结构的剖面示意图。图1为根据本揭露的一实施例说明在初始制造阶段的III-V HEMT的剖面示意图。提供适合作为III-V HEMT的支撑衬底的半导体衬底302。半导体衬底302包含多层。在一些实施例中，半导体衬底302包含大块硅，多个半导体层形成在所述大块硅上。半导体衬底302包括适合作为制造III-V族半导体装置的衬底的任何材料。在一些实施例中，半导体衬底302包含硅(Si)、碳化硅(SiC)、蓝宝石、以及类似物。或者，在一些实施例中，半导体衬底302包括可制造III-V族半导体装置的材料的天然衬底，以及例如可为天然的GaN或其它III-氮化物衬底。再者，虽然半导体衬底302显示为实质单一衬底，然而，在其它实施例中，半导体衬底302相当于绝缘体衬底上半导体，例如绝缘体上硅(silicon on insulator，SOI)或绝缘体上锗(germanium on insulator，GOI)衬底。
在图2中，在半导体衬底302上方，连续形成过渡结构304与沟道层312。在一些实施例中，过渡结构304包括多个层，媒介从半导体衬底302到沟道层312的晶格过渡。在此方式中，可减少半导体衬底302与沟道层312之间的晶格错位。
在一些实施例中，过渡结构304包含半导体衬底302上方的成核层(nuclearlayer)。成核层具有晶格结构与/或热膨胀系数(thermal expansion coefficient，TEC)适合桥接半导体衬底302与上方层之间的晶格错位与/或TEC错配，例如本揭露所述的GaN层。在一些实施例中，成核层包含氮化铝(AlN)。在一些实施例中，成核层厚度为70到300纳米(nm)。在一些实施例中，省略成核层。
在一或多个实施例中，过渡结构304进一步包含在成核层上方的过渡层。过渡层进一步促使成核层(或半导体衬底302)与沟道层312之间的晶格结构与TEC逐渐变化。在一些实施例中，过渡层包含分级的(graded)氮化铝镓(AlxGa(1-x)N，x为铝-镓组成中的铝含量比例，0<x<1)层。在一些实施例中，分级的氮化铝镓层包含多层，由与半导体衬底302相邻的底层到沟道层312，各自具有降低的比例x。在至少一实施例中，分级的氮化铝镓层具有三层，底层的x比例范围为约0.7-0.9，中间层的范围为约0.4-0.6，以及顶层的范围为约0.15-0.3。在一些实施例中，取代具有不同x比例的多层，分级的氮化铝镓层具有连续梯度的比例x。在一些实施例中，过渡层厚度为约500到1050nm。在一些实施例中，省略过渡层。
在一些实施例中，沟道层312包含一或多个III-V族化合物层。III-V族化合物层的例子包含但不限于GaN、AlGaN、InGaN与InAlGaN。在至少一实施例中，一或多个III-V族化合物层被掺杂。在一或多个实施例中，沟道层312包含交错配置的p掺杂与n掺杂的III-V族化合物层。在至少一实施例中，沟道层312包含p掺杂的GaN层。P掺杂的GaN层中的p型掺质的例子包含但不限于C、Fe、Mg与Zn。在一实施例中，沟道层312厚度为约100到约200nm。
可使用一些现有的成长技术，在半导体衬底302上方形成沟道层312。在一些实施例中，可使用分子束外延(molecular-beam epitaxy，MBE)沟道层312、金属有机化学气相沉积(metalorganic chemical vapor deposition，MOCVD)、混合气相外延(hydride vaporphase epitaxy，HVPE)或其它合适的方式，在过渡结构304上方形成沟道层312。
在图3中，在沟道层312上方形成有源层314。有源层314包含一或多个III-V族化合物层，其组成不同于沟道层312的III-V族化合物层。在一些实施例中，有源层314包含AlN、AlyGa(1-y)N(其中y为铝含量比例，0<y<1)，或其组合。有源层314经配置以沿着沟道层312与有源层314之间的界面引起沟道层314中的二维电子气体(2DEG)318。具有两种不同半导体材料的有源层314与沟道层312之间，形成异接合(heterojunction)。有源层314与沟道层312之间存在带隙不连续。由于压电效应(piezoelectric effect)，有源层314中的电子可掉落到沟道层312中，因而产生高移动性传导电子的薄层，即2DEG318，在与有源层314界面相邻的沟道层312中。2DEG 318中的电子为沟道层312中的电荷载体。
在制造制程过程中，有源层314的表面可被逐渐氧化，造成在其暴露的表面上方形成(天然的)氧化物。所述氧化物包含氧化铝(AlO)、氧化镓(GaO)、氧化氮(NO)、或Al、Ga、N与O的组合。在此实施例中，在移到后续阶段之前，在有源层214的表面上，进行清理步骤与/或退火(annealing)，如图4所示。清理步骤可移除有源层314的表面上的污染。清理步骤还可移除氧化物或减少有源层的表面上吸收的氧化物量。在此实施例中，通过将有源层314的表面暴露于任何合适的湿式清理溶液，进行湿式清理步骤。
在例示实施例中，在退火制程过程中，对于有源层314的表面提供氮环境气氛(nitrogen-based ambient atmosphere)。使用所述退火，通过修补由高密度的供应型点缺陷存在造成的缺陷，以降低有源层314的阻抗，所述缺陷例如氮空缺(nitrogen vacancies，VN)、Ga/N反位(anti-site)，以及其与天然缺陷与受体掺质的复合物，具有相对低的形成能量。已知这些缺陷在GaN中具有供应者作用(donor behavior)，因而限制最大的p型传导。由于植入诱发的破坏产生额外的供应型缺陷，补偿活化孔(activated hole)，因而在离子植入的GaN层中甚至更难以达到高p型传导性。所导入的缺陷在带隙内具有主要的深级(deeplevel)；因此，植入的GaN为高电阻。所述破坏必须被退火以达成植入掺质的电性活化。在一些实施例中，在约350℃到约800℃的温度范围中，完成退火。
在图5(a)中，薄AlN膜319为毯状物，沉积在有源层314的经清理且退火的表面上方。AlN膜319的Al浓度高于有源层314中的Al浓度。在一些实施例中，AlN膜319中的Al浓度与有源层314中的Al浓度比例为约1.1到2.5。在一些实施例中，可使用原子层沉积(atomiclayer deposition，ALD)，用于将薄Al膜319毯状沉积在有源层314上方。然而，这并非本揭露的限制。在其它的实施例中，可使用MBE、化学气相沉积(CVD)、溅镀、电子束蒸镀(E-beamevaporation)、热蒸镀，或其它合适的方式，在有源层314上方形成薄Al膜319。所沉积的AlN膜319厚度足以对于相邻的有源层314提供所需要的Al浓度。在一些实施例中，所沉积的AlN膜319的厚度为约3到20个Al原子的长度。
在一些其它实施例中，薄AlN膜319'沉积在有源层314的经清理且退火的表面的一部分上方，如图5(b)所示。特别地，可选择性进行在有源层314上方沉积薄AlN膜319'，以避免有源层314的所述部分表面保留用于栅极电极。AlN膜319'中的Al浓度高于有源层314中的Al浓度。在一些实施例中，AlN膜319'中的Al浓度与有源层314中的Al浓度比例为约1.1到2.5。由于所述栅极电极附近的高电压与高温可加速高Al浓度层与相邻的有源层314之间键结断裂，因而薄膜319'的部分沉积可对于所制造的装置提供较高的可信赖度。薄AlN膜319'的厚度需求可与AlN膜319实质相同。在一些实施例中，AlN膜319'沉积厚度约为3到21个Al原子的长度。可使用MBE、CVD、溅镀、E束蒸镀、热蒸镀、或其它合适的方式，在有源层314上方形成薄AlN膜319'。
在图6(a)中，在图5(a)的半导体结构上进行高温退火。在退火过程中，来自高浓度区域(例如在薄AlN膜31中)的Al原子逐渐扩散到相邻有源层314且与相邻有源层314反应。在退火之后，Al膜319与有源层314合作形成额外的Al扩散有源层321，其中Al浓度从所述额外的Al扩散有源层321的表面/边界朝向其内部逐渐降低。在一些实施例中，在约500℃到约900℃的温度范围中，完成所述退火。
在一些实施例中，Al的额外扩散从额外的Al扩散有源层321朝向其内部延伸到小于约5nm的深度，并且形成高扩散Al层(例如高Al扩散层322)，如图6(a)所示。因此，在高温退火之前，在高Al扩散层322下方的额外的Al扩散有源层321的大部分仍具有与有源层314实质相同的Al浓度。高Al扩散层322在有源层314与后续步骤中形成在其上的栅极电极的电介层之间的界面自然呈现高带阻障(high band barrier)。在此方式中，高Al扩散层322可降低电子落入界面处的晶格错配缺陷的机会。因此，可显著改进关于界面捕捉密度(Dit)的一些特性，例如线性漏极电流(Idlin)退化、电流崩塌、以及动态开启状态阻抗RON。
在图6(b)中，在图5(b)的半导体结构上进行类似于图6(a)的高温退火。在退火过程中，来自较高浓度区域(例如在薄AlN膜319'中)的Al原子逐渐扩散到相邻的有源层314中并且与相邻的有源层314反应。在退火之后，Al膜319'与有源层314合作形成额外的Al扩散有源层321'，其中Al浓度从额外的Al扩散有源层321'的表面/边界朝向其内部逐渐降低。在一些实施例中，在约500℃到约900℃的温度范围中，完成所述退火。
在一些实施例中，Al的额外扩散从额外的Al扩散有源层321'朝向其内部延伸到小于约5nm的深度，并且形成高Al扩散层322'，如图6(b)所示。因此，在高温退火之前，在高Al扩散层322'外部的额外的Al扩散有源层321'的大部分仍具有与有源层314实质相同的Al浓度。高Al扩散层322'还可改进一些特性，例如界面捕捉密度、Idlin退化、电流崩塌以及动态开启状态阻抗RON。
在讨论III-V HEMT结构的以下形成制程之前，请参阅图9。图9是根据本揭露的一些实施例说明Ga原子与Al原子的X射线能量散射分析(energy dispersive X-ray，EDX)的图表。在EDX分析中，额外的Al扩散有源层321位于约18nm的深度，以及高Al扩散层322的区域或高Al扩散层322'位于约18nm到约24nm的深度。EDX分析显示Al原子的主要峰值位于高Al扩散层322/322'。在高温退火之前，位于比约24nm深度更深的Al原子的平曲线(flatcurve)的Al浓度与有源层314实质相同。在此实施例中，主要峰值的Al原子总量为约26原子％，以及额外的Al扩散有源层321/321'中的平曲线的Al原子总量为约18原子％。在一些实施例中，主要峰值的Al浓度与平曲线的Al浓度的比例为约1.1到2.5。此外，在相同深度，主要峰值的Al浓度低于Ga浓度。在一些实施例中，可通过X射线光电子光谱(X-rayphotoelectron spectroscopy，XPS)分析或任何其它合适的方式，得到相同的结果。
参阅图7(a)，栅极结构362包含形成在栅极电介质320上方的传导栅极电极364。传导栅极电极364可包括任何合适的传导材料，例如掺杂的多晶硅，或是金属，例如钛(Ti)或铝(Al)。栅极电介质320可包括例如氧化铝(Al2O3)、二氧化硅(SiO2)或氮化硅(Si3N4)。栅极电极364将非欧姆触点形成在高Al扩散层322的表面。
在实质相同的方式中，如图7(b)所示，栅极结构362包含将传导栅极电极364形成在栅极电介质320上方。传导栅极电极364可包括任何合适的传导材料，例如掺杂的多晶硅，或是金属，例如钛(Ti)或铝(Al)。栅极电极364将非欧姆触点形成在额外的Al扩散有源层321'的表面。
在图8(a)中，在栅极电极364的两侧上，提供欧姆源极触点372与欧姆漏极触点374。源极与漏极电极372与374形成在高Al扩散层322的表面上方并且与高Al扩散层322的表面接触。在实质相同的方式中，如图8(b)所示，在栅极电极364的两侧上，提供欧姆源极触点372与欧姆漏极触点374。源极与漏极电极372与374形成在高Al扩散层322'的表面上方并且与高Al扩散层322'的表面接触。在此实施例中，栅极电极364与漏极电极374相距约20微米的距离L1，以与门极电极364与漏极电极374的侧的高Al扩散层322'的最近端相距约15微米的距离L2。在一些实施例中，L2/L1比例从约0到约0.8，并且距离L2可代表栅极电极364与漏极电极374之间的距离或是栅极电极364与源极电极372之间的距离。
一般来说，2DEG 318中的电子呈现高载体移动性。通过将电压施加到栅极电极364，而调整此区域的传导性。当施加逆电压(reverse voltage)时，2DEG 318附近的传导带上升到Fermi程度之上，并且2DEG 318的一部分耗尽载体，借以防止电流从源极电极372流到漏极电极374。
图10是根据本揭露的一些实施例说明发明人进行的实验结果的图表，说明在不同深度有或没有高Al扩散层322/322'所制造的III-V HEMT上测量的界面捕捉密度Dit的值。不同深度对应于不同的能级，分别标示为“0.2”、“0.3”、“0.4”、“0.5”、“0.6”与“0.7”eV，其在相同条件下处理，差别在于高Al扩散层322/322'的存在与不存在。较小的能级对应于与额外的Al扩散有源层321/321'的表面相距较浅的深度。将较于具有高Al扩散层322/322'所制造的III-V HEMT(图10中以“正方形”表示的数据点)，没有高Al扩散层322/322'所制造的III-V HEMT(图10中以“菱形”表示的数据点)于那些较浅的深度具有较高的界面捕捉密度Dit。
图11是根据本揭露的一些实施例说明发明人所进行的实验结果的图表，说明线性漏极电流(linear drain current(Idlin))退化为有或没有高Al扩散层所制造的III-VHEMT群组上测量的应力时间(stress time)的函数。发现相较于不具有高Al扩散层322/322'所制造的III-V HEMT，即正方形，具有高Al扩散层322/322'所制造的III-V HEMT具有较少的Idlin退化。当应力时间延长时，差异变得更加显著。因此，可理解具有高Al扩散层322/322'的III-V HEMT至少在可信赖度具有较佳表现。
图12是根据本揭露的实施例说明发明人所进行的实验结果的图表，说明动态最小“开启(on)”阻抗(Rdson)比例为有或没有高Al扩散层322/322'所制造的III-V HEMT群组上测量的应力电压的函数。发现相较于不具有高Al扩散层322/322'所制造的III-V HEMT，即正方形，具有高Al扩散层322/322'所制造的III-V HEMT具有较小的Rdson比例增加。换句话说，具有高Al扩散层322/322'的HEMT的Rdson增加速度小于不具有高Al扩散层322/322'的HEMT的Rdson增加速度。当应力电压增加时，差异变得更加显著。因此，可理解具有高Al扩散层322/322'的III-V HEMT至少在可信赖度具有较佳表现。
本揭露的一些实施例提供一种半导体结构。所述半导体结构包含：沟道层；在所述沟道层上方的有源层，其中所述有源层经配置以沿着所述沟道层与所述有源层之间的界面将二维电子气体(2DEG)形成在所述沟道层中；在所述有源层的顶表面上方的栅极电极；以及在所述有源层的顶表面上方的源极/漏极电极；其中所述有源层包含从所述有源层的所述顶表面到底表面依序配置在其中的第一层与第二层，以及相较于所述第二层，所述第一层具有较高的铝(Al)原子浓度。
前述内容概述一些实施方式的特征，因而所属领域的技术人员可更加理解本揭露的各方面。所属领域的技术人员应理解可轻易使用本揭露作为基础，用于设计或修饰其它制程与结构而实现与本申请案所述的实施例具有相同目的与/或达到相同优点。所属领域的技术人员还应理解此均等架构并不脱离本揭露揭示内容的精神与范围，并且所属领域的技术人员可进行各种变化、取代与替换，而不脱离本揭露的精神与范围。
符号说明
302 半导体衬底
304 过渡结构
312 沟道层
314 有源层
318 二维电子气体
319 薄AlN膜
319' 薄AlN膜
320 栅极电介质
321 额外的Al扩散有源层
321' 额外的Al扩散有源层
322 高Al扩散层
322' 高Al扩散层
362 栅极结构
364 传导栅极电极
372 欧姆源极触点
374 欧姆漏极触点

Claims (1)

1.一种半导体结构，包括：
沟道层；
有源层，位于所述沟道层上方，所述有源层经配置以形成二维电子气体2DEG，所述二维电子气体沿着所述沟道层与所述有源层之间的界面形成在所述沟道层中；
栅极电极，形成在所述有源层的顶表面上方；以及
源极/漏极电极，位于所述有源层的所述顶表面上方；
其中所述有源层包含从所述顶表面到所述有源层的底表面依序堆栈的第一层与一第二层，相较于所述第二层，所述第一层具有较高的铝(Al)原子浓度。
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