CN107436518A - A kind of array base palte, display panel, display device and HUD display systems - Google Patents

A kind of array base palte, display panel, display device and HUD display systems Download PDF

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Publication number
CN107436518A
CN107436518A CN201710772694.4A CN201710772694A CN107436518A CN 107436518 A CN107436518 A CN 107436518A CN 201710772694 A CN201710772694 A CN 201710772694A CN 107436518 A CN107436518 A CN 107436518A
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CN
China
Prior art keywords
insulating barrier
pixels
display
base palte
substrate
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CN201710772694.4A
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Chinese (zh)
Inventor
乐琴
沈柏平
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厦门天马微电子有限公司
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Priority to CN201710772694.4A priority Critical patent/CN107436518A/en
Publication of CN107436518A publication Critical patent/CN107436518A/en

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    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS, OR APPARATUS
    • G02B27/00Optical systems or apparatus not provided for by any of the groups G02B1/00 - G02B26/00, G02B30/00
    • G02B27/01Head-up displays
    • G02B27/0101Head-up displays characterised by optical features
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/133345Insulating layers
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136209Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F2001/133357Planarisation layer

Abstract

The invention provides a kind of array base palte,Display panel,Display device and HUD (Head Up Display,Head-up display) display system,By self-planarization layer to the direction of transistor array in array base palte,Including the first insulating barrier to N insulating barriers,Any non-white subpixel area is corresponded to at least one insulating barrier to carry out hollowing out processing,The insulating barrier or planarization layer that then cut-out is subsequently made are filled,By the quantity for the insulating barrier for reducing non-white sub-pixels corresponding region,With in non-white sub-pixels corresponding region light extraction,Reduce because of situations such as being reflected in different insulative interlayer and cause the situation of light losing,Improve the light transmittance of non-white sub-pixels corresponding region,And then improve the emitting brightness of non-white sub-pixels corresponding region,Improve the display effect of the display device using the array base palte.

Description

A kind of array base palte, display panel, display device and HUD display systems

Technical field

The present invention relates to display technology field, more specifically, is related to a kind of array base palte, display panel, display dress Put and HUD display systems.

Background technology

With the development of science and technology, application of the HUD display systems on automobile is increasingly extensive.HUD display systems now In display picture, the light of display picture is typically emitted by display panel, then throws the light of the display picture On shadow to the display screen set on the windshield, and then it is easy to driver to observe display picture information, wherein, HUD is shown Systematic difference, which avoids driver, to be needed to bow just see the situation of meter information, improves driving safety performance.HUD shows Show that requirement of the system for display picture is higher, thus need display panel that there is higher emitting brightness, can show now White sub-pixels are added in the pixel cell of panel, to lift the emitting brightness of display panel.But add white sub-pixels Display panel emitting brightness when showing white picture is too high, and emitting brightness is relatively low when showing other colored pictures, causes to show Show that effect is not high.

The content of the invention

In view of this, the invention provides a kind of array base palte, display panel, display device and HUD display systems, in battle array By self-planarization layer to the direction of transistor array in row substrate, including the first insulating barrier is to N insulating barriers, to it is at least one absolutely Edge layer corresponds to any non-white subpixel area and carries out hollowing out processing, the insulating barrier or flat that then cut-out is subsequently made Change layer to be filled, the quantity of the insulating barrier by reducing non-white sub-pixels corresponding region, to correspond to area in non-white sub-pixels During the light extraction of domain, reduce because of situations such as being reflected in different insulative interlayer and cause the situation of light losing, improve non- The light transmittance of white sub-pixels corresponding region, and then the emitting brightness of non-white sub-pixels corresponding region is improved, improve Using the display effect of the display device of the array base palte.

To achieve the above object, technical scheme provided by the invention is as follows:

A kind of array base palte, including multiple pixel cells, each pixel cell Corresponding matching have the first color sub- picture Element to M color sub-pixels and a white sub-pixels, the array base palte includes:

Substrate;

Transistor array positioned at substrate side;

And deviate from the planarization layer of the substrate side positioned at the transistor array;

Wherein, it is exhausted to include first from the planarization layer to the direction of the transistor array successively for the transistor array Edge layer to N insulating barriers, at least one insulating barrier correspond to first color sub-pixels into M color sub-pixels any one Or multiple regions is void region, M, N are the integer not less than 1;

Wherein, when first insulating barrier or first insulating barrier have the void region to the i-th insulating barrier, institute State void region to be filled by the planarization layer, i is the positive integer more than 1 and no more than N;

And when N is more than 1 and there is the hollow out in the jth insulating barrier or the jth insulating barrier to kth insulating barrier During region, the void region is filled by the insulating barrier of jth -1, and j is the integer more than 1 and no more than N, and k is more than j and is not more than N integer.

Optionally, it is non-void region that first insulating barrier to N insulating barriers, which correspond to the white sub-pixels,.

Optionally, M 3, wherein, the first color sub-pixels are red sub-pixel, and the second color sub-pixels are the sub- picture of green Element, the 3rd color sub-pixels are blue subpixels.

Optionally, the region that at least one insulating barrier corresponds to the red sub-pixel and green sub-pixels is the vacancy section Domain, and it is non-engrave that first insulating barrier to the N insulating barriers, which correspond to the blue subpixels and the region of white sub-pixels, Dummy section.

Optionally, the transistor array includes:

Active layer positioned at the substrate side;

Deviate from the second insulating barrier of the substrate side positioned at the active layer;

Deviate from the gate metal layer of the substrate side positioned at second insulating barrier;

Deviate from first insulating barrier of the substrate side positioned at the gate metal layer;

And deviate from the source-drain electrode metal level of the substrate side positioned at first insulating barrier;

Wherein, first insulating barrier and/or second insulating barrier correspond to first color sub-pixels to M colors Any one or more regions is the void region in sub-pixel.

Optionally, the transistor array includes:

Gate metal layer positioned at the substrate side;

Deviate from the second insulating barrier of the substrate side positioned at the gate metal layer;

Deviate from the active layer of the substrate side positioned at second insulating barrier;

Deviate from first insulating barrier of the substrate side positioned at the active layer;

And deviate from the source-drain electrode metal level of the substrate side positioned at first insulating barrier;

Wherein, first insulating barrier and/or second insulating barrier correspond to first color sub-pixels to M colors Any one or more regions is the void region in sub-pixel.

Optionally, the array base palte also includes:

Cushion between the substrate and the transistor array.

Optionally, the cushion correspond to first color sub-pixels into M color sub-pixels any one or it is more Individual region is void region.

Optionally, the array base palte also includes:Light shield layer between the substrate and the cushion;

Wherein, the silicon island of the lightproof area of the light shield layer and the active layer is correspondingly arranged.

Accordingly, present invention also offers a kind of display panel, the display panel to include above-mentioned array base palte.

Accordingly, present invention also offers a kind of display device, the display device to include above-mentioned display panel.

Optionally, the display device is liquid crystal display device.

Accordingly, present invention also offers a kind of HUD display systems, the HUD display systems include above-mentioned display and filled Put.

Compared to prior art, technical scheme provided by the invention at least has advantages below:

The invention provides a kind of array base palte, display panel, display device and HUD display systems, array base palte to include Multiple pixel cells, each pixel cell Corresponding matching have the first color sub-pixels to M color sub-pixels and a white Sub-pixel, the array base palte include:Substrate;Transistor array positioned at substrate side;And carried on the back positioned at the transistor array From the planarization layer of the substrate side;Wherein, the transistor array is from the planarization layer to the transistor array Direction includes the first insulating barrier to N insulating barriers successively, and at least one insulating barrier corresponds to first color sub-pixels to M face Any one or more regions is void region in sub-pixels, and M, N are the integer not less than 1;Wherein, described first When insulating barrier or first insulating barrier to the i-th insulating barrier have the void region, the void region is by the planarization Layer filling, i are the positive integer more than 1 and no more than N;And insulated when N is more than 1 and in the jth insulating barrier or the jth When layer to kth insulating barrier has the void region, the void region is filled by the insulating barrier of jth -1, and j is more than 1 and little In N integer, k is the integer more than j and no more than N.

As shown in the above, technical scheme provided by the invention,

By self-planarization layer to the direction of transistor array in array base palte, including the first insulating barrier is to N insulating barriers, Correspond to any non-white subpixel area at least one insulating barrier to carry out hollowing out processing, then cut-out is subsequently made Insulating barrier or planarization layer are filled, the quantity of the insulating barrier by reducing non-white sub-pixels corresponding region, with non-white During the light extraction of sub-pixel corresponding region, reduce because of situations such as being reflected in different insulative interlayer and cause the feelings of light losing Condition, improves the light transmittance of non-white sub-pixels corresponding region, and then improves going out for non-white sub-pixels corresponding region Brightness, improve the display effect of the display device using the array base palte.

Brief description of the drawings

In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this The embodiment of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis The accompanying drawing of offer obtains other accompanying drawings.

A kind of structural representation for pixel cell that Fig. 1 the embodiment of the present application provides;

Fig. 2 is along a kind of sectional drawing in AA ' directions in Fig. 1;

Fig. 3 is the structural representation for another pixel cell that application embodiment provides;

Fig. 4 is along a kind of sectional drawing in BB ' directions in Fig. 3;

Fig. 5 is along another sectional drawing in BB ' directions in Fig. 3;

Fig. 6 is a kind of structural representation for array base palte that the embodiment of the present application provides;

Fig. 7 is the structural representation for another array base palte that the embodiment of the present application provides;

Fig. 8 is a kind of structural representation for display panel that the embodiment of the present application provides;

Fig. 9 is a kind of structural representation for display device that the embodiment of the present application provides.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made Embodiment, belong to the scope of protection of the invention.

As described in background, requirement of the HUD display systems for display picture is higher, thus needs display panel to have There is higher emitting brightness, white sub-pixels can be added in the pixel cell of display panel now, to lift display panel Emitting brightness.But it is too high to add the display panels of the white sub-pixels emitting brightness when showing white picture, and show other Emitting brightness is relatively low during colored picture, causes display effect not high.

Based on this, the embodiment of the present application provides a kind of array base palte, display panel, display device and HUD display systems,

By self-planarization layer to the direction of transistor array in array base palte, including the first insulating barrier is to N insulating barriers, Correspond to any non-white subpixel area at least one insulating barrier to carry out hollowing out processing, then cut-out is subsequently made Insulating barrier or planarization layer are filled, the quantity of the insulating barrier by reducing non-white sub-pixels corresponding region, with non-white During the light extraction of sub-pixel corresponding region, reduce because of situations such as being reflected in different insulative interlayer and cause the feelings of light losing Condition, improves the light transmittance of non-white sub-pixels corresponding region, and then improves going out for non-white sub-pixels corresponding region Brightness, improve the display effect of the display device using the array base palte.To achieve the above object, the embodiment of the present application provides Technical scheme it is as follows, the specific technical scheme provided with reference to Fig. 1 to Fig. 9 the embodiment of the present application is described in detail.

With reference to shown in Fig. 1 and Fig. 2, a kind of structural representation for pixel cell that Fig. 1 provides for the embodiment of the present application, Fig. 2 For a kind of sectional drawing in Fig. 1 along AA ' directions, wherein, array base palte includes multiple pixel cells, each pixel cell pair The first color sub-pixels 11 to M color sub-pixels 1m and a white sub-pixels 20, the array base palte, which should have been matched, to be included:

Substrate 100;

Transistor array (not shown) positioned at the side of substrate 100;

And deviate from the planarization layer 300 of the side of substrate 100 positioned at the transistor array;

Wherein, the transistor array includes the successively from the planarization layer 300 to the direction of the transistor array For one insulating barrier 201 to N insulating barrier 20n, at least one insulating barrier corresponds to first color sub-pixels 11 to M color sub- pictures Any one or more regions is void region 600 in plain 1m, and M, N are the integer not less than 1;

Wherein, there is the hollow out in first insulating barrier 201 or the insulating barrier 20i of first insulating barrier 201 to the i-th During region, the void region 600 is filled by the planarization layer 300, and i is the positive integer more than 1 and no more than N;

And when N is more than 1 and there is the hollow out in the jth insulating barrier or the jth insulating barrier to kth insulating barrier During region, the void region is filled by the insulating barrier of jth -1, and j is the integer more than 1 and no more than N, and k is more than j and is not more than N integer.

In this application, the void region position that any one color sub-pixels are corresponded on different insulative layer is identical.In Fig. 1 Shown, all insulating barriers correspond to the first color sub-pixels 11 to M color sub- pictures in the insulating barrier 20i of the first insulating barrier 201 to the i-th Any one or more regions is void region in plain 1m, and the first color sub-pixels 11 are appointed into M color sub-pixels 1m The void region position anticipated corresponding to a color sub-pixels on the insulating barrier 20i of the first insulating barrier 201 to the i-th is identical.

It should be noted that the array base palte that the embodiment of the present application provides, transistor array include multiple transistors 230th, a plurality of gate line 210 and a plurality of data lines 220, wherein, a plurality of gate line 210 and the intersection restriction of a plurality of data lines 220 are more Individual pixel cell, it is same as the prior art to this, therefore unnecessary repeat is not done.In addition, in Fig. 2 and it is not drawn into where data wire 220 Structure sheaf, this is specifically described in follow-up explanation and diagram.In addition, the void region that the embodiment of the present application provides is located at In the range of data wire and gate line intersect limited area in pixel cell, and the region that gate line and data wire are covered is not done Hollow out processing.

And it is corresponding to liquid crystal display device in array base palte in the array base palte that the embodiment of the present application provides During array base palte, the array base palte also includes the pixel electrode (not shown) connected with transistor, public electrode (not shown) Etc. structure, and mutually insulated is set between pixel electrode and public electrode, wherein, pixel electrode can be located at public electrode with putting down There is separation layer between smoothization layer and between pixel electrode and public electrode, or, public electrode be located at pixel electrode with it is flat There is separation layer between change layer and between pixel electrode and public electrode, or, pixel electrode is located at same layer with public electrode, It is same as the prior art to this, therefore unnecessary repeat is not done.

In addition, the embodiment of the present application is preferable, the first insulating barrier to the i-th insulating barrier is respectively provided with void region, and planarizes Layer fills the void region.Wherein, it is exhausted to N to be more than the first insulating barrier for the transmitance for the planarization layer that the embodiment of the present application provides The transmitance of any one insulating barrier in edge layer, so, after subsequently the first insulating barrier to the i-th insulating barrier is hollowed out, pass through planarization The material of layer is filled the void region, is further ensured that the light transmittance of non-white sub-pixels corresponding region is high.At this Apply in an embodiment, the planarization layer that the application provides is specifically as follows esters organic film, and esters organic film has high light line Transmitance, its specific material the application is not particularly limited.

In the embodiment of the application one, first insulating barrier to the N insulating barriers that the application provides correspond to the white Sub-pixel is non-void region, wherein, all insulating barriers corresponding to white sub-pixels respective regions are not hollowed out into processing, It is excessive and influence the display effect of display device to avoid white picture brightness.In addition, in the application other embodiment, white All insulating barriers corresponding to sub-pixel respective regions can select self-planarization layer partly to be dug successively to the direction of transistor array Sky, it is also an option that all hollow out, also, the quantity of insulating barrier that white sub-pixels respective regions are hollowed out, it is less than non-white Sub-pixels corresponding region is hollowed out the quantity of insulating barrier, this application is not particularly limited, it is necessary to be entered according to practical application The specific design of row.

As shown in the above, the technical scheme that the embodiment of the present application provides, in array base palte by self-planarization layer extremely The direction of transistor array, including the first insulating barrier correspond to any non-white dice picture at least one insulating barrier to N insulating barriers Plain region is carried out hollowing out processing, and the insulating barrier or planarization layer that then cut-out is subsequently made are filled, non-by reducing The quantity of the insulating barrier of white sub-pixels corresponding region, with non-white sub-pixels corresponding region light extraction, reduce due to Situations such as different insulative interlayer reflects and cause the situation of light losing, improve the light of non-white sub-pixels corresponding region Line penetrance, and then the emitting brightness of non-white sub-pixels corresponding region is improved, improve and filled using the display of the array base palte The display effect put.

In the embodiment of the application one, M 3, wherein, the first color sub-pixels are red sub-pixel, the second color sub- picture Element is green sub-pixels, and the 3rd color sub-pixels are blue subpixels.

Optionally, at least one insulating barrier that the embodiment of the present application provides corresponds to the red sub-pixel and green sub-pixels Region be the void region, and first insulating barrier to the N insulating barriers correspond to the blue subpixels and white The region of sub-pixel is non-void region;Wherein, in actual applications, by red sub-pixel and green sub-pixels respective regions pair The default insulating barrier answered is hollowed out, and insulating barrier corresponding to white sub-pixels and blue subpixels respective regions is not processed, and is entered And the light penetration of red subpixel areas corresponding to array base palte and green subpixel areas is improved, improve red and green Emitting brightness;Meanwhile ensure array base palte correspond to blue subpixel areas transmitance it is relatively low, avoid display device display picture Occurs white point partially blue situation during face.

It should be noted that the application correspondingly presets insulating barrier for which kind of color sub-pixels respective regions hollows out situation not Concrete restriction is done, can be by red sub-pixel, green sub-pixels and blue subpixels respective area in the application other embodiment Insulating barrier is preset corresponding to domain and hollows out processing;Or can be by corresponding to red sub-pixel and blue subpixels respective regions Default insulating barrier hollows out processing, and does not hollow out processing to insulating barrier corresponding to green sub-pixels respective regions;Or by green Insulating barrier is preset corresponding to sub-pixel and blue subpixels respective regions and hollows out processing, and it is corresponding to red sub-pixel respective regions Insulating barrier do not hollow out processing etc., to this needs according to material, structure used by the preparation of display device in practical application The design parameters such as layer carry out specific design.Wherein, the embodiment of the present application be specially to default insulating barrier described above any layer not It is limited, it is necessary to carry out specific design according to practical application.

In the array base palte that the embodiment of the application one, the application provide, it can be using LTPS (Low Temperature Poly-silicon, low temperature polycrystalline silicon) array base palte that is prepared of technology.With reference to specific accompanying drawing pair The array base palte that the embodiment of the present application carries is described in detail.It should be noted that below array substrate description with The explanation carried out exemplified by the planar structure of the pixel cell of array base palte shown in Fig. 3, simply in BB ' directions shown in accompanying drawings below Section structure is different, wherein, Fig. 3 is the structural representation for another pixel cell that the embodiment of the present application provides.

In the embodiment of the application one, the array base palte for using LTPS technology to prepare of the application offer can be top gate type Array base palte, be that array base palte includes substrate 100, institute along a kind of sectional drawing in BB ' directions in Fig. 3 with reference to shown in figure 4 Stating transistor array includes:

Active layer positioned at the side of substrate 100, wherein, silicon island 231 of the active layer formed with transistor 230;

Deviate from the second insulating barrier 202 of the side of substrate 100 positioned at the active layer;

Deviate from the gate metal layer of the side of substrate 100 positioned at second insulating barrier 202, wherein, gate metal layer Grid 232 formed with transistor 230, and, formed with grid line 210;

Deviate from first insulating barrier 201 of the side of substrate 100 positioned at the gate metal layer;

And deviate from the source-drain electrode metal level of the side of substrate 100 positioned at first insulating barrier 201, wherein, source electrode gold Belong to source electrode 233 and drain electrode 234 of the layer formed with transistor 230, and source electrode 233 and drain electrode 234 are by forming in the second insulating barrier 202 and the first via on insulating barrier 201 connected with silicon island 231;Specifically, silicon island includes source area, drain region and raceway groove, Source area is contacted with source electrode by via, and drain region is contacted with draining by via, and the light shield layer subsequently prepared enters to raceway groove Row blocks;

Wherein, first insulating barrier 201 and/or corresponding first color sub-pixels 11 of second insulating barrier 202 Into M color sub-pixels 1m, any one or more regions is the void region.

That is, first insulating barrier 201 that the embodiment of the present application provides corresponds to first color sub-pixels 11 to M face Any one or more regions is the void region in sub-pixels 1m;Or first insulating barrier 201 and described Corresponding first color sub-pixels 11 of two insulating barriers 202 region any one or more into M color sub-pixels 1m is equal For the void region;Or second insulating barrier 202 corresponds to first color sub-pixels 11 to M color sub-pixels Any one or more regions is the void region in 1m.

Or in the embodiment of the application one, the array base palte that what the application provided use LTPS technology to prepare can be for The array base palte of bottom gate type, it is to include base along another sectional drawing in BB ' directions, array base palte in Fig. 3 with reference to shown in figure 5 Plate 100, the transistor array include:

Gate metal layer positioned at the side of substrate 100, wherein, grid of the gate metal layer formed with transistor 230 232, and formed with gate line 210;

Deviate from the second insulating barrier 202 of the side of substrate 100 positioned at the gate metal layer;

Deviate from the active layer of the side of substrate 100 positioned at second insulating barrier 202, wherein, active layer is formed with crystalline substance The silicon island 231 of body pipe 230;

Deviate from first insulating barrier 201 of the side of base 100 positioned at the active layer;

And deviate from the source-drain electrode metal level of the side of substrate 100 positioned at first insulating barrier 201, wherein, source electrode gold Belong to source electrode 233 and drain electrode 234 of the layer formed with transistor 230, and source electrode 233 and drain electrode 234 are by forming in the first insulating barrier Via on 201 connects with silicon island 231;Specifically, silicon island includes source area, drain region and raceway groove, source area leads to source electrode Via is contacted, and drain region is contacted with draining by via, and the light shield layer subsequently prepared blocks to raceway groove;

Wherein, first insulating barrier 201 and/or corresponding first color sub-pixels 11 of second insulating barrier 202 Into M color sub-pixels 1m, any one or more regions is the void region.

That is, first insulating barrier 201 that the embodiment of the present application provides corresponds to first color sub-pixels 11 to M face Any one or more regions is the void region in sub-pixels 1m;Or first insulating barrier 201 and described Corresponding first color sub-pixels 11 of two insulating barriers 202 region any one or more into M color sub-pixels 1m is equal For the void region;Or second insulating barrier 202 corresponds to first color sub-pixels 11 to M color sub-pixels Any one or more regions is the void region in 1m.

Further, when the embodiment of the present application prepares array base palte using LTPS technology, the array base of the application preparation Plate also includes a cushion, avoids when substrate is glass, and the metal ion in glass influences the preparation of transistor array, ginseng Examine shown in Fig. 6, a kind of structural representation of the array base palte provided for the embodiment of the present application, wherein, the array base palte also wraps Include:

Cushion 400 between the substrate 100 and the transistor array.

Further, the array base palte that the embodiment of the present application provides, its cushion 400 can equally be hollowed out, and then Further improve the emitting brightness of other colors.Wherein, described in corresponding in first insulating barrier and/or second insulating barrier When the first color sub-pixels region any one or more into M color sub-pixels is the void region, the buffering Corresponding first color sub-pixels of the layer region any one or more into M color sub-pixels is void region.Wherein, When the first insulating barrier and/or the second insulating barrier have void region, the cushion, the first insulating barrier and second insulation The void region position correspondence that layer has.

And when the embodiment of the present application prepares array base palte using LTPS technology, array base palte prepared by the application is also Include a light shield layer, shading treatment is carried out to silicon island by light shield layer, avoids light from influenceing the performance of transistor, with reference to figure 7 Shown, the structural representation of another array base palte provided for the embodiment of the present application, the array base palte also includes:Positioned at institute State the light shield layer 500 between substrate 100 and the cushion 400;

Wherein, the lightproof area of the light shield layer 500 is correspondingly arranged with the silicon island 231 of the active layer, i.e. lightproof area At least cover the raceway groove region of silicon island.

It should be noted that the array base palte that the application provides, it can not only use the LTPS technology of above-mentioned offer Prepare, the technologies such as a-Si can also be used to be prepared, this embodiment of the present application is not particularly limited, it is necessary to be answered according to actual With carrying out specific design.In addition, the array base palte that the embodiment of the present application provides can be the array included by liquid crystal display device Substrate, wherein, array base palte also includes public electrode and pixel electrode, and public electrode and pixel electrode are located at planarization layer Away from substrate side and mutually insulated;Wherein, the application does not do for the hierarchical relationship of public electrode and pixel electrode and had Body is limited, it is necessary to carry out specific design according to practical application.

Accordingly, the embodiment of the present application additionally provides a kind of display panel, and the display panel includes above-mentioned any one reality The array base palte of example offer is provided.With reference to shown in figure 8, a kind of structural representation of the display panel provided for the embodiment of the present application, Wherein, display panel can be included with liquid crystal display panel, liquid crystal display panel:

The array base palte 1000 that above-mentioned any one embodiment provides;

The color membrane substrates 2000 being oppositely arranged with array base palte 1000;

And it is arranged at the liquid crystal layer 3000 between array base palte 1000 and color membrane substrates 2000.

It should be noted that the embodiment of the present application is not particularly limited for the type of display panel, it can be liquid crystal It display panel, can also be other types display panel, specific design is carried out according to practical application to this needs.

Accordingly, the embodiment of the present application additionally provides a kind of display device, and the display device includes above-mentioned any one reality The display panel of example offer is provided.With reference to shown in figure 9, a kind of structural representation of the display device provided for the embodiment of the present application, Wherein, display device is liquid crystal display device, and liquid crystal display device includes:

Above-mentioned any one embodiment provides display panel 4000;

And the backlight source module 5000 of light source is provided for display panel 4000.

It should be noted that the display device that the embodiment of the present application provides can be liquid crystal display device, in this Shen Please be in other embodiment, display device can also be other types display device, and this application is not particularly limited.

Accordingly, the embodiment of the present application additionally provides a kind of HUD display systems, and the HUD display systems include above-mentioned The display device that an embodiment of anticipating provides.

The embodiment of the present application provides a kind of array base palte, display panel, display device and HUD display systems, array base Plate includes multiple pixel cells, each pixel cell Corresponding matching have the first color sub-pixels to M color sub-pixels and One white sub-pixels, the array base palte include:Substrate;Transistor array positioned at substrate side;And positioned at the transistor Array deviates from the planarization layer of the substrate side;Wherein, the transistor array is from the planarization layer to the transistor The direction of array corresponds to described first including the first insulating barrier to N insulating barriers, first insulating barrier to the i-th insulating barrier successively The color sub-pixels region any one or more into M color sub-pixels is void region, and the void region is by institute Planarization layer filling is stated, M, N are the integer not less than 1, and i is the positive integer no more than N.

As shown in the above, the technical scheme that the embodiment of the present application provides, in array base palte by self-planarization layer extremely The direction of transistor array, including the first insulating barrier correspond to any non-white dice picture at least one insulating barrier to N insulating barriers Plain region is carried out hollowing out processing, and the insulating barrier or planarization layer that then cut-out is subsequently made are filled, non-by reducing The quantity of the insulating barrier of white sub-pixels corresponding region, with non-white sub-pixels corresponding region light extraction, reduce due to Situations such as different insulative interlayer reflects and cause the situation of light losing, improve the light of non-white sub-pixels corresponding region Line penetrance, and then the emitting brightness of non-white sub-pixels corresponding region is improved, improve and filled using the display of the array base palte The display effect put.

The foregoing description of the disclosed embodiments, professional and technical personnel in the field are enable to realize or using the present invention. A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one The most wide scope caused.

Claims (13)

1. a kind of array base palte, including multiple pixel cells, each pixel cell Corresponding matching has the first color sub-pixels To M color sub-pixels and a white sub-pixels, it is characterised in that the array base palte includes:
Substrate;
Transistor array positioned at the substrate side;
And deviate from the planarization layer of the substrate side positioned at the transistor array;
Wherein, the transistor array includes the first insulating barrier successively from the planarization layer to the direction of the transistor array To N insulating barriers, at least one insulating barrier correspond to first color sub-pixels into M color sub-pixels any one or it is more Individual region is void region, and M, N are the integer not less than 1;
Wherein, it is described to engrave when first insulating barrier or first insulating barrier have the void region to the i-th insulating barrier Dummy section is filled by the planarization layer, and i is the positive integer more than 1 and no more than N;
And when N is more than 1 and there is the void region in the jth insulating barrier or the jth insulating barrier to kth insulating barrier When, the void region is filled by the insulating barrier of jth -1, and j is the integer more than 1 and no more than N, and k is more than j and no more than N's Integer.
2. array base palte according to claim 1, it is characterised in that first insulating barrier to N insulating barriers corresponds to institute It is non-void region to state white sub-pixels.
3. array base palte according to claim 1, it is characterised in that M 3, wherein, the first color sub-pixels are red son Pixel, the second color sub-pixels are green sub-pixels, and the 3rd color sub-pixels are blue subpixels.
4. array base palte according to claim 3, it is characterised in that at least one insulating barrier corresponds to the red sub-pixel Region with green sub-pixels is the void region, and first insulating barrier to the N insulating barriers correspond to the blueness The region of sub-pixel and white sub-pixels is non-void region.
5. array base palte according to claim 1, it is characterised in that the transistor array includes:
Active layer positioned at the substrate side;
Deviate from the second insulating barrier of the substrate side positioned at the active layer;
Deviate from the gate metal layer of the substrate side positioned at second insulating barrier;
Deviate from first insulating barrier of the substrate side positioned at the gate metal layer;
And deviate from the source-drain electrode metal level of the substrate side positioned at first insulating barrier;
Wherein, first insulating barrier and/or second insulating barrier correspond to first color sub-pixels to M color sub- pictures Any one or more regions is the void region in element.
6. array base palte according to claim 1, it is characterised in that the transistor array includes:
Gate metal layer positioned at the substrate side;
Deviate from the second insulating barrier of the substrate side positioned at the gate metal layer;
Deviate from the active layer of the substrate side positioned at second insulating barrier;
Deviate from first insulating barrier of the substrate side positioned at the active layer;
And deviate from the source-drain electrode metal level of the substrate side positioned at first insulating barrier;
Wherein, first insulating barrier and/or second insulating barrier correspond to first color sub-pixels to M color sub- pictures Any one or more regions is the void region in element.
7. the array base palte according to claim 5 or 6, it is characterised in that the array base palte also includes:
Cushion between the substrate and the transistor array.
8. array base palte according to claim 7, it is characterised in that the cushion corresponds to first color sub-pixels Into M color sub-pixels, any one or more regions is void region.
9. array base palte according to claim 7, it is characterised in that the array base palte also includes:Positioned at the substrate With the light shield layer between the cushion;
Wherein, the silicon island of the lightproof area of the light shield layer and the active layer is correspondingly arranged.
10. a kind of display panel, it is characterised in that the display panel includes the array described in claim 1~9 any one Substrate.
11. a kind of display device, it is characterised in that the display device includes the display panel described in claim 10.
12. display device according to claim 11, it is characterised in that the display device is liquid crystal display device.
13. a kind of HUD display systems, it is characterised in that the HUD display systems include the display described in claim 11 or 12 Device.
CN201710772694.4A 2017-08-31 2017-08-31 A kind of array base palte, display panel, display device and HUD display systems CN107436518A (en)

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CN1641450A (en) * 2004-01-17 2005-07-20 统宝光电股份有限公司 Liquid crystal display device, and its manufacturing method anbd transistor array substrate and manufacturing method
CN103984169A (en) * 2013-02-08 2014-08-13 群创光电股份有限公司 Liquid crystal display device
TWM487953U (en) * 2014-01-17 2014-10-11 Shern Dar Ind Corp Auto return apparatus improvement
CN105182581A (en) * 2015-08-27 2015-12-23 深圳市华星光电技术有限公司 Pixel structure and liquid crystal display panel
CN106324923A (en) * 2016-10-18 2017-01-11 上海中航光电子有限公司 Array substrate and display panel

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1641450A (en) * 2004-01-17 2005-07-20 统宝光电股份有限公司 Liquid crystal display device, and its manufacturing method anbd transistor array substrate and manufacturing method
CN103984169A (en) * 2013-02-08 2014-08-13 群创光电股份有限公司 Liquid crystal display device
TWM487953U (en) * 2014-01-17 2014-10-11 Shern Dar Ind Corp Auto return apparatus improvement
CN105182581A (en) * 2015-08-27 2015-12-23 深圳市华星光电技术有限公司 Pixel structure and liquid crystal display panel
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