CN107369683A - The power device of electromagnetism interference - Google Patents

The power device of electromagnetism interference Download PDF

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Publication number
CN107369683A
CN107369683A CN201710502967.3A CN201710502967A CN107369683A CN 107369683 A CN107369683 A CN 107369683A CN 201710502967 A CN201710502967 A CN 201710502967A CN 107369683 A CN107369683 A CN 107369683A
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CN
China
Prior art keywords
grid
conductivity type
power device
electromagnetism interference
junction
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Granted
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CN201710502967.3A
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Chinese (zh)
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CN107369683B (en
Inventor
曹峰
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Suzhou Meitian Network Technology Co Ltd
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Suzhou Meitian Network Technology Co Ltd
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Priority to CN201710502967.3A priority Critical patent/CN107369683B/en
Priority to PCT/CN2017/108955 priority patent/WO2019000762A1/en
Publication of CN107369683A publication Critical patent/CN107369683A/en
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Publication of CN107369683B publication Critical patent/CN107369683B/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors

Abstract

A kind of power device of electromagnetism interference of disclosure of the invention includes:The substrate of first conductivity type, its bottom are configured with the first drain electrode of MOS power devices, and the substrate upper end is configured with epitaxial layer;The raceway groove of second conductivity type;The body area of second conductivity type, is provided with the first source electrode in it, and the upper end between the adjacent body area is configured with first grid;Wherein, two the first individual channels and the second individual channel not covered by the body area in the raceway groove at least be present, the first individual channel top is configured with metal oxide semiconductor field effect tube, epitaxial layer upper end insulation configuration has first resistor, second drain electrode of the metal oxide semiconductor field effect tube and second grid are connected with the first grid simultaneously, and the second source electrode of the metal oxide semiconductor field effect tube is connect altogether by the first resistor and first source electrode.The present invention solves power device easily by the technical problem of electromagnetic interference.

Description

The power device of electromagnetism interference
Technical field
The invention belongs to technical field of semiconductors, more particularly to a kind of power device of electromagnetism interference.
Background technology
Power device includes Power IC and power discrete device, and power discrete device then mainly includes power MOSFET, big The semiconductor devices such as power transistor and IGBT, power device are almost used for all electronics manufacturings, the product bag applied Include notebook, PC, server, display and the various peripheral hardwares of computer realm;The mobile phone of network communication field, phone and Other various terminals and local side apparatus;Traditional black and white household electrical appliances of consumer electronics field and various digital products;In Industry Control class Industrial PC, all kinds of instrument and meters and all kinds of control devices etc..In addition to the normal operation for ensureing these equipment, power device Effective energy-conserving action can also be played.Due to the continuous improvement of demand and the efficiency requirement of electronic product, Chinese power device Market is always maintained at faster development speed.
Power semiconductor is the important component of Power Electronic Circuit, and a preferable power semiconductor should The static and dynamic c haracteristics having had, it can bear high voltage in cut-off state and leakage current is small, in conducting state, energy High current and very low tube voltage drop are flowed through, when switching conversion, there is the short open and close time;On-state loss, off-state are lost and opened Pass loss is intended to small.High di/dt and du/dt can be born simultaneously and with full control function.
Existing power device has the switching characteristic being exceedingly fast, and realizes higher power conversion efficiency, but in power device Disconnect and closing course in, grid is also easy to produce concussion, causes that power device on off state is instantaneously uncontrollable, and power device easily misses Action, generates very big electromagnetic interference, reduces the reliability of power device.
The content of the invention
For above-mentioned technical problem, a kind of power device of electromagnetism interference is proposed in the present invention, is set in first grid Shunt circuit is equipped with, when the gate voltage concussion of power device is excessive, voltage avoids gate voltage from shaking by shunt circuit water conservancy diversion Swing, solve power device easily by the technical problem of electromagnetic interference.
In order to realize according to object of the present invention and further advantage, there is provided a kind of power device of electromagnetism interference Part, including:
The substrate of first conductivity type, its bottom are configured with the first drain electrode of MOS power devices, and the substrate upper end is configured with The epitaxial layer of first conductivity type;
The raceway groove of second conductivity type, its interval are configured in the epitaxial layer;
The body area of second conductivity type, it is configured in the raceway groove and epitaxial layer top, wherein, the body area is at least covered in The upper end of two adjacent raceway grooves forms adjacent body area, and the first source electrode of the first conductivity type is configured with the body area, described Upper end between adjacent body area is configured with first grid;
Wherein, two the first individual channels and the second independent ditch not covered by the body area in the raceway groove at least be present Road, the first individual channel top are configured with Metal-Oxide Semiconductor FET, epitaxial layer upper end insulation configuration Have a first resistor, the second drain electrode of the Metal-Oxide Semiconductor FET and second grid and meanwhile with the first grid Pole connects, and the second source electrode of the Metal-Oxide Semiconductor FET passes through the first resistor and first source electrode Connect altogether.
Preferably, the epitaxial layer upper end also insulation configuration has second resistance, and it is conductively connected with the first grid.
Preferably, the second individual channel top is configured with PN junction, the second resistance by the PN junction with it is described First grid is conductively connected, and the second resistance is connected with the anode of the PN junction, the negative electrode of the PN junction and the first grid Pole connects.
Preferably, the second drain electrode of the Metal-Oxide Semiconductor FET and second grid are connected to the PN The connects end altogether of knot and the first grid.
Preferably, the top interval of first individual channel is configured with source region and the drain region of the first conductivity type, the source Area upper end is provided with second source electrode, and the drain region upper end is provided with second drain electrode, and the source region and drain region upper end are matched somebody with somebody It is equipped with the second grid.
Preferably, the top of second individual channel is configured with the base of the first conductivity type, and its top is configured with second Firstth area of conductivity type, the base upper end are configured with the secondth area of the first conductivity type.
Preferably, first conductivity type is N-type, and second conductivity type is p-type, and firstth area is the PN junction Anode, secondth area are the negative electrode of the PN junction.
Preferably, first conductivity type is p-type, and second conductivity type is N-type, and secondth area is the PN junction Anode, firstth area are the negative electrode of the PN junction.
Preferably, the Metal-Oxide Semiconductor FET is at least 2, each Metal-Oxide Semiconductor FET separate configurations in first individual channel, each Metal-Oxide Semiconductor FET it is each Individual second grid is in parallel, in parallel, each second sources connected in parallel of each second drain electrode.
Preferably, the first grid is to divide grid grid or full grid grid.
The present invention comprises at least following beneficial effect:
1st, the power device of a kind of electromagnetism interference proposed by the present invention, faster, contact capacity is bigger for switching speed;
2nd, anti-electromagnetic interference capability is strong, and the reliability of power device is higher;
3rd, the switching loss of power device is lower.
Further advantage, target and the feature of the present invention embodies part by following explanation, and part will also be by this The research and practice of invention and be understood by the person skilled in the art.
Brief description of the drawings
Fig. 1 is the sectional view of the power device of electromagnetism interference;
Fig. 2 is the top view of the power device of electromagnetism interference;
Fig. 3 is the close-up schematic view in Fig. 2.
Embodiment
The present invention is described in further detail below in conjunction with the accompanying drawings, to make those skilled in the art with reference to specification text Word can be implemented according to this.
It should be appreciated that such as " having ", "comprising" and " comprising " term used in the present invention do not allot one or The presence or addition of a number of other elements or its combination.
Meanwhile to clearly demonstrate the embodiment of the present invention, listed schematic diagram in Figure of description, it is exaggerated this The described layer of invention and the thickness in region, and listed feature size does not represent actual size;Figure of description be it is schematical, It should not limit the scope of the present invention.Listed embodiment should not be limited only to the specific shape in region shown in Figure of description in specification Shape, but including resulting shape deviation etc. as caused by manufacture, generally there is bending or mellow and full as etched obtained curve The characteristics of, represented in embodiments of the present invention with rectangle.
As Figure 1-3, the power device of electromagnetism interference proposed by the present invention, including:
The substrate 700 of first conductivity type, its bottom are configured with the first drain electrode of MOS power devices, the upper end of substrate 700 The epitaxial layer 200 of the first conductivity type is configured with, the material of substrate epitaxial layer 200 is preferably silicon, but is not limited to silicon;
The raceway groove 100 of second conductivity type, its interval is configured in the epitaxial layer, as shown in figure 1, only showing in the present embodiment 5 raceway grooves 100 are gone out, its quantity can determine according to specific product design requirement, the upper end of raceway groove 100 and epitaxial layer 200 Flush;
The body area 300 of second conductivity type, it is configured in the raceway groove 100 and the top of epitaxial layer 200, specifically, second leads Electricity Xing Ti areas 300 cover the top for being arranged on several raceway grooves 100 so that the body area 300 of final second conductivity type and extension The upper end of layer 200 flushes, wherein, the upper end that the body area 300 is at least covered in two adjacent raceway grooves 100 forms adjacent body Area, is configured with the first source electrode 310 of the first conductivity type in the body area, and the upper end between the adjacent body area is configured with the first grid Pole 500, so as to constitute MOS power devices;
Wherein, two Hes of the first individual channel 110 not covered by the body area 300 in the raceway groove 100 at least be present Second individual channel 120, the top of the first individual channel 110 is configured with Metal-Oxide Semiconductor FET, described outer Prolonging the upper end insulation configuration of layer 200 has first resistor 610, the second 115 Hes of drain electrode of the Metal-Oxide Semiconductor FET Second grid 114 is connected with the first grid 500 simultaneously, the second source electrode of the Metal-Oxide Semiconductor FET 113 are connect altogether by the first resistor 610 and first source electrode 310.All it is to pass through gold between each pole and between resistance Belong to line connection, be prior art, do not described again in the present embodiment.
When power device turns off, there is concussion voltage in first grid, when shaking overtension, passes through metal-oxide Thing semiconductor field water conservancy diversion is effectively slowed down by first resistor to the first source electrode and absorbs high voltage, avoid gate voltage Concussion, when the voltage of first grid is in normal voltage value, Metal-Oxide Semiconductor FET cut-off, electric current will not lead to Metal-Oxide Semiconductor FET water conservancy diversion is crossed, is also consumed without going past first resistor, so as to reduce the damage of power device Consumption, the contact capacity of power device is improved, gate voltage concussion is effectively eliminated, it is achieved thereby that superpower electromagnetism interference energy Power, the reliability of power device is improved, faster, contact capacity is higher for switching speed.
In a kind of embodiment, the first grid 500 is all a point grid grid, that is, first grid be independently arranged at it is each Body area upper end, it is not connected to two adjacent body areas.
In a kind of embodiment, one layer of insulation film 400 is formed on the upper surface of power device, on insulation film 400 Form one layer of conducting film, etching conductive film and insulation film, remaining conducting film turns into the first grid, second grid and the One resistance, while second resistance 620 is also formed with conducting film, the second resistance 620 connects with the first grid 500 Connect.
In a kind of embodiment, the top of the second individual channel 120 is configured with PN junction, and the second resistance 620 passes through institute PN junction is stated to be conductively connected with the first grid 500, wherein, the second resistance 620 is connected with the anode of the PN junction, described The negative electrode of PN junction is connected with the first grid 500, and the other end of second resistance is connected with first grid control terminal.
In a kind of embodiment, the second drain electrode 115 of the Metal-Oxide Semiconductor FET and second grid 114 It is connected to the connects end altogether of the PN junction negative electrode and the first grid 500.
In a kind of embodiment, the top interval of first individual channel 110 is configured with the He of source region 112 of the first conductivity type Drain region 111, as shown in Figures 2 and 3, the upper end of source region 112 are provided with second source electrode 113, and the upper end of drain region 111 is set There is second drain electrode 115, the source region and drain region upper end are configured with the second grid 114.
In a kind of embodiment, the top of second individual channel 120 is configured with the base 121 of the first conductivity type, thereon Portion is configured with the first area 122 of the second conductivity type, and the upper end of base 121 is configured with the second area 123 of the first conductivity type.
In a kind of embodiment, first conductivity type is N-type, and second conductivity type is p-type, and firstth area is described The anode of PN junction, secondth area are the negative electrode of the PN junction.
In a kind of embodiment, first conductivity type is p-type, and second conductivity type is N-type, and secondth area is described The anode of PN junction, firstth area are the negative electrode of the PN junction.
In a kind of embodiment, the Metal-Oxide Semiconductor FET is at least 2, each metal-oxide Semiconductor field separate configurations are in first individual channel, each Metal-Oxide Semiconductor field-effect Each second grid of pipe is in parallel, in parallel, each second sources connected in parallel of each second drain electrode, to strengthen first grid overvoltage Water conservancy diversion effect, further reduce gate voltage concussion, the Interruption performance of firm power device.
From the above mentioned, the power device of a kind of electromagnetism interference proposed by the present invention, faster, contact capacity is more for switching speed Greatly, anti-electromagnetic interference capability is strong, and the reliability of power device is higher, meanwhile, the switching loss of power device is lower.
Although embodiment of the present invention is disclosed as above, it is not restricted in specification and embodiment listed With it can be applied to various suitable the field of the invention completely, can be easily for those skilled in the art Other modification is realized, therefore under the universal limited without departing substantially from claim and equivalency range, it is of the invention and unlimited In specific details and shown here as the legend with description.

Claims (10)

  1. A kind of 1. power device of electromagnetism interference, it is characterised in that including:
    The substrate of first conductivity type, its bottom are configured with the first drain electrode of MOS power devices, and the substrate upper end is configured with first The epitaxial layer of conductivity type;
    The raceway groove of second conductivity type, its interval are configured in the epitaxial layer;
    The body area of second conductivity type, it is configured in the raceway groove and epitaxial layer top, wherein, the body area is at least covered in two The upper end of the adjacent raceway groove forms adjacent body area, and the first source electrode of the first conductivity type is configured with the body area, described adjacent Upper end between body area is configured with first grid;
    Wherein, two the first individual channels and the second individual channel not covered by the body area in the raceway groove at least be present, The first individual channel top is configured with Metal-Oxide Semiconductor FET, and epitaxial layer upper end insulation configuration has First resistor, the Metal-Oxide Semiconductor FET second drain electrode and second grid at the same with the first grid Connection, the second source electrode of the Metal-Oxide Semiconductor FET are total to by the first resistor and first source electrode Connect.
  2. 2. the power device of electromagnetism interference as claimed in claim 1, it is characterised in that the epitaxial layer upper end, which is also insulated, matches somebody with somebody Second resistance is equipped with, it is conductively connected with the first grid.
  3. 3. the power device of electromagnetism interference as claimed in claim 2, it is characterised in that match somebody with somebody on the second individual channel top PN junction is equipped with, the second resistance is conductively connected by the PN junction and the first grid, the second resistance and the PN The anode connection of knot, the negative electrode of the PN junction are connected with the first grid.
  4. 4. the power device of electromagnetism interference as claimed in claim 3, it is characterised in that the Metal-Oxide Semiconductor Second drain electrode of FET and second grid are connected to the connects end altogether of the PN junction and the first grid.
  5. 5. the power device of electromagnetism interference as claimed in claim 4, it is characterised in that the top of first individual channel Interval is configured with source region and the drain region of the first conductivity type, and the source region upper end is provided with second source electrode, the drain region upper end Second drain electrode is provided with, the source region and drain region upper end are configured with the second grid.
  6. 6. the power device of electromagnetism interference as claimed in claim 5, it is characterised in that the top of second individual channel The base of the first conductivity type is configured with, its top is configured with the firstth area of the second conductivity type, and the base upper end is configured with first Secondth area of conductivity type.
  7. 7. the power device of electromagnetism interference as claimed in claim 6, it is characterised in that first conductivity type is N-type, institute It is p-type to state the second conductivity type, and firstth area is the anode of the PN junction, and secondth area is the negative electrode of the PN junction.
  8. 8. the power device of electromagnetism interference as claimed in claim 6, it is characterised in that first conductivity type is p-type, institute It is N-type to state the second conductivity type, and secondth area is the anode of the PN junction, and firstth area is the negative electrode of the PN junction.
  9. 9. the power device of electromagnetism interference as claimed in claim 7 or 8, it is characterised in that the metal-oxide is partly led Body FET is at least 2, and each Metal-Oxide Semiconductor FET separate configurations is in first independence In raceway groove, each second grid of each Metal-Oxide Semiconductor FET is in parallel, each second drain electrode is in parallel, each Individual second sources connected in parallel.
  10. 10. the power device of electromagnetism interference as claimed in claim 1, it is characterised in that the first grid is to divide grid grid Pole or full grid grid.
CN201710502967.3A 2017-06-27 2017-06-27 Anti-electromagnetic interference power device Active CN107369683B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201710502967.3A CN107369683B (en) 2017-06-27 2017-06-27 Anti-electromagnetic interference power device
PCT/CN2017/108955 WO2019000762A1 (en) 2017-06-27 2017-11-01 Electromagnetic interference-resistant power component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710502967.3A CN107369683B (en) 2017-06-27 2017-06-27 Anti-electromagnetic interference power device

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CN107369683A true CN107369683A (en) 2017-11-21
CN107369683B CN107369683B (en) 2020-06-23

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WO (1) WO2019000762A1 (en)

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CN101019319A (en) * 2004-08-03 2007-08-15 飞思卡尔半导体公司 A semiconductor switch arrangement and an electronic device
CN103151348A (en) * 2011-12-06 2013-06-12 英飞凌科技奥地利有限公司 Integrated circuit including a power transistor and an auxiliary transistor
TW201411809A (en) * 2012-09-05 2014-03-16 Silicongear Corp Power MOSFET element
US20150091641A1 (en) * 2013-09-30 2015-04-02 Infineon Technologies Austria Ag Integrated Circuit with a Power Transistor and a Driver Circuit Integrated in a Common Semiconductor Body
CN105161491A (en) * 2015-09-22 2015-12-16 苏州东微半导体有限公司 Integrated gate driver transistor (IGDT) power device and manufacturing method thereof
WO2016173394A1 (en) * 2015-04-30 2016-11-03 苏州东微半导体有限公司 Semiconductor super-junction power device and manufacturing method therefor

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KR101418396B1 (en) * 2007-11-19 2014-07-10 페어차일드코리아반도체 주식회사 Power semiconductor device
US8614480B2 (en) * 2011-07-05 2013-12-24 Texas Instruments Incorporated Power MOSFET with integrated gate resistor and diode-connected MOSFET
US9425304B2 (en) * 2014-08-21 2016-08-23 Vishay-Siliconix Transistor structure with improved unclamped inductive switching immunity
CN104952928A (en) * 2015-04-30 2015-09-30 苏州东微半导体有限公司 Gate-drain capacitance slow change super-junction power device and manufacturing method thereof
CN107256865B (en) * 2017-06-27 2020-06-19 苏州美天网络科技有限公司 Low-loss semiconductor power device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5304802A (en) * 1992-01-06 1994-04-19 Fuji Electric Co., Ltd. Semiconductor device including overvoltage protective circuit
CN101019319A (en) * 2004-08-03 2007-08-15 飞思卡尔半导体公司 A semiconductor switch arrangement and an electronic device
CN103151348A (en) * 2011-12-06 2013-06-12 英飞凌科技奥地利有限公司 Integrated circuit including a power transistor and an auxiliary transistor
TW201411809A (en) * 2012-09-05 2014-03-16 Silicongear Corp Power MOSFET element
US20150091641A1 (en) * 2013-09-30 2015-04-02 Infineon Technologies Austria Ag Integrated Circuit with a Power Transistor and a Driver Circuit Integrated in a Common Semiconductor Body
WO2016173394A1 (en) * 2015-04-30 2016-11-03 苏州东微半导体有限公司 Semiconductor super-junction power device and manufacturing method therefor
CN105161491A (en) * 2015-09-22 2015-12-16 苏州东微半导体有限公司 Integrated gate driver transistor (IGDT) power device and manufacturing method thereof

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CN107369683B (en) 2020-06-23

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