CN107305849B - 封装结构及其制作方法 - Google Patents
封装结构及其制作方法 Download PDFInfo
- Publication number
- CN107305849B CN107305849B CN201610255094.6A CN201610255094A CN107305849B CN 107305849 B CN107305849 B CN 107305849B CN 201610255094 A CN201610255094 A CN 201610255094A CN 107305849 B CN107305849 B CN 107305849B
- Authority
- CN
- China
- Prior art keywords
- layer
- chip
- conductive
- conductive circuit
- circuit layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 239000000758 substrate Substances 0.000 claims abstract description 80
- 229910000679 solder Inorganic materials 0.000 claims abstract description 60
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 50
- 239000011889 copper foil Substances 0.000 claims description 42
- 238000003466 welding Methods 0.000 claims description 20
- 238000007747 plating Methods 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 15
- 238000009713 electroplating Methods 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 3
- 238000003825 pressing Methods 0.000 claims 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- 239000013039 cover film Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010329 laser etching Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610255094.6A CN107305849B (zh) | 2016-04-22 | 2016-04-22 | 封装结构及其制作方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610255094.6A CN107305849B (zh) | 2016-04-22 | 2016-04-22 | 封装结构及其制作方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN107305849A CN107305849A (zh) | 2017-10-31 |
CN107305849B true CN107305849B (zh) | 2020-05-19 |
Family
ID=60152565
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610255094.6A Active CN107305849B (zh) | 2016-04-22 | 2016-04-22 | 封装结构及其制作方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN107305849B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109273578A (zh) * | 2018-11-01 | 2019-01-25 | 深圳市灏天光电有限公司 | 一种led灯支架结构及其制备方法 |
CN114976623B (zh) * | 2022-04-15 | 2023-09-19 | 盛合晶微半导体(江阴)有限公司 | 一种封装结构及其封装方法 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102683220A (zh) * | 2011-03-08 | 2012-09-19 | 中国科学院微电子研究所 | 一种制作多层有机液晶聚合物基板结构的方法 |
CN102800598A (zh) * | 2011-05-24 | 2012-11-28 | 中国科学院微电子研究所 | 埋置有源元件的基板及埋置方法 |
CN102833962A (zh) * | 2011-06-15 | 2012-12-19 | 珠海方正科技多层电路板有限公司富山分公司 | 一种互联电路板制作的方法及互联电路板 |
CN103646880A (zh) * | 2013-09-29 | 2014-03-19 | 华进半导体封装先导技术研发中心有限公司 | 一种基于板级功能基板的封装工艺及封装结构 |
CN104080280A (zh) * | 2013-03-26 | 2014-10-01 | 深南电路有限公司 | 一种封装基板单元及其制作方法和基板组件 |
CN104112673A (zh) * | 2013-04-19 | 2014-10-22 | 宏启胜精密电子(秦皇岛)有限公司 | 芯片封装基板及其制作方法 |
CN104113983A (zh) * | 2013-04-17 | 2014-10-22 | 深南电路有限公司 | 一种埋入式电路板及其制作方法 |
CN104244616A (zh) * | 2014-08-27 | 2014-12-24 | 华进半导体封装先导技术研发中心有限公司 | 一种无芯板薄型基板的制作方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20130032529A (ko) * | 2011-09-23 | 2013-04-02 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
-
2016
- 2016-04-22 CN CN201610255094.6A patent/CN107305849B/zh active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102683220A (zh) * | 2011-03-08 | 2012-09-19 | 中国科学院微电子研究所 | 一种制作多层有机液晶聚合物基板结构的方法 |
CN102800598A (zh) * | 2011-05-24 | 2012-11-28 | 中国科学院微电子研究所 | 埋置有源元件的基板及埋置方法 |
CN102833962A (zh) * | 2011-06-15 | 2012-12-19 | 珠海方正科技多层电路板有限公司富山分公司 | 一种互联电路板制作的方法及互联电路板 |
CN104080280A (zh) * | 2013-03-26 | 2014-10-01 | 深南电路有限公司 | 一种封装基板单元及其制作方法和基板组件 |
CN104113983A (zh) * | 2013-04-17 | 2014-10-22 | 深南电路有限公司 | 一种埋入式电路板及其制作方法 |
CN104112673A (zh) * | 2013-04-19 | 2014-10-22 | 宏启胜精密电子(秦皇岛)有限公司 | 芯片封装基板及其制作方法 |
CN103646880A (zh) * | 2013-09-29 | 2014-03-19 | 华进半导体封装先导技术研发中心有限公司 | 一种基于板级功能基板的封装工艺及封装结构 |
CN104244616A (zh) * | 2014-08-27 | 2014-12-24 | 华进半导体封装先导技术研发中心有限公司 | 一种无芯板薄型基板的制作方法 |
Also Published As
Publication number | Publication date |
---|---|
CN107305849A (zh) | 2017-10-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20220102166A1 (en) | Leadframe package with pre-applied filler material | |
US8810040B2 (en) | Wiring substrate including projecting part having electrode pad formed thereon | |
TWI545998B (zh) | Built-in parts wiring board | |
US9433109B2 (en) | Wiring substrate and semiconductor package | |
US11121107B2 (en) | Interconnect substrate having columnar electrodes | |
KR20060061227A (ko) | 회로 기판의 제조 방법 및 전자부품 실장 구조체의 제조방법 | |
KR20100130555A (ko) | 배선기판 및 그 제조방법 | |
US8067698B2 (en) | Wiring substrate for use in semiconductor apparatus, method for fabricating the same, and semiconductor apparatus using the same | |
US20160157345A1 (en) | Wiring substrate, method of manufacturing the same and electronic component device | |
CN107305849B (zh) | 封装结构及其制作方法 | |
KR20160084666A (ko) | 인쇄회로기판, 반도체 패키지 및 이들의 제조방법 | |
KR20160085120A (ko) | 인쇄회로기판, 그 제조방법, 및 전자부품 모듈 | |
KR20150065029A (ko) | 인쇄회로기판, 그 제조방법 및 반도체 패키지 | |
US9532468B2 (en) | Printed wiring board and method for manufacturing printed wiring board | |
US8786108B2 (en) | Package structure | |
US20190013263A1 (en) | Wiring board and semiconductor package | |
JP2016100352A (ja) | プリント配線板およびその製造方法 | |
JP2019186330A (ja) | 配線基板、半導体パッケージ及び配線基板の製造方法 | |
KR20160010246A (ko) | 전자 소자 모듈 및 그 제조 방법 | |
TWI420989B (zh) | 印刷電路板及其製造方法 | |
EP4213197A1 (en) | A semiconductor package substrate made from non-metallic material and a method of manufacturing thereof | |
JP3692810B2 (ja) | 半導体装置及びその製造方法、回路基板並びに電子機器 | |
JP2007129148A (ja) | 電子部品実装構造体の製造方法 | |
KR101922873B1 (ko) | 전자 소자 모듈 제조 방법 | |
KR101118878B1 (ko) | 회로 기판 및 그 제조 방법, 그리고 상기 회로 기판을 구비하는 반도체 패키지 및 그 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20220722 Address after: No. 18-2, Tengfei Road, Qinhuangdao Economic and Technological Development Zone, Hebei Province Patentee after: Liding semiconductor technology Qinhuangdao Co.,Ltd. Patentee after: Qi Ding Technology Qinhuangdao Co.,Ltd. Patentee after: Zhen Ding Technology Co.,Ltd. Address before: No.18, Tengfei Road, Qinhuangdao Economic and Technological Development Zone, Hebei Province 066004 Patentee before: Qi Ding Technology Qinhuangdao Co.,Ltd. Patentee before: Zhen Ding Technology Co.,Ltd. |
|
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20240205 Address after: 18-2 Tengfei Road, Economic and Technological Development Zone, Qinhuangdao City, Hebei Province Patentee after: Liding semiconductor technology Qinhuangdao Co.,Ltd. Country or region after: China Patentee after: Zhen Ding Technology Co.,Ltd. Country or region after: Taiwan, China Address before: 066004 No. 18-2, Tengfei Road, Qinhuangdao Economic and Technological Development Zone, Hebei Province Patentee before: Liding semiconductor technology Qinhuangdao Co.,Ltd. Country or region before: China Patentee before: Qi Ding Technology Qinhuangdao Co.,Ltd. Patentee before: Zhen Ding Technology Co.,Ltd. Country or region before: Taiwan, China |
|
TR01 | Transfer of patent right |