CN107230712A - The preparation method of zirconium oxide gate medium transistor - Google Patents

The preparation method of zirconium oxide gate medium transistor Download PDF

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Publication number
CN107230712A
CN107230712A CN201610178229.3A CN201610178229A CN107230712A CN 107230712 A CN107230712 A CN 107230712A CN 201610178229 A CN201610178229 A CN 201610178229A CN 107230712 A CN107230712 A CN 107230712A
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medium
contact hole
layer
gate
dielectric layer
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刘美华
孙辉
林信南
陈建国
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Peking University
Peking University Founder Group Co Ltd
Shenzhen Founder Microelectronics Co Ltd
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Peking University
Peking University Founder Group Co Ltd
Shenzhen Founder Microelectronics Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66431Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

The present invention relates to a kind of preparation method of zirconium oxide gate medium transistor, first medium is deposited by surface on a semiconductor substrate, first medium layer is formed;First medium layer is etched, source electrode, the contact hole of drain electrode is formed, redeposited second medium forms second dielectric layer;To second dielectric layer photoetching, etching, source electrode, the second medium of the exterior domain of drain contact hole are removed, so that first medium layer segment upper surface is exposed, first window is formed;With nitrogen as reacting gas, the whole Semiconductor substrate after formation Ohm contact electrode is made annealing treatment;In first window, the aluminum gallium nitride of first medium layer and preset thickness is performed etching, gate contact hole is formed;Zirconium oxide is deposited in gate contact hole, zirconia layer is formed, its thickness is less than the depth in gate contact hole;The 3rd medium is accumulated in gate contact inner hole deposition, so that gate contact hole is completely covered in the 3rd medium, the grid of transistor is formed.

Description

The preparation method of zirconium oxide gate medium transistor
Technical field
The present invention relates to technical field of semiconductor device preparation, more particularly to a kind of zirconium oxide gate medium crystal The preparation method of pipe.
Background technology
With the increasingly increase of efficiently complete circuit for power conversion and system requirements, with low-power consumption and height The power device of fast characteristic is increasingly by extensive concern.
Gallium nitride GaN is third generation semiconductor material with wide forbidden band, and there is big energy gap, high electronics to satisfy for it With speed, high breakdown electric field, higher heat-conductivity, corrosion-resistant and radiation resistance, high pressure, high frequency, There is stronger advantage, it is considered to be research shortwave photoelectricity under high temperature, high-power and Flouride-resistani acid phesphatase environmental condition The optimal material of sub- device and high voltagehigh frequency rate high power device.Gallium nitride GaN base aluminium gallium nitride alloy AlGaN/ Gallium nitride GaN high mobility transistors are the study hotspots in power device, because in aluminium gallium nitride alloy High concentration, the two-dimensional electron gas of high mobility are formed at AlGaN and gallium nitride GaN hetero-junctions (Two-dimensional electron gas, referred to as " 2DEG "), while hetero-junctions has to 2DEG There is good adjustment effect.
However, after the grid power-up of transistor, because grid has leaky, so as to limit nitrogen Change gallium GaN HEMTs (High Electron Mobility Transistor, abbreviation " HEMT ") electrology characteristic and reliability;Meanwhile, electric leakage of the grid can also reduce the breakdown potential of device Pressure and power added efficiency.
The content of the invention
The present invention provides a kind of preparation method of zirconium oxide gate medium transistor, to optimize transistors The manufacture craft of part, it is possible to compatible with CMOS technology line, optimised devices structure reduces grid leakage Electrical phenomena, improves transistor device breakdown characteristics, improves the reliability of gallium nitride semiconductor device.
The present invention provides a kind of preparation method of zirconium oxide gate medium transistor, including:
Surface deposition first medium, forms first medium layer on a semiconductor substrate;The Semiconductor substrate Aluminum gallium nitride, gallium nitride layer, layer-of-substrate silicon are included from top to bottom;
Performed etching on first medium layer, form source contact openings and drain contact hole;
In the first medium layer surface, the source contact openings, in the drain contact hole, deposition Second medium, so that the source contact openings, the drain contact hole is completely covered in the second medium, And form second dielectric layer on first medium layer;
Photoetching, etching are carried out to the second dielectric layer, the source contact openings, the drain electrode is removed and connects The second medium of the exterior domain of contact hole, so that the portion of upper surface of first medium layer is exposed, shape Into first window;The width of the retained second medium is more than or equal to the source contact openings and institute State the width of drain contact bore region, the retained second medium formation Ohm contact electrode;
With nitrogen as reacting gas, to the whole Semiconductor substrate after the formation Ohm contact electrode Made annealing treatment;
In the first window, the aluminum gallium nitride of first medium layer and preset thickness is entered Row etching, forms gate contact hole;
Gate medium zirconium oxide is deposited in the gate contact hole, zirconia layer is formed;The zirconia layer Thickness be less than the gate contact hole depth;
The 3rd medium is accumulated in the gate contact inner hole deposition, so that the grid are completely covered in the 3rd medium Pole contact hole, forms the grid of transistor.
Optionally, the first medium is silicon nitride Si3N4 media;Accordingly, it is described in semiconductor lining Basal surface deposits first medium, and forming first medium layer includes:
In the aluminium gallium nitride alloy layer surface deposited silicon nitride Si3N4 media, silicon nitride Si3N4 media are formed Layer;The thickness of the silicon nitride Si3N4 dielectric layers is 350 angstroms.
Optionally, it is described to be performed etching on first medium layer, form source contact openings and drain electrode connects Contact hole includes:
Dry etching is carried out on first medium layer, source contact openings and drain contact hole is formed;
It is described to be performed etching on first medium layer, formed after source contact openings and drain contact hole, Also include:
Using the mixed solution, hydrogen peroxide and hydrogen chloride of hydrofluoric acid solution, hydrogen peroxide and aqua ammonia Mixed solution, to it is described formation source contact openings and drain contact hole after semiconductor substrate surface enter Row surface treatment.
Optionally, the second medium includes titanium medium, aluminium medium, titanium nitride medium;Accordingly, institute State in the first medium layer surface, the source contact openings, in the drain contact hole, deposition the Second medium, so that the source contact openings, the drain contact hole is completely covered in the second medium, and Forming second dielectric layer on first medium layer includes:
In the first medium layer surface, the source contact openings, in the drain contact hole, successively The titanium medium, aluminium medium, titanium medium, titanium nitride medium are deposited, to form the second dielectric layer; So that the second dielectric layer includes from bottom to top:First titanium dielectric layer, aluminium dielectric layer, the second titanium medium Layer, titanium nitride dielectric layer;Wherein, the thickness of the first titanium dielectric layer is 200 angstroms, the aluminium medium The thickness of layer is 1200 angstroms, the thickness of the second titanium dielectric layer is 200 angstroms, the titanium nitride dielectric layer Thickness be 200 angstroms.
Optionally, it is described with nitrogen as reacting gas, to whole after the formation Ohm contact electrode Individual Semiconductor substrate, which carries out annealing, to be included:
With nitrogen as reacting gas, under conditions of 840 degrees Celsius, to the formation Ohmic contact electricity Whole Semiconductor substrate after pole carries out the annealing of 30 seconds.
Optionally, the depth in the gate contact hole is 475 angstroms~550 angstroms.
Optionally, in the first window, the nitridation to first medium layer and preset thickness Gallium aluminium layer is performed etching, and forming gate contact hole includes:
In the first window, the aluminum gallium nitride of first medium layer and preset thickness is entered Row dry etching, forms gate contact hole.
Optionally, it is described in the first window, to described in first medium layer and preset thickness Aluminum gallium nitride is performed etching, and is formed after gate contact hole, in addition to:
The gate contact hole is cleaned using hydrochloric acid solution, to remove the impurity thing in the gate contact hole.
Optionally, the 3rd medium includes:Nickel metal medium, golden metal medium.
Optionally, it is described to accumulate the 3rd medium in the gate contact inner hole deposition, so that the 3rd medium is complete Gate contact hole described in all standing, forming the grid of transistor includes:
Have second between the Ohm contact electrode on the gate contact hole and the source contact openings Have the between the Ohm contact electrode on window, the gate contact hole and the drain contact hole Three windows, the width of second window is less than the width of the 3rd window.
The preparation method of the zirconium oxide gate medium transistor of the present invention, by from top to bottom comprising nitridation Gallium aluminium layer, gallium nitride layer, the Semiconductor substrate upper surface deposition first medium of layer-of-substrate silicon, form the One dielectric layer;Then performed etching on first medium layer, form source contact openings and drain contact hole; In first medium layer surface, source contact openings, in drain contact hole, second medium is deposited, so that Source contact openings, drain contact hole is completely covered in second medium, and forms second on first medium layer Dielectric layer;To second dielectric layer carry out photoetching, etching, remove source contact openings, drain contact hole it The second medium of exterior domain, so that the portion of upper surface of first medium layer is exposed, forms first window; The width of retained second medium is more than or equal to the width of source contact openings and drain contact bore region Degree, retained second medium formation Ohm contact electrode;With nitrogen as reacting gas, to being formed Whole Semiconductor substrate after Ohm contact electrode is made annealing treatment;In first window, to first Dielectric layer and the aluminum gallium nitride of preset thickness are performed etching, and form gate contact hole;Connect in grid Deposit gate medium zirconium oxide in contact hole, forms zirconia layer;The thickness of zirconia layer is less than gate contact The depth in hole;The 3rd medium is accumulated in gate contact inner hole deposition, so that the 3rd medium is completely covered grid and connect Contact hole, forms the grid of transistor.The Optimization of preparation of above-mentioned zirconium oxide gate medium transistor crystalline substance The manufacture craft of body tube device, it is possible to compatible with CMOS technology line, optimised devices structure, effectively Electric leakage of the grid phenomenon is reduced, improves transistor device breakdown characteristics, improves gallium nitride semiconductor device Reliability.
Brief description of the drawings
Fig. 1 is the flow of the preparation method of the zirconium oxide gate medium transistor shown in an exemplary embodiment Figure;
Fig. 2~Fig. 8 is the cross-sectional view of the zirconium oxide gate medium transistor of embodiment illustrated in fig. 1;
Fig. 9 is the flow of the preparation method of the zirconium oxide gate medium transistor shown in another exemplary embodiment Figure.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with this hair Accompanying drawing in bright embodiment, the technical scheme in the embodiment of the present invention is clearly and completely described, Obviously, described embodiment is a part of embodiment of the invention, rather than whole embodiments.It is based on Embodiment in the present invention, those of ordinary skill in the art are obtained under the premise of creative work is not made The every other embodiment obtained, belongs to the scope of protection of the invention.
Fig. 1 is the flow of the preparation method of the zirconium oxide gate medium transistor shown in an exemplary embodiment Figure, Fig. 2~Fig. 8 is the cross-sectional view of the zirconium oxide gate medium transistor of embodiment illustrated in fig. 1, As shown in Fig. 1~8, the method for the present embodiment includes:
Step 101, on a semiconductor substrate surface deposition first medium, form first medium layer 14.
Specifically, the Semiconductor substrate includes aluminum gallium nitride 13 (AlGaN), gallium nitride layer from top to bottom 12 (GaN), layer-of-substrate silicon 11 (Si).Wherein, the cross-sectional view of Semiconductor substrate such as Fig. 2 It is shown, aluminum gallium nitride 13, gallium nitride layer 12, layer-of-substrate silicon 11 are followed successively by from top to bottom.In nitridation 13 upper surface of gallium aluminium layer deposition first medium, forms first medium layer 14.Wherein, gallium nitride is Three generations's semiconductor material with wide forbidden band, it has big energy gap (3.4eV), high electron saturation velocities (2e7cm/s), high breakdown electric field (1e10~-3e10V/cm), higher heat-conductivity, corrosion-resistant and anti-spoke Penetrate the characteristics such as performance and have under high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase environmental condition Stronger advantage, is the optimal material for studying shortwave opto-electronic device and high voltagehigh frequency rate high power device.
Step 102, perform etching on first medium layer 14, form source contact openings 15 and drain electrode and connect Contact hole 16.
Specifically, being performed etching on the first medium layer 14 shown in Fig. 2, the mode of etching can be used Dry etching, dry etching is the technology that film etching is carried out with plasma, by aluminum gallium nitride 13 On part first medium remove, as shown in figure 3, exposing source contact openings 15 and drain contact hole 16.
Step 103, on 14 surface of first medium layer, in source contact openings 15, in drain contact hole 16, Second medium is deposited, so that second medium is completely covered source contact openings 15, drain contact hole 16, and Second dielectric layer 17 is formed on first medium layer 14.
Specifically, as shown in figure 4, magnetron sputtering membrane process can be used, in first medium layer 14 Deposition second medium in surface and source contact openings 15, in drain contact hole 16, so that second medium Full of in whole source contact openings 15 and drain contact hole 16.On the surface of first medium layer 14 after deposition Upper formation second dielectric layer 17.
Step 104, to second dielectric layer 17 carry out photoetching, etching, remove source contact openings 15, drain electrode The second medium of the exterior domain of contact hole 16, so that the portion of upper surface of first medium layer 14 is exposed, shape Into first window 18;The width of retained second medium is more than or equal to source contact openings 15 and drain electrode The width in the region of contact hole 16, retained second medium formation Ohm contact electrode.
Specifically, as shown in figure 5, carrying out photoetching, etching to second dielectric layer 17;Wherein, photoetching Technique includes gluing, the process such as exposed and developed, after etching, by source contact openings 15, drain contact The second medium of the exterior domain in hole 16 is removed, and makes the portion of upper surface of first medium layer 14 exposed, source electrode Exposed part first medium layer 14 forms first window 18 between contact hole 15 and drain contact hole 16; Full source contact openings 15 are filled by second medium and drain contact hole 16 forms Ohm contact electrode;Its In, second medium is metal medium.
Step 105, with nitrogen as reacting gas, whole partly led to formed after Ohm contact electrode Body substrate is made annealing treatment.
Specifically, being passed through nitrogen N 2 in reacting furnace, the whole Semiconductor substrate currently formed is carried out high Temperature annealing, so that the source contact openings 15 of the full second medium of filling form good with drain contact hole 16 The electrode metal of good Ohmic contact.Meanwhile, annealing can also make second dielectric layer 17 and aluminium nitride Gallium layer 13 is reacted to form alloy on both contact surfaces, to reduce second dielectric layer 17 and nitrogen Change the contact resistance between gallium aluminium layer 13.
Step 106, in first window 18, to first medium layer 14 and the aluminum gallium nitride of preset thickness 13 perform etching, and form gate contact hole 19.
Specifically, using dry etching in the region of first window 18, remove all first Jie of predetermined width Matter layer 14, and preset thickness (depth) aluminum gallium nitride 13, form gate contact hole 19.Such as Shown in Fig. 6, gate contact hole 19 completely penetrates through first medium layer 14, and passes through the aluminium gallium nitride alloy of part Layer 13 so that the depth ratio source contact openings 15 in gate contact hole 19 and the depth of drain contact hole 16 It is deep.
Step 107, the deposit gate medium zirconium oxide in gate contact hole 19, form zirconia layer 20.
Specifically, zirconium oxide ZrO2 coatings can be prepared using chemical vapour deposition technique, as shown in fig. 7, The thickness of the zirconia layer 20 is less than the depth in gate contact hole 19.
Step 108, the 3rd medium 21 of deposition in gate contact hole 19, so that the 3rd medium 21 is complete Grid contact hole 19 is covered, the grid of transistor is formed.
Specifically, magnetron sputtering membrane process can be used, the 3rd medium of deposition in gate contact hole 19 21, so that the region of gate contact hole 19 is completely covered in the 3rd medium 21, so as to form the contact of grid Electrode, forms zirconium oxide gate medium transistor.
The preparation method of the zirconium oxide gate medium transistor of the present embodiment, by including nitrogen from top to bottom Change gallium aluminium layer, gallium nitride layer, the Semiconductor substrate upper surface deposition first medium of layer-of-substrate silicon, formed First medium layer;Then performed etching on first medium layer, form source contact openings and drain contact Hole;In first medium layer surface, source contact openings, in drain contact hole, second medium is deposited, So that source contact openings, drain contact hole is completely covered in second medium, and formed on first medium layer Second dielectric layer;Photoetching, etching are carried out to second dielectric layer, source contact openings, drain contact is removed The second medium of the exterior domain in hole, so that the portion of upper surface of first medium layer is exposed, forms the first window Mouthful;The width of retained second medium is more than or equal to source contact openings and drain contact bore region Width, retained second medium formation Ohm contact electrode;With nitrogen as reacting gas, to shape Made annealing treatment into the whole Semiconductor substrate after Ohm contact electrode;In first window, to One dielectric layer and the aluminum gallium nitride of preset thickness are performed etching, and form gate contact hole;In grid Deposit gate medium zirconium oxide in contact hole, forms zirconia layer;The thickness of zirconia layer connects less than grid The depth of contact hole;The 3rd medium is accumulated in gate contact inner hole deposition, so that grid is completely covered in the 3rd medium Contact hole, forms the grid of transistor.The Optimization of preparation of above-mentioned zirconium oxide gate medium transistor The manufacture craft of transistor device, it is possible to compatible with CMOS technology line, optimised devices structure has Effect reduces electric leakage of the grid phenomenon, improves transistor device breakdown characteristics, improves gallium nitride semiconductor device The reliability of part.
Fig. 9 is the flow of the preparation method of the zirconium oxide gate medium transistor shown in another exemplary embodiment Figure, such as Fig. 9 and the cross-sectional view with reference to shown in Fig. 2~Fig. 8, on the basis of a upper embodiment, The method of the present embodiment includes:
Step 201, on a semiconductor substrate surface deposition first medium, form first medium layer 14.
Specifically, first medium can be silicon nitride Si3N4Medium, in the surface of aluminum gallium nitride 13 deposition Silicon nitride Si3N4 media, form silicon nitride Si3N4 dielectric layers 14;Wherein, silicon nitride Si3N4 media The thickness of layer 14 can be 350 angstroms.The formation of first medium layer 14 can be strengthened with using plasma Chemical gaseous phase electrodeposition method, is passed through silane SiH in reacting furnace4Gas, oxygen O2, nitric oxide NO The mixed gas of gas, or it is passed through silane gas, oxygen, carbon dioxide CO2The mixed gas of gas, Generation silicon nitride Si after being reacted so as to mixed gas3N4, surface cvd nitride on a semiconductor substrate Silicon Si3N4, form silicon nitride layer 14.
Step 202, perform etching on first medium layer 14, form source contact openings 15 and drain electrode and connect Contact hole 16.
Step 203, the mixed solution using hydrofluoric acid solution, hydrogen peroxide and aqua ammonia, peroxidating The mixed solution of hydrogen and hydrogen chloride, to partly leading after formation source contact openings 15 and drain contact hole 16 Body substrate surface is surface-treated.
Specifically, after dry etching is carried out to first medium layer 14, the Semiconductor substrate table after etching Face can have the impurity things such as impurity, particle, using DHF+SC1+SC2, i.e., first using the hydrogen after dilution Fluorspar acid solution handles surface, then using the alkaline mixed solution processing surface of hydrogen peroxide and aqua ammonia, Again using the acidic mixed solution processing surface of hydrogen peroxide and hydrogen chloride, the impurity thing on surface can be removed.
Step 204, second medium include titanium medium, aluminium medium, titanium nitride medium;In first medium layer 14 surfaces, in source contact openings 15, in drain contact hole 16, be sequentially depositing titanium medium, aluminium medium, Titanium medium, titanium nitride medium, to form second dielectric layer 17.
Specifically, second dielectric layer 17 includes from bottom to top:First titanium Ti dielectric layers, aluminium Al dielectric layers, Second titanium Ti dielectric layers, titanium nitride TiN dielectric layers;Wherein, the thickness of each layer is:First titanium dielectric layer Thickness be 200 angstroms, the thickness of aluminium dielectric layer be 1200 angstroms, the thickness of the second titanium dielectric layer be 200 angstroms, The thickness of titanium nitride dielectric layer is 200 angstroms.
Step 205, to second dielectric layer 17 carry out photoetching, etching, remove source contact openings 15, drain electrode The second medium of the exterior domain of contact hole 16, so that the portion of upper surface of first medium layer 14 is exposed, shape Into first window 18;The width of retained second medium is more than or equal to source contact openings 15 and drain electrode The width in the region of contact hole 16, retained second medium formation Ohm contact electrode.
Step 206, with nitrogen as reacting gas, under conditions of 840 degrees Celsius, to formed ohm Whole Semiconductor substrate after contact electrode carries out the annealing of 30 seconds.
Step 207, in first window 18, to first medium layer 14 and the aluminum gallium nitride of preset thickness 13 perform etching, and form gate contact hole 19.
Wherein, the mode of etching can use dry etching, and the depth in gate contact hole 19 is preferably 475 Angstrom~550 angstroms.
Step 208, gate contact hole 19 cleaned using hydrochloric acid solution, to remove in gate contact hole 19 Impurity thing.
Specifically, it is miscellaneous to have impurity, particle, ion etc. in the gate contact hole 19 obtained by etching Matter thing, gate contact hole 19 is cleaned by using hydrochloric acid HCL solution, will be miscellaneous in gate contact hole 19 Matter thing is got rid of, and possesses good electric property with the grid for ensureing subsequent deposition formation.
Step 209, the deposit gate medium zirconium oxide in gate contact hole 19, form zirconia layer 20.
Step 210, the 3rd medium 21 of deposition in gate contact hole 19, so that the 3rd medium 21 is complete Grid contact hole 19 is covered, the grid of transistor is formed.
Specifically, the 3rd medium 21 can include:Nickel metal medium, golden metal medium.Gate contact hole 19 and source contact openings 15 on Ohm contact electrode between have the second window 22, gate contact hole 19 With the 3rd window 23 between the Ohm contact electrode on drain contact hole 16, and the second window 22 Width is less than the width of the 3rd window 23.
One of ordinary skill in the art will appreciate that:Realize all or part of step of above-mentioned each method embodiment Suddenly it can be completed by the related hardware of programmed instruction.Foregoing program can be stored in a computer can Read in storage medium.The program upon execution, performs the step of including above-mentioned each method embodiment;And Foregoing storage medium includes:ROM, RAM, magnetic disc or CD etc. are various can be with store program codes Medium.
Finally it should be noted that:Various embodiments above is merely illustrative of the technical solution of the present invention, rather than right It is limited;Although the present invention is described in detail with reference to foregoing embodiments, this area it is common Technical staff should be understood:It can still modify to the technical scheme described in foregoing embodiments, Or equivalent substitution is carried out to which part or all technical characteristic;And these modifications or replacement, and The essence of appropriate technical solution is not set to depart from the scope of various embodiments of the present invention technical scheme.

Claims (10)

1. a kind of preparation method of zirconium oxide gate medium transistor, it is characterised in that including:
Surface deposition first medium, forms first medium layer on a semiconductor substrate;The Semiconductor substrate Aluminum gallium nitride, gallium nitride layer, layer-of-substrate silicon are included from top to bottom;
Performed etching on first medium layer, form source contact openings and drain contact hole;
In the first medium layer surface, the source contact openings, in the drain contact hole, deposition Second medium, so that the source contact openings, the drain contact hole is completely covered in the second medium, And form second dielectric layer on first medium layer;
Photoetching, etching are carried out to the second dielectric layer, the source contact openings, the drain electrode is removed and connects The second medium of the exterior domain of contact hole, so that the portion of upper surface of first medium layer is exposed, shape Into first window;The width of the retained second medium is more than or equal to the source contact openings and institute State the width of drain contact bore region, the retained second medium formation Ohm contact electrode;
With nitrogen as reacting gas, to the whole Semiconductor substrate after the formation Ohm contact electrode Made annealing treatment;
In the first window, the aluminum gallium nitride of first medium layer and preset thickness is entered Row etching, forms gate contact hole;
Gate medium zirconium oxide is deposited in the gate contact hole, zirconia layer is formed;The zirconia layer Thickness be less than the gate contact hole depth;
The 3rd medium is accumulated in the gate contact inner hole deposition, so that the grid are completely covered in the 3rd medium Pole contact hole, forms the grid of transistor.
2. according to the method described in claim 1, it is characterised in that the first medium is silicon nitride Si3N4 media;Accordingly, it is described to deposit first medium in semiconductor substrate surface, form first medium Layer includes:
In the aluminium gallium nitride alloy layer surface deposited silicon nitride Si3N4 media, silicon nitride Si3N4 media are formed Layer;The thickness of the silicon nitride Si3N4 dielectric layers is 350 angstroms.
3. according to the method described in claim 1, it is characterised in that described on first medium layer Perform etching, forming source contact openings and drain contact hole includes:
Dry etching is carried out on first medium layer, source contact openings and drain contact hole is formed;
It is described to be performed etching on first medium layer, formed after source contact openings and drain contact hole, Also include:
Using the mixed solution, hydrogen peroxide and hydrogen chloride of hydrofluoric acid solution, hydrogen peroxide and aqua ammonia Mixed solution, to it is described formation source contact openings and drain contact hole after semiconductor substrate surface enter Row surface treatment.
4. according to the method described in claim 1, it is characterised in that the second medium include titanium medium, Aluminium medium, titanium nitride medium;Accordingly, it is described in the first medium layer surface, the source contact In hole, in the drain contact hole, deposit second medium so that the second medium be completely covered it is described Source contact openings, the drain contact hole, and formation second dielectric layer includes on first medium layer:
In the first medium layer surface, the source contact openings, in the drain contact hole, successively The titanium medium, aluminium medium, titanium medium, titanium nitride medium are deposited, to form the second dielectric layer; So that the second dielectric layer includes from bottom to top:First titanium dielectric layer, aluminium dielectric layer, the second titanium medium Layer, titanium nitride dielectric layer;Wherein, the thickness of the first titanium dielectric layer is 200 angstroms, the aluminium medium The thickness of layer is 1200 angstroms, the thickness of the second titanium dielectric layer is 200 angstroms, the titanium nitride dielectric layer Thickness be 200 angstroms.
5. according to the method described in claim 1, it is characterised in that described with nitrogen as reacting gas, Carrying out annealing to the whole Semiconductor substrate after the formation Ohm contact electrode includes:
With nitrogen as reacting gas, under conditions of 840 degrees Celsius, to the formation Ohmic contact electricity Whole Semiconductor substrate after pole carries out the annealing of 30 seconds.
6. according to the method described in claim 1, it is characterised in that the depth in the gate contact hole is 475 angstroms~550 angstroms.
7. the method according to any one of claim 1~6, it is characterised in that in the first window, The aluminum gallium nitride of first medium layer and preset thickness is performed etching, gate contact is formed Hole includes:
In the first window, the aluminum gallium nitride of first medium layer and preset thickness is entered Row dry etching, forms gate contact hole.
8. the method according to any one of claim 1~6, it is characterised in that described described first Window, performs etching to the aluminum gallium nitride of first medium layer and preset thickness, forms grid After the contact hole of pole, in addition to:
The gate contact hole is cleaned using hydrochloric acid solution, to remove the impurity thing in the gate contact hole.
9. the method according to any one of claim 1~6, it is characterised in that the 3rd medium bag Include:Nickel metal medium, golden metal medium.
10. method according to claim 9, it is characterised in that described in the gate contact hole The 3rd medium of interior deposition, so that the gate contact hole is completely covered in the 3rd medium, forms transistor Grid include:
Have second between the Ohm contact electrode on the gate contact hole and the source contact openings Have the between the Ohm contact electrode on window, the gate contact hole and the drain contact hole Three windows, the width of second window is less than the width of the 3rd window.
CN201610178229.3A 2016-03-25 2016-03-25 The preparation method of zirconium oxide gate medium transistor Pending CN107230712A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102017160A (en) * 2008-04-23 2011-04-13 特兰斯夫公司 Enhancement mode III-N HEMTs
CN103579328A (en) * 2012-08-09 2014-02-12 台湾积体电路制造股份有限公司 High electron mobility transistor and manufacturing method thereof
US20160079371A1 (en) * 2014-09-12 2016-03-17 Kabushiki Kaisha Toshiba Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102017160A (en) * 2008-04-23 2011-04-13 特兰斯夫公司 Enhancement mode III-N HEMTs
CN103579328A (en) * 2012-08-09 2014-02-12 台湾积体电路制造股份有限公司 High electron mobility transistor and manufacturing method thereof
US20160079371A1 (en) * 2014-09-12 2016-03-17 Kabushiki Kaisha Toshiba Semiconductor device

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Application publication date: 20171003