CN107180817B - Electrostatic discharge protector and forming method thereof - Google Patents
Electrostatic discharge protector and forming method thereof Download PDFInfo
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- CN107180817B CN107180817B CN201610134352.5A CN201610134352A CN107180817B CN 107180817 B CN107180817 B CN 107180817B CN 201610134352 A CN201610134352 A CN 201610134352A CN 107180817 B CN107180817 B CN 107180817B
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Abstract
The present invention provides a kind of electrostatic discharge protector and forming method thereof, wherein the forming method includes: substrate, including neighbouring first crystal area under control and second transistor area；Neighbouring the first P doped region and the first N doped region in the substrate of first crystal area under control；The 2nd P doped region and the 2nd N doped region in second transistor area substrate, the first P doped region and the 2nd N doped region be neighbouring or the first N doped region and the 2nd P doped region are neighbouring or the first P doped region neighbouring and the first N doped region and the 2nd P doped region are neighbouring with the 2nd N doped region；Positioned at the anode of the first P doped region and the 2nd P doped region surface；Positioned at the cathode of the first N doped region and the 2nd N doped region surface.The electrostatic discharge protector has more Electro-static Driven Comb path, can reduce the current density in electrostatic discharge protector, reduces electric current and generates damage to electrostatic discharge protector.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of electrostatic discharge protector and its formation sides
Method.
Background technique
Electrostatic is a kind of natural phenomena of objective reality, and there are many modes of generation, such as contact, friction, appliance chamber induction
Deng.Electrostatic has the characteristics that accumulation for a long time, high voltage, low battery, low current and action time are short.
For electronic product, static discharge (Electrostatic discharge, ESD) is to influence integrated circuit
One principal element of reliability.ESD is a kind of quick N-process of charge.Due to electrostatic potential is very high can be to integrated circuit
The consequence of causing damage property causes the failure of integrated circuit.Therefore, in order to protect integrated circuit from the damage of ESD, ESD is protected
Shield device is also designed in integrated circuit, to prevent damage of the integrated circuit by ESD.
Since fin formula field effect transistor (Fin Field-Effect Transistor, FinFET) can increase grid
Structure has important application to the control action of channel, therefore in technical field of semiconductors, however formed in FinFET processing procedure
ESD protective device, since fin width is smaller, the current channel that ESD protective device is formed when being connected is relatively narrow, therefore, ESD protection
Current density is larger in device, and ESD protective device is easy to be damaged.
It can be seen that the ESD protective device formed in FinFET processing procedure has current density larger, ESD protective device is held
Easy impaired disadvantage.
Summary of the invention
Problems solved by the invention is to provide a kind of electrostatic discharge protector and forming method thereof, can reduce electrostatic and put
The damage of electric protective component.
To solve the above problems, the present invention provides a kind of electrostatic discharge protector, comprising: substrate, the substrate include
Neighbouring first crystal area under control and second transistor area；The first neighbouring P doped region and in the substrate of first crystal area under control
One N doped region；The 2nd P doped region and the 2nd N doped region in second transistor area substrate, the first P doped region with
The neighbouring perhaps described first N doped region of 2nd N doped region and the 2nd P doped region are neighbouring or the first P mixes
Miscellaneous area is neighbouring with the 2nd N doped region and the first N doped region and the 2nd P doped region are neighbouring；Positioned at the first P
The anode of doped region and the 2nd P doped region surface；Positioned at the cathode of the first N doped region and the 2nd N doped region surface.
Optionally, the substrate includes substrate and the fin on substrate；The first P doped region, the first N doping
Area, the 2nd P doped region and the 2nd N doped region are located in the fin.
Optionally, there is fin between the first P doped region and the first N doped region.
Optionally, there is fin between the 2nd P doped region and the 2nd N doped region.
Optionally, there is isolation structure in the fin between the first P doped region and the first N doped region.
Optionally, there is isolation structure in the fin between the 2nd P doped region and the 2nd N doped region.
Optionally, the material of the isolation structure is silica.
Optionally, the first P doped region and the contact of the first N doped region；The 2nd P doped region and the 2nd N doped region
Contact.
Optionally, the electrostatic discharge protector further include: be located at the first P doped region and the first N doped region it
Between substrate surface gate structure.
Optionally, the electrostatic discharge protector further include: be located at the 2nd P doped region and the 2nd N doped region it
Between substrate surface gate structure.
Correspondingly, the present invention also provides a kind of forming methods of electrostatic discharge protector characterized by comprising shape
At substrate, the substrate includes neighbouring first crystal area under control and second transistor area；In the substrate of the first crystal area under control
Form the first P doped region；The 2nd P doped region is formed in second transistor area substrate；In the substrate of the first crystal area under control
Form the first N doped region of neighbouring first P doped region；The of neighbouring 2nd P doped region is formed in second transistor area substrate
Two N doped regions, the first P doped region are mixed adjacent to the 2nd N doped region or the first N doped region adjacent to the 2nd P
Miscellaneous area or the first P doped region are adjacent to the 2nd N doped region, and the first N doped region is mixed adjacent to the 2nd P
Miscellaneous area；Anode is formed in the first P doped region and the 2nd P doped region surface；It is adulterated in the first N doped region and the 2nd N
Area surface forms cathode.
Optionally, the step of forming the first P doped region and the 2nd P doped region includes: to provide the first light shield, and described the
One light shield includes the first figure corresponding with the first P doped region and the 2nd P doped region；It is exposure mask to described using first light shield
Substrate carries out ion implanting, forms the first P doped region and the 2nd P doped region；
The step of forming the first N doped region and the 2nd N doped region includes: to provide the second light shield, second light shield
Including second graph corresponding with the first N doped region and the 2nd N doped region；Using second light shield as exposure mask to the substrate into
Row ion implanting forms the first N doped region and the 2nd N doped region.
Optionally, the step of forming substrate includes: offer initial substrate；The initial substrate is patterned to form lining
Bottom and the fin on substrate, the fin connects the first P doped region and the first N doped region, the fin are also connected with the 2nd P
Doped region and the 2nd N doped region.
Optionally, it is formed after the substrate, the forming method further include: form grid knot in the substrate surface
Structure；The first P doped region and the first N doped region are located in the substrate of the gate structure two sides；The 2nd P doping
Area and the 2nd N doped region are located in the substrate of the gate structure two sides.
Optionally, the step of forming substrate includes: offer initial substrate；The initial substrate is patterned, is formed
Substrate and the fin on substrate；
It is formed after substrate, the forming method further include: the graphical fin forms groove in the fin；
Isolation structure is formed in the groove；
The first P doped region and the first N doped region are located in the substrate of the isolation structure two sides；Described second
P doped region and the 2nd N doped region are located in the substrate of the isolation structure two sides.
Optionally, the groove exposes the substrate.
Optionally, the material of the isolation structure is silica
Compared with prior art, technical solution of the present invention has the advantage that
In electrostatic discharge protector of the invention, adulterated in the substrate of the first crystal area under control with the first neighbouring P
Area and the first N doped region have neighbouring the 2nd P doped region and the 2nd N doped region in second transistor area substrate, because
This can be between the first P doped region and the first N doped region in electrostatic discharge protector conducting, the 2nd P doping
Conductive channel is formed between area and the 2nd N doped region, realizes the release to electrostatic.In addition, the first P doped region and described the
Two N doped regions are neighbouring or the first N doped region and the 2nd P doped region are neighbouring or the first P doped region and institute
State that the 2nd N doped region is neighbouring and the first N doped region and the 2nd P doped region are neighbouring, therefore, electrostatic discharge protector
When conducting, additionally it is possible between the first P doped region and the 2nd N doped region or the first N doped region and the 2nd P doped region it
Between or the first P doped region and the 2nd N doped region between and the first N doped region and the 2nd P doped region between formed and lead
Electric pathway, to increase the path of Electro-static Driven Comb.Therefore, the electrostatic discharge protector has more Electro-static Driven Comb road
Diameter can reduce the current density in electrostatic discharge protector, and it is excessive to electrostatic discharge protector production to reduce current density
Raw damage.
Further, in the fin between the first P doped region and the first N doped region there is isolation structure or the 2nd P to mix
Have between isolation structure or the first P doped region and the first N doped region between miscellaneous area and the 2nd N doped region and the 2nd P mixes
There is isolation structure, the isolation structure can be realized the first P doped region and the in fin between miscellaneous area and the 2nd N doped region
Between one N doped region or the 2nd P doped region and the 2nd N doped region or between the first P doped region and the first N doped region and
Electric isolution between 2nd P doped region and the 2nd N doped region, can make electric current by anode by the substrate below isolation structure to
Up to cathode, to increase the length of current channel, current density is reduced, and then reduce electric current to electrostatic discharge protector
Damage.
In the forming method of electrostatic discharge protector of the invention, mix the first P doped region adjacent to the 2nd N
Miscellaneous area or the first N doped region are mixed adjacent to the 2nd P doped region or the first P doped region adjacent to the 2nd N
Miscellaneous area, and the first N doped region is adjacent to the 2nd P doped region.When electrostatic discharge protector is connected, it can increase the
Between one P doped region and the 2nd N doped region perhaps between the first N doped region and the 2nd P doped region or the first P doping
Between bis- N doped region of Qu Yu and the conductive path between the first N doped region and the 2nd P doped region, increase electrostatic are released
The path put.Therefore, it can reduce the current density in electrostatic discharge protector, it is excessive to the electrostatic to reduce current density
The damage that discharge prevention device generates.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of one embodiment of electrostatic discharge protector；
Fig. 2 and Fig. 3 is the structural schematic diagram of one embodiment of electrostatic discharge protector of the invention；
Fig. 4 and Fig. 5 is the structural schematic diagram of the another embodiment of electrostatic discharge protector of the invention；
Fig. 6 to Figure 11 is each step structural representation of one embodiment of forming method of electrostatic discharge protector of the invention
Figure；
Figure 12 and Figure 13 is that each step structure of the another embodiment of forming method of electrostatic discharge protector of the invention is shown
It is intended to.
Specific embodiment
There are problems for existing ESD protective device, such as: current density is larger in ESD protective device, is easy to be damaged
Bad disadvantage.
It is larger below in conjunction with current density in Fig. 1 analysis ESD protective device, it is easy impaired reason, Fig. 1 is a kind of
The structural schematic diagram of ESD protective device.
Referring to FIG. 1, the ESD protective device includes:
Substrate 100, the substrate 100 include neighbouring first area A and second area B；
Multiple fins 120 positioned at 100 surface of substrate；
Across the gate structure 110 of first area A and second area B fin 120, the gate structure 110 covers described
120 partial sidewall of fin and top surface；
Doped region in 110 two sides fin 120 of gate structure, in the doped region, positioned at the doping of first area A
Area is P doped region, and the doped region positioned at second area B is N doped region；
Anode 111 positioned at P doped region surface；
Cathode 112 positioned at N doped region surface.
In the ESD protective device, the type of the doped region in the doped region and second area B of first area A
Difference therefore, can be between the P doped region and N doped region of first area A and second area B when ESD protective device is connected
Conductive channel is formed, Electro-static Driven Comb is made.However, the doped region type positioned at first area A is identical；Positioned at mixing for second area B
Miscellaneous area's type is also identical, thus, conductive channel cannot be formed between the doped region of 110 two sides of gate structure.Therefore, described
Conductive channel is few in ESD protective device, and the current density in ESD protective device is larger.
In addition, different types of doped region is handed on same fin in first crystal area under control in another ESD protective device
For distribution, first crystal area under control is identical as the doped region type that second transistor area is adjacent.Therefore, when ESD protective device is connected
When, conductive channel can only be formed in the fin of the first transistor and second transistor, conductive channel is less, and since fin is wide
Degree is smaller, and the current channel that ESD protective device is formed when being connected is relatively narrow, and therefore, the current density in ESD protective device is larger,
It is easily damaged electrostatic discharge protector.
To solve the technical problem, the present invention provides a kind of ESD protection circuits, comprising: substrate, the base
Bottom includes neighbouring first crystal area under control and second transistor area；The first neighbouring P doping in the substrate of first crystal area under control
Area and the first N doped region；The 2nd P doped region and the 2nd N doped region in second transistor area substrate, the first P mix
Miscellaneous area and the 2nd N doped region be neighbouring or the first N doped region and the 2nd P doped region are neighbouring or the first P mixes
Miscellaneous area is neighbouring with the 2nd N doped region and the first N doped region and the 2nd P doped region are neighbouring；Positioned at the first P
The anode of doped region and the 2nd P doped region surface；Positioned at the cathode of the first N doped region and the 2nd N doped region surface.
Wherein, there is neighbouring the first P doped region and the first N doped region in the substrate of the first crystal area under control, described the
In two-transistor area substrate there is neighbouring the 2nd P doped region and the 2nd N doped region therefore to lead in electrostatic discharge protector
When logical, it can be formed between the 2nd P doped region and the 2nd N doped region between the first P doped region and the first N doped region
Conductive channel realizes the release to electrostatic.In addition, the first P doped region and the 2nd N doped region are neighbouring or described
One N doped region and the 2nd P doped region be neighbouring or the first P doped region and the 2nd N doped region it is neighbouring and described
First N doped region and the 2nd P doped region are neighbouring, therefore, when electrostatic discharge protector is connected, additionally it is possible to mix in the first P
Between miscellaneous area and the 2nd N doped region perhaps between the first N doped region and the 2nd P doped region or the first P doped region and
Conductive path is formed between two N doped regions and between the first N doped region and the 2nd P doped region, is released to increase electrostatic
The path put.Therefore, the electrostatic discharge protector has more Electro-static Driven Comb path, can reduce electrostatic discharge (ESD) protection
Current density in device reduces the excessive damage generated to electrostatic discharge protector of current density.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 2 and Fig. 3 is the structural schematic diagram of one embodiment of electrostatic discharge protector of the present invention.Fig. 2 and Fig. 3 are please referred to,
Fig. 3 is cross-sectional view of the Fig. 2 along dotted line 1-1 '.The electrostatic discharge protector includes:
Substrate, the substrate include neighbouring first crystal area under control I and second transistor area II；
Neighbouring the first P doped region 231 and the first N doped region 232 in the first crystal area under control I substrate；
Neighbouring the 2nd P doped region and the 2nd N doped region, the first P in the second transistor area II substrate
Doped region 231 and the 2nd N doped region be neighbouring or the first N doped region 232 and the 2nd P doped region it is neighbouring, or
The first P the doped region 231 neighbouring and described first N doped region 232 and the 2nd P doped region with the 2nd N doped region
It is neighbouring；
Positioned at the anode of the first P doped region 231 and the 2nd P doped region surface；
Positioned at the cathode of the first N doped region 232 and the 2nd N doped region surface.
It should be noted that the present embodiment is carried out for improving the electrostatic discharge protector formed in FinFET processing procedure
Explanation.But in other embodiments, electrostatic discharge protector structure of the invention can be used for planar transistor processing procedure
In.
It is illustrated below with reference to attached drawing.
Substrate, the substrate include neighbouring first crystal area under control I and second transistor area II.
The first transistor region I and second transistor region II are used to form transistor.
It should be noted that the substrate includes a first crystal area under control I and a second transistor in the present embodiment
Area II.In other embodiments, the substrate can also include multiple first crystal areas under control and multiple second transistor areas.
In the present embodiment, the substrate includes: substrate 200 and multiple fins 201 positioned at 200 surface of substrate；Positioned at institute
The separation layer 202 on 200 surface of substrate between fin 201 is stated, the separation layer 202 covers 201 partial sidewall of fin.The isolation
Layer 202 is for realizing the electrical isolation between adjacent fin 201.
The fin 201 is arranged in parallel in first crystal area under control I and second transistor area II, and the fin 201 prolongs
Stretch the line of demarcation for being oriented parallel to first crystal area under control I and second transistor area II.
In the present embodiment, the first crystal area under control I substrate and second transistor area II substrate include 4 fins 201.
In other embodiments, first crystal area under control substrate and second transistor area substrate can also include the fin of other quantity
Portion.
In other embodiments, the substrate can also include the oxide layer between substrate and fin.
In the present embodiment, the material of the substrate 200 is silicon, and the material of the fin 201 is silicon.In other embodiments
In, the material of the substrate and fin can also be germanium.
Neighbouring the first P doped region 231 and the first N doped region 232 in the first crystal area under control I substrate.
Neighbouring the 2nd P doped region and the 2nd N doped region, the first P in the second transistor area II substrate
Doped region 231 and the 2nd N doped region be neighbouring or the first N doped region 232 and the 2nd P doped region it is neighbouring, or
The first P the doped region 231 neighbouring and described first N doped region 232 and the 2nd P doped region with the 2nd N doped region
It is neighbouring.
There is neighbouring the first P doped region 231 and the first N doped region 232, the second crystal in the I substrate of first crystal area under control
There is neighbouring the 2nd P doped region and the 2nd N doped region in the II substrate of area under control.In electrostatic discharge protector conducting, the first P
It is capable of forming between doped region 231 and the first N doped region 232 and between the 2nd P doped region and the 2nd N doped region conductive logical
Road, to realize the release to electrostatic.In addition, the first P doped region 231 and the 2nd N doped region are neighbouring or described the
One N doped region 232 and the 2nd P doped region are neighbouring, alternatively, the first P doped region 231 and the 2nd N doping
Area is neighbouring and the first N doped region 232 and the 2nd P doped region are neighbouring, then can also be in the first P doped region 231
Between the 2nd N doped region or between the first N doped region 232 and the 2nd P doped region or the first P is adulterated
It is formed between area 231 and the 2nd N doped region and between the first N doped region 232 and the 2nd P doped region conductive logical
Road reduces the current density in ESD protection circuit, to reduce electric current to electrostatic to increase the channel of Electro-static Driven Comb
The damage of discharge prevention device.
It include multiple alternately arranged first P doped regions in the first transistor region I fin 201 in the present embodiment
231 and the first N doped region 232.The first crystal area under control I substrate includes multiple fins 201, therefore, the first transistor
Area I includes the alternately arranged first P doped region 231 of multirow and the first N doped region 232.
It include multiple alternately arranged 2nd P doped regions in the second transistor region II fin 201 in the present embodiment
With the 2nd N doped region.The first crystal area under control I substrate includes multiple fins 201, therefore, the second transistor area II packet
Include the alternately arranged 2nd P doped region of multirow and the 2nd N doped region.
It should be noted that the first P doped region 231 is along 201 direction of fin and perpendicular to fin in the present embodiment
Arrangement forms the matrix of multiple lines and multiple rows on 201 direction；The first N doped region 232 is along 201 direction of fin and perpendicular to fin
Arrangement forms the matrix of multiple lines and multiple rows on 201 direction.
In the present embodiment, the 2nd P doped region arranges shape on the direction along 201 direction of fin and perpendicular to fin 201
At the matrix of multiple lines and multiple rows；It arranges and is formed on direction of the 2nd N doped region along 201 direction of fin and perpendicular to fin 201
The matrix of multiple lines and multiple rows.And the first P doped region 231 of the 2nd N doped region of second transistor area II and the first transistor region I
On the same straight line perpendicular to fin 201；The of the 2nd P doped region of second transistor area II and first crystal area under control I
One N doped region 232 is on the same straight line perpendicular to fin 201.
In the present embodiment, between the first P doped region 231 and the first N doped region 232 and the 2nd P doped region and
There is fin 201 between two N doped regions.In other embodiments, the first P doped region 231 and the first N doped region 232 are gone back
It can be in contact；Or the 2nd be in contact between P doped region and the 2nd N doped region；Or the first P doped region 231 and
One N doped region 232 is in contact and the 2nd P doped region and the 2nd N doped region are in contact.
The electrostatic discharge protector further include: be located at the first P doped region 231, the first N doped region 232, second
The electrode of P doped region and the 2nd N doped region surface.
Electrode positioned at the first P doped region 231 and the 2nd P doped region surface is anode, is located at 232 He of the first N doped region
The electrode on the 2nd N doped region surface is cathode.
In the present embodiment, shared in the I of the first transistor region perpendicular to the first P doped region 231 on the straight line of fin 201
One anode forms the first anode 211；Perpendicular to the first N doped region on the straight line of fin 201 in the I of the first transistor region
232 share a cathode, form the first cathode 212.
In addition, sharing a sun perpendicular to the 2nd P doped region on the straight line of fin 201 in the II of second transistor region
Pole forms second plate 221；One is shared perpendicular to the 2nd N doped region on the straight line of fin 201 in the II of second transistor region
A cathode forms the second cathode 222.
In the present embodiment, the first anode 211 of the first transistor region I and the first cathode 212 are alternately arranged；Described second
The second plate 221 of transistor area II and the second cathode 222 are alternately arranged；First crystal area under control I and second transistor area II
The type of adjacent electrode is different.Therefore, in the present embodiment, when the electrostatic discharge protector at work, anode connects quiet
Electricity, minus earth.When amount of electrostatic charge is run up to it is a certain amount of when, anode voltage increase, electrostatic discharge protector is connected, first
Partial electrostatic lotus in anode 211 reaches the first cathode 212 by fin 201 from the first P doped region 231, finally imports underground；The
Partial electrostatic lotus in one anode 211 is from the first anode 211 through the first transistor region I fin 201 and second transistor region
Substrate 200 between II fin 201 reaches the second cathode 222 of second transistor area II, finally imports underground.Meanwhile second
When the amount of electrostatic charge of anode 221 runs up to a certain amount of, anode voltage is increased, and electrostatic discharge protector is connected, second plate
Partial electrostatic lotus in 221 reaches the second cathode 232 by fin 201 from the 2nd P doped region 231, finally imports underground；Second sun
Partial electrostatic lotus in pole 221 is from second plate 221 through the first transistor region I fin 201 and second transistor region II fin
Substrate 200 between portion 201 reaches the first cathode 212 of first crystal area under control I, finally imports underground.It can be seen that of the invention
Electrostatic discharge protector in, the electrostatic of anode accumulation may pass through two conductive paths and be released, conductive path compared with
More, the current density in electrostatic discharge protector is small, and electrostatic discharge protector is not easy to be damaged.
It should be noted that the electrostatic discharge protector further includes being located at the first P doped region in the present embodiment
231 and the first 200 surface of substrate and the base between the 2nd P doped region and the 2nd N doped region between N doped region 232
The gate structure 230 on 200 surface of bottom.The gate structure 230 can be used in applying voltage in electrostatic discharge protector
Electric current is controlled.But in other implementations, the electrostatic discharge protector can also not have the gate structure.
Fig. 4 and Fig. 5 is the structural schematic diagram of the another embodiment of electrostatic discharge protector of the invention.
Fig. 4 and Fig. 5 are please referred to, Fig. 5 is cross-sectional view of the Fig. 4 along 2-2 '.The something in common of the present embodiment and previous embodiment
This will not be repeated here, and difference includes:
The electrostatic discharge protector does not have gate structure, the first P doped region 431 and the first N doped region 432
Between and the fin 401 between the 2nd P doped region and the 2nd N doped region in have isolation structure 430, the isolation structure
430 can be realized between the first P doped region 431 and the first N doped region 432 and between the 2nd P doped region and the 2nd N doped region
Electrical isolation, to make electric current reach cathode by the substrate 400 of 430 lower section of the isolation structure from anode, to increase
The length of the conductive channel of electric current can be such that the electric field strength in conducting channel reduces, and energy density caused by electric current is low, compared with
Damage of the low current to electrostatic discharge protector.
It should be noted that in the present embodiment, between the first P doped region 431 and the first N doped region 432 and
Isolation structure is all had between two P doped regions and the 2nd N doped region.In other embodiments, can also only the first P doped region and
There is isolation structure between first N doped region；There is fin and gate structure between 2nd P doped region and the 2nd N doped region.Or
Person, the 2nd P doped region and the 2nd N doped region have isolation structure；There is fin between first P doped region and the first N doped region
And gate structure.
In the present embodiment, the first anode 411 in the first transistor region and the first cathode 412 are alternately arranged；Described second
The second plate 421 of transistor area and the second cathode 422 are alternately arranged；First crystal area under control is adjacent with second transistor area
The type of electrode is different.Therefore, in the present embodiment, when the electrostatic discharge protector at work, anode connects electrostatic, cathode
Ground connection.When amount of electrostatic charge is run up to it is a certain amount of when, anode voltage increase, electrostatic discharge protector is connected, the first anode 411
Interior partial electrostatic lotus reaches the first cathode 412 by the substrate 400 of 430 lower section of isolation structure from the first P doped region 431, finally
Import underground；Partial electrostatic lotus in the first anode 411 is from the first anode 411 through the first transistor region fin 401 and second
Substrate 400 between transistor area fin 401 reaches second cathode 422 in second transistor area, finally imports underground.Together
When, when the amount of electrostatic charge of second plate 421 runs up to a certain amount of, anode voltage is increased, and electrostatic discharge protector is connected, the
Partial electrostatic lotus in two anodes 421 reaches the second cathode by the substrate 400 of 430 lower section of isolation structure from the 2nd P doped region
422, finally import underground；Partial electrostatic lotus in second plate 421 is from second plate 421 through the first transistor region fin
Substrate 400 between 401 and second transistor region fin 401 reaches first cathode 412 in first crystal area under control, final to import
Underground.It can be seen that the electrostatic of anode accumulation may pass through two conductive paths in electrostatic discharge protector of the invention
Be released, conductive path is more, and the current density in electrostatic discharge protector is small, electrostatic discharge protector be not easy by
Damage.
In the present embodiment, the material of the isolation structure 430 is silica, and silica can glue well with silicon base
It is attached.In other embodiments, the material of the isolation structure may be silicon oxynitride.
To sum up, in electrostatic discharge protector of the invention, there is the first neighbouring P in the substrate of the first crystal area under control
Doped region and the first N doped region have neighbouring the 2nd P doped region and the 2nd N doped region in second transistor area substrate,
Therefore, can be between the first P doped region and the first N doped region when electrostatic discharge protector is connected, the 2nd P mixes
Conductive channel is formed between miscellaneous area and the 2nd N doped region, realizes the release to electrostatic.In addition, the first P doped region with it is described
2nd N doped region is neighbouring or the first N doped region and the 2nd P doped region are neighbouring or the first P doped region and institute
State that the 2nd N doped region is neighbouring and the first N doped region and the 2nd P doped region are neighbouring.Therefore, electrostatic discharge protector
When conducting, additionally it is possible between the first P doped region and the 2nd N doped region or the first N doped region and the 2nd P doped region it
Between or the first P doped region and the 2nd N doped region between and the first N doped region and the 2nd P doped region between formed and lead
Electric pathway increases the path of Electro-static Driven Comb.Therefore, the electrostatic discharge protector has more Electro-static Driven Comb path, energy
The current density in electrostatic discharge protector is enough reduced, the excessive damage generated to electrostatic discharge protector of current density is reduced
Wound.
Further, there is isolation structure or the 2nd P doped region in the fin between the first P doped region and the first N doped region
And the 2nd have between N doped region between isolation structure or the first P doped region and the first N doped region and the 2nd P doped region
And the 2nd have isolation structure between N doped region, the isolation structure can be realized the first P doped region and the first N doped region or
Electric isolution between 2nd P doped region and the 2nd N doped region, can make electric current by anode by the substrate below isolation structure to
Up to cathode, to increase the length of current channel, current density is reduced, and then reduce electric current to electrostatic discharge protector
Damage.
Correspondingly, the present invention also provides a kind of forming methods of electrostatic discharge protector, comprising:
Substrate is formed, the substrate includes neighbouring first crystal area under control and second transistor area；
The first P doped region is formed in the substrate of the first crystal area under control, and forms in second transistor area substrate the
Two P doped regions；
The first N doped region is formed in the substrate of the first crystal area under control, and forms in second transistor area substrate the
Two N doped regions, the first P doped region are mixed adjacent to the 2nd N doped region or the first N doped region adjacent to the 2nd P
Miscellaneous area, the first P doped region is adjacent to the 2nd N doped region, and the first N doped region is adjacent to the 2nd P doped region；
Anode is formed in the first P doped region and the 2nd P doped region surface；
Cathode is formed in the first N doped region and the 2nd N doped region surface.
Referring to FIG. 6, forming substrate, the substrate includes neighbouring first crystal area under control M and second transistor area N.
It should be noted that the substrate includes a first crystal area under control M and a second transistor in the present embodiment
Area N.In other embodiments, the substrate can also include multiple first crystal areas under control and multiple second transistor areas.
In the present embodiment, formed substrate the step of include: offer initial substrate；The initial substrate is patterned,
Form substrate and multiple fins 501 on substrate；Separation layer 502 is formed on substrate between the fin 501, it is described
Separation layer 502 covers 501 partial sidewall of fin, for realizing the electrical isolation between adjacent fin 501.
In the present embodiment, the fin 501 is arranged in parallel in first crystal area under control M and second transistor area N, and the fin
The extending direction in portion 501 is parallel to the line of demarcation of first crystal area under control M and second transistor area N.
In the present embodiment, the first crystal area under control M substrate and second transistor area N substrate include 4 fins 501.
In other embodiments, first crystal area under control substrate and second transistor area substrate can also include the fin of other quantity
Portion.
In the present embodiment, the material of the substrate is silicon, and the material of the fin 501 is silicon.In other embodiments, institute
The material for stating substrate and fin can also be germanium.
Referring to FIG. 7, in the present embodiment, after substrate is provided, the forming method further include: be developed across the fin
501 multiple gate structures 510, the gate structure 510 cover the 501 part side of fin perpendicular to the fin 501
Wall and top surface.The gate structure 510 is for controlling the electric current in the electrostatic discharge protector.
In other embodiments, the forming method can not also include: the gate structure for being developed across the fin 501
510。
Fig. 8 and Fig. 9 are please referred to, forms the first P doped region 511 in the first crystal area under control M substrate, and in the second crystalline substance
The 2nd P doped region 521 is formed in the N substrate of body area under control.
In the present embodiment, the step of forming the first P doped region 511 and the 2nd P doped region 512 further include: provide the
One light shield 540, first light shield 540 have the first figure, and first figure is mixed with the first P doped region and the 2nd P
The position in miscellaneous area is corresponding；It is that exposure mask carries out ion implanting to the substrate with first light shield 540, forms the first P doped region
511 and the 2nd P doped region.
In the present embodiment, first light shield 540 includes corresponding with the first P doped region 511 of the first transistor region M
One P doped region figure 541；The 2nd P doped region figure 542 corresponding with the 2nd P doped region 521 of second transistor region N.It is described
First P doped region figure 541 and the 2nd P doped region figure 542 are the strip being arranged in the horizontal direction, and the first P is adulterated
Area's figure 541 and the 2nd P doped region figure 542 mutually stagger.
In the present embodiment, by directly carrying out ion implanting to the substrate, forms the first P doped region 511 and the 2nd P mixes
Miscellaneous area 521.In other embodiments, the first P doped region and the 2nd P doped region can also be formed by doping process in situ.
In conjunction with reference Figure 10, the first N doped region 512 is formed in the first crystal area under control M substrate, and in the second crystal
The 2nd N doped region 522 is formed in the N substrate of area under control, the first P doped region 511 is adjacent to the 2nd N doped region 522 or described
First N doped region 512 is adulterated adjacent to the 2nd P doped region 521 or the first P doped region 511 adjacent to the 2nd N
Area 522, and the first N doped region 512 is adjacent to the 2nd P doped region 521.
The step of forming the first N doped region 512 and the 2nd N doped region 522 further include: the second light shield is provided, it is described
Second light shield has second graph, the position pair of the second graph and the first the N doped region 512 and the 2nd N doped region 522
It answers；Ion implanting is carried out to the substrate using second light shield as exposure mask, forms the first N doped region 512 and the 2nd N doped region
522。
In the present embodiment, the arrangement mode and the first P doped region of the first N doped region 521, the 2nd N doped region 522
511, the 2nd P doped region 521 is identical.Therefore, during forming the first N doped region 512 and the 2nd N doped region 522, second
Light shield is identical as the first light shield.In the present embodiment, the first light shield 540 is rotated into 180 degree as the second light shield to base along horizontal line
Bottom carries out ion implanting.
In the present embodiment, by directly carrying out ion implanting to the substrate, forms the first N doped region 512 and the 2nd N mixes
Miscellaneous area 522.In other embodiments, the first N doped region and the 2nd N doped region can also be formed by doping process in situ.
In the present embodiment, the first P doped region 511 of formation and the first N doped region 512 are alternately arranged；The 2nd P formed mixes
Miscellaneous area 521 and the 2nd N doped region 522 are alternately arranged.And the first P doped region 511 it is adjacent with the 2nd N doped region 522, the first N mixes
Miscellaneous area 512 is adjacent with the 2nd P doped region 521.
In the present embodiment, there is neighbouring the first P doped region 511 and the first N doped region in the M substrate of first crystal area under control
512, there is in second transistor area N substrate neighbouring the 2nd P doped region 521 and the 2nd N doped region 522.It is protected in static discharge
Protect break-over of device when, between the first P doped region 511 and the first N doped region 512 and the 2nd P doped region 521 and the 2nd N doping
It is capable of forming conductive channel between area 522, to realize the release to electrostatic.In addition, the first P doped region 511 with it is described
2nd N doped region 522 is neighbouring and the first N doped region 512 and the 2nd P doped region 521 it is neighbouring, then can also be
Between the first P doped region 511 and the 2nd N doped region 522 and the first N doped region 512 and the 2nd P doped region
Conductive channel is formed between 521, so that electrostatic be made further to discharge, is increased the conductive channel of Electro-static Driven Comb, is reduced static discharge
The current density in device is protected, to reduce damage of the electric current to electrostatic discharge protector.
It include multiple alternately arranged first P doped regions in the first transistor region M fin 501 in the present embodiment
511 and the first N doped region 512.The first crystal area under control M substrate includes multiple fins 501, therefore, the first transistor
Area M includes the alternately arranged first P doped region 511 of multirow and the first N doped region 512.
Figure 11 is please referred to, in the first P doped region 511 (as shown in Figure 9) and the 2nd P doped region 521 (as shown in Figure 9)
Surface forms anode 520；In the first N doped region 512 (as shown in Figure 10) and the 2nd N doped region 522 (as shown in Figure 10) surface
Form cathode 530.
The forming method of the anode and cathode is same as the prior art, is not repeating them here.
Figure 12 and Figure 13 is the structure of each step of the another embodiment of forming method of electrostatic discharge protector of the invention
Implement figure.
The present embodiment and the something in common of a upper embodiment do not repeat herein, and difference includes: to form fin 601
Later, the graphical fin 601 forms groove 630；Isolation structure 610 is formed in the groove 630.
Figure 12 is please referred to, is formed after fin 601, the forming method of the electrostatic discharge protector includes: graphical
The fin 601 forms the multiple grooves 630 for running through the first transistor region X and second transistor region Y fin 601, described
Groove 630 is perpendicular to fin 601.
In the present embodiment, the groove 630 exposes substrate surface, therefore, can make the fin of 630 two sides of groove
601 is completely separable, to make after forming electrostatic discharge protector, electric current mainly passes through from the substrate of 630 bottom of groove, from
And increase the length of conductive channel.
Figure 13 is please referred to, the isolation structure 610 being filled in the groove 630 (with reference to Figure 12) is formed.
In the present embodiment, the material of the isolation structure 610 is silica.
In the present embodiment, the technique for forming the isolation structure 610 includes: that chemical vapor deposition process and chemical machinery are ground
Grinding process.
To sum up, in the forming method of electrostatic discharge protector of the invention, make the first P doped region adjacent to described
Two N doped regions or the first N doped region are adjacent to the 2nd P doped region, or keep the first P doped region neighbouring described
2nd N doped region, and the first N doped region is adjacent to the 2nd P doped region.It, can when electrostatic discharge protector is connected
Increase the conduction between the first P doped region and the 2nd N doped region or between the first N doped region and the 2nd P doped region
Access increases the path of Electro-static Driven Comb.Therefore, it can reduce the current density in electrostatic discharge protector, it is close to reduce electric current
It spends and damage is generated to the electrostatic discharge protector greatly.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (17)
1. a kind of electrostatic discharge protector characterized by comprising
Substrate, the substrate include neighbouring first crystal area under control and second transistor area；
Neighbouring the first P doped region and the first N doped region in the substrate of first crystal area under control；
The 2nd P doped region and the 2nd N doped region in second transistor area substrate, the first P doped region and described the
The neighbouring perhaps described first N doped region of two N doped regions and the 2nd P doped region be neighbouring or the first P doped region with
The 2nd N doped region is neighbouring and the first N doped region and the 2nd P doped region are neighbouring；
Positioned at the anode of the first P doped region and the 2nd P doped region surface；
Positioned at the cathode of the first N doped region and the 2nd N doped region surface.
2. electrostatic discharge protector as described in claim 1, which is characterized in that the substrate include substrate and be located at substrate
On fin；
The first P doped region, the first N doped region, the 2nd P doped region and the 2nd N doped region are located in the fin.
3. electrostatic discharge protector as claimed in claim 2, which is characterized in that the first P doped region and the first N doping
There is fin between area.
4. electrostatic discharge protector as claimed in claim 2 or claim 3, which is characterized in that the 2nd P doped region and the 2nd N
There is fin between doped region.
5. electrostatic discharge protector as claimed in claim 2, which is characterized in that the first P doped region and the first N doping
There is isolation structure in fin between area.
6. the electrostatic discharge protector as described in claim 2 or 5, which is characterized in that the 2nd P doped region and the 2nd N
There is isolation structure in fin between doped region.
7. electrostatic discharge protector as claimed in claim 5, which is characterized in that the material of the isolation structure is oxidation
Silicon.
8. electrostatic discharge protector as described in claim 1, which is characterized in that the first P doped region and the first N doping
Area's contact；The 2nd P doped region and the contact of the 2nd N doped region.
9. electrostatic discharge protector as described in claim 1, which is characterized in that further include: it is located at the first P doped region
And the first substrate surface between N doped region gate structure.
10. the electrostatic discharge protector as described in claim 1 or 9, which is characterized in that further include: it is mixed positioned at the 2nd P
The gate structure of substrate surface between miscellaneous area and the 2nd N doped region.
11. a kind of forming method of electrostatic discharge protector characterized by comprising
Substrate is formed, the substrate includes neighbouring first crystal area under control and second transistor area；
The first P doped region is formed in the substrate of the first crystal area under control；
The 2nd P doped region is formed in second transistor area substrate；
The first N doped region of neighbouring first P doped region is formed in the substrate of the first crystal area under control；
The 2nd N doped region of neighbouring 2nd P doped region is formed in second transistor area substrate, the first P doped region is neighbouring
Perhaps the first N doped region is adjacent adjacent to the 2nd P doped region or the first P doped region for the 2nd N doped region
The nearly 2nd N doped region, and the first N doped region is adjacent to the 2nd P doped region；
Anode is formed in the first P doped region and the 2nd P doped region surface；
Cathode is formed in the first N doped region and the 2nd N doped region surface.
12. the forming method of electrostatic discharge protector as claimed in claim 11, which is characterized in that form the first P
The step of doped region and the 2nd P doped region includes: to provide the first light shield, and first light shield includes and the first P doped region and the
Corresponding first figure of two P doped regions；Ion implanting is carried out to the substrate using first light shield as exposure mask, forms the first P
Doped region and the 2nd P doped region；
The step of forming the first N doped region and the 2nd N doped region includes: to provide the second light shield, and second light shield includes
Second graph corresponding with the first N doped region and the 2nd N doped region；Using second light shield as exposure mask to the substrate carry out from
Son injection, forms the first N doped region and the 2nd N doped region.
13. the forming method of electrostatic discharge protector as claimed in claim 11, which is characterized in that the step of forming substrate
It include: offer initial substrate；The initial substrate is patterned to form substrate and the fin on substrate；
The fin connects the first P doped region and the first N doped region, and the fin is also connected with the 2nd P doped region and the 2nd N doping
Area.
14. the forming method of electrostatic discharge protector as claimed in claim 11, which is characterized in that formed the substrate it
Afterwards, the forming method further include: form gate structure in the substrate surface；
The first P doped region and the first N doped region are located in the substrate of the gate structure two sides；
The 2nd P doped region and the 2nd N doped region are located in the substrate of the gate structure two sides.
15. the forming method of electrostatic discharge protector as claimed in claim 11, which is characterized in that the step of forming substrate
It include: offer initial substrate；The initial substrate is patterned, substrate and the fin on substrate are formed；
It is formed after substrate, the forming method further include: the graphical fin forms groove in the fin；Institute
It states and forms isolation structure in groove；
The first P doped region and the first N doped region are located in the substrate of the isolation structure two sides；
The 2nd P doped region and the 2nd N doped region are located in the substrate of the isolation structure two sides.
16. the forming method of electrostatic discharge protector as claimed in claim 15, which is characterized in that the groove exposes
The substrate.
17. the forming method of electrostatic discharge protector as claimed in claim 15, which is characterized in that the isolation structure
Material is silica.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610134352.5A CN107180817B (en) | 2016-03-09 | 2016-03-09 | Electrostatic discharge protector and forming method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610134352.5A CN107180817B (en) | 2016-03-09 | 2016-03-09 | Electrostatic discharge protector and forming method thereof |
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| CN107180817B true CN107180817B (en) | 2019-05-28 |
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| KR20040041149A (en) * | 2001-07-05 | 2004-05-14 | 사르노프 코포레이션 | Electrostatic discharge(esd)protection device with simultaneous and distributed self-biasing for multi-finger turn-on |
| KR100431066B1 (en) * | 2001-09-27 | 2004-05-12 | 삼성전자주식회사 | Semiconductor device having electro-static discharge circuit |
| KR100772097B1 (en) * | 2005-06-11 | 2007-11-01 | 주식회사 하이닉스반도체 | Electrostatic protection device for semiconductor circuit |
| CN104078459B (en) * | 2013-03-28 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic preventing structure and electrostatic discharge protective circuit |
| US9947659B2 (en) * | 2014-05-27 | 2018-04-17 | Mediatek Inc. | Fin field-effect transistor gated diode |
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