CN107180793A - 一种调节高k金属栅cmos器件阈值的方法 - Google Patents
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- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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Abstract
本发明公开了一种调节高K金属栅CMOS器件阈值的方法,包括:提供衬底,所述衬底包括NMOS区域和PMOS区域,所述NMOS区域和所述PMOS区域上均设置有金属栅叠层;沉积掺杂有掺杂原子的牺牲层;退火扩散所述牺牲层中的掺杂原子,使所述掺杂原子扩散进入所述金属栅叠层;去除所述牺牲层。本发明提供的方法,用以解决现有技术中高K金属栅CMOS器件阈值调节工艺存在的可控性差,并且临近界面易造成对沟道的工艺损伤的技术问题。实现了简化功函数调节工艺,减少对沟道的工艺损伤的技术效果。
Description
技术领域
本发明涉及半导体集成技术领域,尤其涉及一种调节高K金属栅CMOS器件阈值的方法。
背景技术
调节高K金属栅CMOS器件阈值的现有方法是:NMOS和PMOS的金属栅先沉积阻挡层和沉积PMOS功函数层(PMOS WFL),再去除NMOS区域的PMOS WFL和调节NMOS区域的阻挡层厚度以调节NMOS阈值,再变化PMOS区域的PMOS WFL的厚度以调节PMOS阈值;再沉积NMOS功函数层(NMOS WFL)。
由于现有方法中NMOS和PMOS的金属栅功函数阈值的厚度调节都基于阻挡层和PMOS WFL的TiNx基材料的腐蚀,可控性差,并且临近界面易造成对沟道的工艺损伤。
发明内容
本申请实施例通过提供一种调节高K金属栅CMOS器件阈值的方法,解决了现有技术中高K金属栅CMOS器件阈值调节工艺存在的可控性差,并且临近界面易造成对沟道的工艺损伤的技术问题。
为解决上述技术问题,本发明的实施例提供了如下技术方案:
一种调节高K金属栅CMOS器件阈值的方法,包括:
提供衬底,所述衬底包括NMOS区域和PMOS区域,所述NMOS区域和所述PMOS区域上均设置有金属栅叠层;
沉积掺杂有掺杂原子的牺牲层;
退火扩散所述牺牲层中的掺杂原子,使所述掺杂原子扩散进入所述金属栅叠层;
去除所述牺牲层。
可选的,所述衬底上设置有阻挡层、功函数层和填充层。
可选的,所述沉积掺杂有掺杂原子的牺牲层,包括:在以下任一层上沉积掺杂有掺杂原子的牺牲层:所述阻挡层、所述功函数层或所述填充层。
可选的,所述阻挡层包括第一阻挡层和第二阻挡层,所述沉积掺杂有掺杂原子的牺牲层,包括:在所述第一阻挡层或所述第二阻挡层上沉积所述牺牲层。
可选的,所述功函数层包括NMOS功函数层和/或PMOS功函数层,所述沉积掺杂有掺杂原子的牺牲层,包括:在所述NMOS功函数层和/或所述PMOS功函数层上沉积所述牺牲层。
可选的,所述牺牲层包含以下材料中的至少一种或多种的组合:氧化物、low-k材料、氮化物、有机物、非晶碳。
可选的,所述掺杂原子包含以下至少一种或多种的组合:B、P、As、活性或过渡金属原子、中性原子。
可选的,所述活性或过渡金属原子包含以下至少一种或多种的组合:Al、Ga、In、Sb、Co、Ti、Ni、Zr、Hf、Mo、La、Ta;所述中性原子包含以下至少一种或多种的组合:C、Si、S、Ge。
可选的,所述退火扩散所述牺牲层中的掺杂原子的方法,包括以下任意一种或多种的组合:炉管退火、快速热退火或激光退火。
可选的,所述去除所述牺牲层的方法,包括以下任意一种或多种的组合:干法腐蚀、湿法腐蚀、灰化或剥离。
本申请实施例中提供的一个或多个技术方案,至少具有如下技术效果或优点:
本申请实施例提供的调节高K金属栅CMOS器件阈值的方法,通过在衬底的金属栅上沉积掺杂有掺杂原子的牺牲层,然后采用退火工艺,使得掺杂原子扩散到下方的金属栅中,从而改变金属栅的功函数,不需要改变器件结构来进行膜厚调节,简化了功函数调节工艺,可有效避免膜厚控制对沟道的工艺损伤。
附图说明
为了更清楚地说明本发明实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据提供的附图获得其他的附图。
图1为本申请实施例中调节高K金属栅CMOS器件阈值的方法的流程图;
图2为本申请实施例中高K金属栅CMOS器件的剖面结构示意图;
图3为本申请实施例中在第一阻挡层上沉积牺牲层的剖面结构示意图;
图4为本申请实施例中在功函数层上沉积牺牲层的剖面结构示意图;
图5为本申请实施例中在第二阻挡层上沉积牺牲层的剖面结构示意图;
图6为本申请实施例中在填充层上沉积牺牲层的剖面结构示意图。
具体实施方式
本申请实施例通过提供一种调节高K金属栅CMOS器件阈值的方法,解决了现有技术中高K金属栅CMOS器件阈值调节工艺存在的可控性差,并且临近界面易造成对沟道的工艺损伤的技术问题。实现了简化功函数调节工艺,减少对沟道的工艺损伤的技术效果。
为解决上述技术问题,本申请实施例提供技术方案的总体思路如下:
一种调节高K金属栅CMOS器件阈值的方法,包括:
提供衬底,所述衬底包括NMOS区域和PMOS区域,所述NMOS区域和所述PMOS区域上均设置有金属栅叠层;
沉积掺杂有掺杂原子的牺牲层;
退火扩散所述牺牲层中的掺杂原子,使所述掺杂原子扩散进入所述金属栅叠层;
去除所述牺牲层。
本申请实施例提供方法,通过在衬底的金属栅上沉积掺杂有掺杂原子的牺牲层,然后采用退火工艺,使得掺杂原子扩散到下方的金属栅中,从而改变金属栅的功函数,不需要改变器件结构来进行膜厚调节,简化了功函数调节工艺,可有效避免膜厚控制对沟道的工艺损伤。
为了更好的理解上述技术方案,下面将结合具体的实施方式对上述技术方案进行详细说明,应当理解本发明实施例以及实施例中的具体特征是对本申请技术方案的详细的说明,而不是对本申请技术方案的限定,在不冲突的情况下,本申请实施例以及实施例中的技术特征可以相互组合。
在本实施例中,提供一种调节高K金属栅CMOS器件阈值的方法,如图1所示,包括:
步骤S101,提供衬底,所述衬底包括NMOS区域和PMOS区域,所述NMOS区域和所述PMOS区域上均设置有金属栅叠层;
步骤S102,沉积掺杂有掺杂原子的牺牲层;
步骤S103,退火扩散所述牺牲层中的掺杂原子,使所述掺杂原子扩散进入所述金属栅叠层;
步骤S104,去除所述牺牲层。
下面,结合图1来详细介绍本申请提供方法的详细步骤:
步骤S101,提供衬底100,所述衬底包括NMOS区域和PMOS区域,所述NMOS区域和所述PMOS区域上均设置有金属栅叠层101;
具体来讲,金属栅叠层为鳍片结构。
在本申请实施例中,如图2所示,所述衬底的鳍片上有底层至顶层的方向可以依次设有隔离层/高k介质层200、第一阻挡层300、功函数层400、第二阻挡层500、以及填充层600。
所述第一阻挡层300包含以下材料中的至少一种或多种的组合:TiN、TaN、TiNx、TaNx、TiNSi。
所述功函数层400包括:NMOS功函数层(WFL)和/或PMOS功函数层(WFL)。所述PMOSWFL,其包含以下材料中的至少一种或多种的组合:TiN、TaN、TiNx、TaNx、TiNSi。所述NMOSWFL,其包含以下材料中的至少一种或多种的组合:Al、TiAl、TiAlx、TiAlCx、TiCx、TaCx。
所述第二阻挡层500包含以下材料中的至少一种或多种的组合:TiN、TaN、TiNx、TaNx、TiNSi。
所述填充层600,的材质选自:Co、Ni、Cu、Al、Pd、Pt、Ru、Re、Mo、Ta、Ti、Hf、Zr、W、Ir、Eu、Nd、Er、La的金属单质、或这些金属的合金以及这些金属的氮化物。
步骤S102,沉积掺杂有掺杂原子的牺牲层1。
在具体实施过程中,沉积所述牺牲层1的位置可以根据需要确定,下面列举3种为例:
第一种,在阻挡层上沉积所述牺牲层1。
具体来讲,即如图3和图4所示,在所述第一阻挡层300沉积后沉积所述牺牲层1,或在所述第二阻挡层500沉积后沉积所述牺牲层1。
第二种,在功函数层400上沉积所述牺牲层1。
具体来讲,即如图5所示,在所述NMOS功函数层和/或所述PMOS功函数层上沉积所述牺牲层。
第三种,在填充层600上沉积所述牺牲层1。
具体来讲,即如图6所示,在所述填充层600上沉积所述牺牲层。
当然,在具体实施过程中,可以根据需要选择在哪个工艺步骤或哪一层上沉积所述牺牲层,在此不作限制,也不再一一列举。
在本申请实施例中,所述牺牲层1包含以下材料中的至少一种或多种的组合:氧化物、low-k材料、氮化物、有机物、非晶碳。
具体来讲,所述牺牲层的上述材料设置能便于掺杂原子和利于牺牲层的去除。
在本申请实施例中,所述掺杂原子包含以下至少一种或多种的组合:B、P、As、活性或过渡金属原子、中性原子。
进一步,所述活性或过渡金属原子包含以下至少一种或多种的组合:Al、Ga、In、Sb、Co、Ti、Ni、Zr、Hf、Mo、La、Ta;
进一步,所述中性原子包含以下至少一种或多种的组合:C、Si、S、Ge。
具体来讲,设置不同的掺杂原子及掺杂浓度,会对功函数产生不同的影响。
接下来,执行步骤S103,退火扩散所述牺牲层1中的掺杂原子,使所述掺杂原子扩散进入所述金属栅叠层101。
在本申请实施例中,所述退火扩散所述牺牲层1中的掺杂原子的方法,包括以下任意一种或多种的组合:
炉管退火、快速热退火或激光退火。
再下来,执行步骤S104,去除所述牺牲层1。
在本申请实施例中,所述去除所述牺牲层1的方法,包括以下任意一种或多种的组合:干法腐蚀、湿法腐蚀、灰化、剥离及化学反应等。
具体来讲,通过在衬底的金属栅上沉积掺杂有掺杂原子的牺牲层,然后采用退火工艺,使得掺杂原子扩散到下方的金属栅中,从而改变金属栅的功函数,该方法不需要改变器件结构,通过调节金属栅掺杂来调节功函数,不用进行膜厚调节,一方面,简化了功函数调节工艺,可有效避免膜厚控制对沟道的工艺损伤,另一方面,可以通过原子掺杂控制功函数调节范围,不受膜厚控制,扩大了调节范围。
在了解了本申请的主要发明点后,下面,以在功函数层400上沉积牺牲层为例,来介绍本实施例的调节高K金属栅CMOS器件阈值的方法的完整工艺流程,具体为鳍式场效应晶体管(Fin Field-Effect Transistor,FinFET)的工艺流程:
首先,在硅衬底上形成鳍片FET;
然后,形成器件隔离区Fin STI;
再在每个假栅极堆叠结构两侧形成栅极侧墙和源漏区。具体步骤为:掺杂形成NMOS和PMOS的阱区和沟道区;形成假栅;形成间隔物(Spacer);NMOS和PMOS的源漏掺杂;NMOS和PMOS的源漏分别选择外延Si和SiGe;NMOS和PMOS的源漏分别掺杂;掺杂退火;
再形成第一层间电解质(ILD 0);第一层间电解质堆叠装配(POP);
去除多个假栅极堆叠结构,在层间介质层中留下多个NMOS栅极沟槽和多个PMOS栅极沟槽;
沉积隔离层/高k介质层200;
接下来,依次沉积第一阻挡层(barrier-1)300和功函数层(WFL)400,所述功函数层包括:NMOS WFL和/或PMOS WFL;
至此,完成步骤S101,提供衬底100,所述衬底100包括NMOS区域和PMOS区域,所述NMOS区域和所述PMOS区域上均设置有金属栅叠层101;
然后,执行步骤S102,如图5所示,沉积掺杂有掺杂原子的牺牲层1;
再执行步骤S103,退火扩散所述牺牲层1中的掺杂原子,使所述掺杂原子扩散进入所述金属栅叠层101;
执行步骤S104,去除所述牺牲层1。
然后,在多个NMOS栅极沟槽和多个PMOS栅极沟槽中依次形成第二阻挡层500、以及填充层600。具体步骤包括:形成第二阻挡层(barrier-Ⅱ)500和钨W导电填充600;高K金属栅叠层化学机械抛光(CMP);其中,所述第二阻挡层500包含以下材料中的至少一种或多种的组合:TiN、TaN、TiNx、TaNx、TiNSi。所述填充层材质优选电阻率低、填充率高的金属,例如Co、Ni、Cu、Al、Pd、Pt、Ru、Re、Mo、Ta、Ti、Hf、Zr、W、Ir、Eu、Nd、Er、La等金属单质、或这些金属的合金以及这些金属的氮化物。其中,CMP平坦化使得金属栅极结构的顶部齐平;
再下来,完成器件互连。具体步骤包括:沉积形成第二层间电解质(ILD 1);形成金属层(CT)和硅化物层(Silicide);形成钨塞(W plug),并化学机械抛光;多层互连;形成钝化层和管脚(Pad)。
当然,在具体实施过程中,也可以是在沉积第一阻挡层300后,先执行步骤S102-S104,再沉积功函数层(WFL)400;还可以是在沉积第二阻挡层500后,先执行步骤S102-S104,再沉积填充层600;还可以是在沉积填充层600后,先执行步骤S102-S104,再完成器件互连,在此不作限制,也不再一一列举。
上述本申请实施例中的技术方案,至少具有如下的技术效果或优点:
本申请实施例提供的调节高K金属栅CMOS器件阈值的方法,通过在衬底的金属栅上沉积掺杂有掺杂原子的牺牲层,然后采用退火工艺,使得掺杂原子扩散到下方的金属栅中,从而改变金属栅的功函数,该方法不需要改变器件结构,通过调节金属栅掺杂来调节功函数,不用进行膜厚调节,一方面,简化了功函数调节工艺,可有效避免膜厚控制对沟道的工艺损伤,另一方面,可以通过原子掺杂控制功函数调节范围,不受膜厚控制,扩大了调节范围。
显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。
Claims (10)
1.一种调节高K金属栅CMOS器件阈值的方法,其特征在于,包括:
提供衬底,所述衬底包括NMOS区域和PMOS区域,所述NMOS区域和所述PMOS区域上均设置有金属栅叠层;
沉积掺杂有掺杂原子的牺牲层;
退火扩散所述牺牲层中的掺杂原子,使所述掺杂原子扩散进入所述金属栅叠层;
去除所述牺牲层。
2.如权利要求1所述的方法,其特征在于,所述衬底上设置有阻挡层、功函数层和填充层。
3.如权利要求2所述的方法,其特征在于,所述沉积掺杂有掺杂原子的牺牲层,包括:
在以下任一层上沉积掺杂有掺杂原子的牺牲层:所述阻挡层、所述功函数层或所述填充层。
4.如权利要求2所述的方法,其特征在于,所述阻挡层包括第一阻挡层和第二阻挡层,所述沉积掺杂有掺杂原子的牺牲层,包括:
在所述第一阻挡层或所述第二阻挡层上沉积所述牺牲层。
5.如权利要求2所述的方法,其特征在于,所述功函数层包括NMOS功函数层和/或PMOS功函数层,所述沉积掺杂有掺杂原子的牺牲层,包括:
在所述NMOS功函数层和/或所述PMOS功函数层上沉积所述牺牲层。
6.如权利要求1所述的方法,其特征在于,所述牺牲层包含以下材料中的至少一种或多种的组合:氧化物、low-k材料、氮化物、有机物、非晶碳。
7.如权利要求1所述的方法,其特征在于,所述掺杂原子包含以下至少一种或多种的组合:B、P、As、活性或过渡金属原子、中性原子。
8.如权利要求7所述的方法,其特征在于,
所述活性或过渡金属原子包含以下至少一种或多种的组合:Al、Ga、In、Sb、Co、Ti、Ni、Zr、Hf、Mo、La、Ta;
所述中性原子包含以下至少一种或多种的组合:C、Si、S、Ge。
9.如权利要求1所述的方法,其特征在于,所述退火扩散所述牺牲层中的掺杂原子的方法,包括以下任意一种或多种的组合:
炉管退火、快速热退火或激光退火。
10.如权利要求1所述的方法,其特征在于,所述去除所述牺牲层的方法,包括以下任意一种或多种的组合:干法腐蚀、湿法腐蚀、灰化或剥离。
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108493157A (zh) * | 2018-01-31 | 2018-09-04 | 中国科学院微电子研究所 | Cmos器件及调节cmos器件阈值的方法 |
CN109979802A (zh) * | 2017-12-28 | 2019-07-05 | 中国科学院苏州纳米技术与纳米仿生研究所 | 高功函数可调的过渡金属氮化物材料、其制备方法及应用 |
CN112951760A (zh) * | 2019-11-26 | 2021-06-11 | 长鑫存储技术有限公司 | 存储器及其形成方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102856180A (zh) * | 2011-06-30 | 2013-01-02 | 中国科学院微电子研究所 | 一种半导体器件的替代栅集成方法 |
US20130157428A1 (en) * | 2011-12-14 | 2013-06-20 | Samsung Electronics Co., Ltd. | Methods of Manufacturing Semiconductor Devices Including Transistors |
CN103579111A (zh) * | 2012-07-26 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | 一种金属栅半导体器件的制造方法 |
CN103794506A (zh) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | 晶体管的形成方法 |
CN104821296A (zh) * | 2014-01-30 | 2015-08-05 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
CN105428361A (zh) * | 2014-09-19 | 2016-03-23 | 中国科学院微电子研究所 | Cmos器件及其制造方法 |
-
2017
- 2017-06-14 CN CN201710448613.5A patent/CN107180793B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102856180A (zh) * | 2011-06-30 | 2013-01-02 | 中国科学院微电子研究所 | 一种半导体器件的替代栅集成方法 |
US20130157428A1 (en) * | 2011-12-14 | 2013-06-20 | Samsung Electronics Co., Ltd. | Methods of Manufacturing Semiconductor Devices Including Transistors |
CN103579111A (zh) * | 2012-07-26 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | 一种金属栅半导体器件的制造方法 |
CN103794506A (zh) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | 晶体管的形成方法 |
CN104821296A (zh) * | 2014-01-30 | 2015-08-05 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
CN105428361A (zh) * | 2014-09-19 | 2016-03-23 | 中国科学院微电子研究所 | Cmos器件及其制造方法 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109979802A (zh) * | 2017-12-28 | 2019-07-05 | 中国科学院苏州纳米技术与纳米仿生研究所 | 高功函数可调的过渡金属氮化物材料、其制备方法及应用 |
CN109979802B (zh) * | 2017-12-28 | 2020-12-22 | 中国科学院苏州纳米技术与纳米仿生研究所 | 高功函数可调的过渡金属氮化物材料、其制备方法及应用 |
CN108493157A (zh) * | 2018-01-31 | 2018-09-04 | 中国科学院微电子研究所 | Cmos器件及调节cmos器件阈值的方法 |
CN108493157B (zh) * | 2018-01-31 | 2021-05-04 | 中国科学院微电子研究所 | Cmos器件及调节cmos器件阈值的方法 |
CN112951760A (zh) * | 2019-11-26 | 2021-06-11 | 长鑫存储技术有限公司 | 存储器及其形成方法 |
CN112951760B (zh) * | 2019-11-26 | 2022-06-24 | 长鑫存储技术有限公司 | 存储器及其形成方法 |
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