CN107144775A  A kind of measurement apparatus and method of CMOS inverter mutual conductance coefficient  Google Patents
A kind of measurement apparatus and method of CMOS inverter mutual conductance coefficient Download PDFInfo
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 CN107144775A CN107144775A CN201710364011.1A CN201710364011A CN107144775A CN 107144775 A CN107144775 A CN 107144775A CN 201710364011 A CN201710364011 A CN 201710364011A CN 107144775 A CN107144775 A CN 107144775A
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 G—PHYSICS
 G01—MEASURING; TESTING
 G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
Description
Technical field
The invention belongs to technical field of integrated circuits, it is related to measurement apparatus and the side of a kind of CMOS inverter mutual conductance coefficient Method, extraction and analysis available for mutual conductance coefficient in IC design and emulation.
Background technology
Phase inverter is by the circuit of the phasing back 180 degree of input signal.Normal inverters have two kinds, are TTL nonrespectively Door and CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor) phase inverter. The input structure and export structure of TTL NOT gates are constituted by transistor and resistance.CMOS inverter is enhanced by two MOS (Metal Oxide Semiconductor metaloxide semiconductor (MOS)s) is constituted, respectively NMOS (NMetalOxide Semiconductor, Ntype metaloxide semiconductor (MOS)) and PMOS (PMetalOxideSemiconductor, ptype metal Oxide semiconductor).Mutual conductance is the parameter for reacting MOS device gate source voltage to drain current control ability, and reaction MOS device is small Signal amplification performance.The definition of MOS device mutual conductance is, when drainsource voltage is a certain fixed numbers, the variable of drain current and to draw It is mutual conductance to play the ratio between gate source voltage of this change.In the linear zone of MOS device, mutual conductance is directly proportional to sourcedrain voltage, in MOS The saturation region of device, mutual conductance is directly proportional to the difference of gate source voltage and threshold voltage.Mutual conductance coefficient is MOS channel width, ditch / 2nd of the ratio between the channel length of road electron mobility, the product of unit area gate capacitance and MOS.Mutual conductance coefficient be reaction across The coefficient of gain is led, it is related to the manufacturing process of device, it is a constant being directly proportional to mutual conductance.By extracting MOS device Mutual conductance coefficient, calculates the mutual conductance of MOS device, so that the low level signal amplification performance of acquisition device, to IC design and emulation Have great significance.
At present, mutual conductance coefficient is mainly the mutual conductance by measuring MOS, further according to the currentvoltage correlation of MOS workspace Formula is calculated and obtained.Existing mutual conductance measuring method is mainly measurement MOS drain currents and gate source voltage, obtains MOS mutual conductance.
The apparatus and method of existing measurement mutual conductance mainly have following several.
1st, by presetting the sourcedrain voltage of metaloxidesemiconductor, the drain current of metaloxidesemiconductor is scanned, the maximum transconductance value of metaloxidesemiconductor is obtained. For example, application publication number be CN105513984A, entitled " method of testing and device of the actual channel length of metaloxidesemiconductor " it is special Profit application, discloses a kind of transconductance parameters measuring method, this method two first scanning elements adjacent by calculating are corresponded to respectively The first drain current the first difference, obtained from multiple first differences maximum the first difference, described is maximum The ratio at the first difference and the interval is the maximum transconductance value of first metaloxidesemiconductor.This method can pass through survey calculation The maximum transconductance value of single MOS device calculates mutual conductance coefficient indirectly, and measurement efficiency is low.
2nd, by measuring bias voltage in CMOS inverter, internal feedback resistance and two interior output resistances, CMOS is calculated anti The output resistance of phase device, substitutes into correlation computations formula by output resistance, obtains the mutual conductance of CMOS inverter.For example, patent is awarded Power number is CN101846723B, and the Chinese patent of entitled " method for measurement of transconductance parameters " discloses a kind of CMOS inverter The method for measurement of transconductance parameters, the method for measurement of the transconductance parameters includes：The input and output end of suspension joint phase inverter, and measure Output end is to obtain the bias voltage of phase inverter.Suspension joint input, and first voltage and second voltage are provided respectively to output End, to be measured from output end to the first electric current corresponding to first voltage and the second electric current corresponding to second voltage.First Voltage has identical voltage level with bias voltage.According to first voltage, second voltage, the first electric current and the second electric current, obtain To the output resistance of phase inverter.According to output resistance, the mutual conductance of oscillating circuit is obtained.This method measurement cost is relatively low, but It is that measuring method has relied on 4 measuring circuits, device is complicated, and time of measuring is long, is not easy to Project Realization.
Abovementioned prior art can only calculate MOS mutual conductance coefficient indirectly by measuring MOS mutual conductance.For what is encapsulated CMOS inverter, the method measurement efficiency that NMOS mutual conductance and PMOS mutual conductance inside CMOS inverter are measured respectively is low, and not It is easy to Project Realization.
The content of the invention
It is an object of the invention to overcome the shortcomings of abovementioned prior art presence, there is provided a kind of CMOS inverter mutual conductance system Several measurement apparatus and method, the mutual conductance coefficient for solving to be unable to direct measurement CMOS inverter present in prior art Technical problem.
To achieve the above object, the technical scheme taken of the present invention is：
A kind of measurement apparatus of CMOS inverter mutual conductance coefficient, including the first dc source, the second dc source, load electricity Resistance, voltmeter, ammeter, first switch, second switch and the 3rd switch；The positive pole of first dc source is opened by first Pass be connected with CMOS inverter input to be measured, negative pole passed sequentially through by being divided into twoway after second switch, all the way ammeter with Load resistance is connected with the output end of CMOS inverter to be measured, another switches of Lu Yu tri connection；Second dc source Positive pole is connected with the power end of CMOS inverter to be measured and the 3rd switch, negative pole ground connection；The voltmeter is in parallel with load resistance. Wherein：
First dc source, the input voltage for providing CMOS inverter to be measured；
Second dc source, the supply voltage for providing CMOS inverter to be measured.
A kind of measuring method of CMOS inverter mutual conductance coefficient, comprises the following steps：
(1) second dc source is that CMOS inverter power end to be measured applies DC voltage V_{dd}；
(2) closure first switch and the 3rd switch, simultaneously switch off second switch；
(3) first dc sources are that CMOS inverter input to be measured applies DC voltage V_{in}；
(4) ammeter and voltmeter measurement NMOS are on and PMOS is in the electric current of the load resistance under cutoff state I_{Rn}With the voltage V at load resistance two ends_{Rn}；
(5) electric current I is passed through_{Rn}With voltage V_{Rn}, calculate NMOS mutual conductance COEFFICIENT K_{n}；
(6) first switch and the 3rd switch are disconnected, second switch is closed at；
(7) ammeter and voltmeter measurement PMOS are on and NMOS is in the electric current of the load resistance under cutoff state I_{Rp}With the voltage V at load resistance two ends_{Rp}；
(8) electric current I is passed through_{Rp}With voltage V_{Rp}, calculate PMOS mutual conductance COEFFICIENT K_{p}。
The present invention compared with prior art, has the following advantages that：
1. the present invention is directly calculated by measuring electric current and voltage of the MOS device on load resistance under different conditions Go out MOS mutual conductance coefficient, for the CMOS inverter encapsulated, NMOS mutual conductances system can be completed simultaneously in a measurement apparatus The measurement of number and PMOS mutual conductance coefficients, compared with prior art, improves measurement efficiency.
2. the present invention uses a set of measurement apparatus, by measuring electricity of the MOS device on load resistance under different conditions Stream and voltage, oneshot measurement go out MOS mutual conductance coefficient, and measurement apparatus is simple, time of measuring is effectively reduced, with prior art phase Than workable, it is easy to Project Realization.
Brief description of the drawings
Fig. 1 is the structural representation of measurement apparatus of the present invention；
Fig. 2 is the implementation process figure of measuring method of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.CMOS in the present embodiment is anti Phase device is by taking NC7SZU04 as an example.
Reference picture 1, a kind of measurement apparatus of CMOS inverter mutual conductance coefficient, including the first dc source, the second direct current Source, load resistance, voltmeter, ammeter, first switch, second switch and the 3rd switch；The positive pole of first dc source It is connected by first switch with CMOS inverter input to be measured, negative pole is led to successively all the way by being divided into twoway after second switch Overcurrent table and load resistance are connected with the output end of CMOS inverter to be measured, another switches of Lu Yu tri connection；Described second The positive pole of dc source is connected with the power end of CMOS inverter to be measured and the 3rd switch, negative pole ground connection；The voltmeter is with bearing Carry resistor coupled in parallel.Wherein, the first dc source, the input voltage for providing CMOS inverter to be measured；Second dc source, is used In the supply voltage for providing CMOS inverter to be measured.
CMOS inverter power supply termination DC voltage V_{dd}, ground terminal ground connection, it is ensured that CMOS inverter is in normal operating conditions Under, i.e., PMOS drain electrode meets high level V inside CMOS inverter_{dd}, CMOS inverter inside NMOS grounded drain, it is ensured that PMOS Voltage difference between NMOS source and drain, makes PMOS and NMOS be in normal operating conditions.
First switch controls whether the first dc source provides input voltage for the input of CMOS inverter, if first opens Close and close, the input for CMOS inverter provides input voltage by the first dc source, now PMOS grid voltage and NMOS Grid voltage is equal with input voltage.
The connection of second switch and the 3rd switch control CMOS inverter output end, closes second switch, then CMOS is antiphase The output end of device connects ground by load resistance, and now NMOS drain voltage and PMOS drain voltage are equal to the defeated of CMOS Go out voltage, with reference to NMOS and grid voltage and PMOS grid voltage, can determine in the case where closing second switch in CMOS inverter The respective conducting situation of portion NMOS and PMOS.Similarly, when closure the 3rd is switched, the output end of CMOS inverter is by loading electricity Resistance connects the second direct voltage source, and now NMOS drain voltage and PMOS drain voltage are equal to CMOS output voltage, knot Close NMOS and grid voltage and PMOS grid voltage, can determine in the case of the switch of closure the 3rd inside CMOS inverter NMOS and The respective conducting situations of PMOS.
A kind of reference picture 2, measuring method of CMOS inverter mutual conductance coefficient, comprises the following steps：
Step 1, the second dc source is that CMOS inverter power end to be measured applies DC voltage V_{dd}。
CMOS inverter is that the condition of circuit normal work is power supply by the circuit of the phasing back 180 degree of input signal Voltage V_{dd}NMOS threshold voltages and PMOS threshold voltage absolute value sums need to be more than.
In the present embodiment, the second dc source is that CMOS inverter power end applies positive voltage V_{dd}=3.3V.
Step 2, closure first switch and the 3rd switch, meanwhile, disconnect second switch.
First switch is closed, and the 3rd switch closure, second switch disconnects, i.e., ammeter is another is terminating the second dc source just Pole.Now circuit equivalent is load resistance R with being connected again with NMOS after PMOS parallel connections.
Step 3, the first dc source is that CMOS inverter input to be measured applies DC voltage V_{in}。
The input of CMOS inverter is the linkage section of NMOS gate and PMOS grids, is that the input of CMOS inverter is applied Plus DC voltage V_{in}It need to ensure that NMOS is in the conduction state.
In the present embodiment, the first dc source is that CMOS inverter applies positive voltage V_{in}=3.3V.
Step 4, ammeter and voltmeter measure the electric current I of load resistance_{Rn}With the voltage V at load resistance two ends_{Rn}。
Because load resistance R is in parallel with PMOS, then PMOS sourcedrain voltage V_{dsp}, meet relational expression：
V_{dsp}=V_{Rn}
In the present embodiment, the voltage V at the load resistance R two ends that voltmeter is measured_{Rn}=2.983V.
In the present embodiment, NMOS threshold voltage is V_{thn}=0.662V, PMOS threshold voltage are V_{thp}=0.858V.
Due to for PMOS, V_{gsp}＞ V_{thp}And V_{dsp}＜ V_{gsp}V_{thp}, now PMOS is in by area, PMOS electric conduction Hinder R_{p}Tend to be infinitely great.
Due to load resistance R resistance R_{r}Far smaller than PMOS conducting resistance R_{p}, therefore load resistance R is in parallel with PMOS Equivalent resistance R_{e1}, meet relational expression：
Now equivalent resistance R_{e1}On equivalent current I_{e1}For：
Wherein, V_{e1}It is equivalent resistance R_{e1}On voltage, V_{e1}With the voltage V on load resistance R_{Rn}It is equal.
Because circuit equivalent is to be connected again with NMOS after load resistance R and PMOS parallel connection, equivalent to equivalent resistance R_{e1}With NMOS connects, therefore NMOS sourcedrain currents I_{dsn}, meet condition：
I_{dsn}=I_{e1}=I_{Rn}
In the present embodiment, the electric current I of ammeter measurement stream overload resistance_{Rn}=14.9mA.
Due to NMOS and equivalent resistance R_{e1}The sourcedrain voltage satisfaction of series connection, then NMOS：
V_{dsn}=V_{dd}V_{Rn}
Step 5, electric current I is passed through_{Rn}With voltage V_{Rn}, calculate NMOS mutual conductance COEFFICIENT K_{n}。
Because NMOS meets V_{gsn}＞ V_{thn}And V_{dsn}＜ V_{gsn}V_{thn}, now NMOS is in linear zone, therefore NMOS meets line Property area formula：
Therefore NMOS mutual conductance coefficient formulas is：
In this example, NMOS mutual conductance COEFFICIENT K is calculated_{n}=0.0754.
Step 6, first switch and the 3rd switch are disconnected, meanwhile, close second switch.
First switch disconnects, now NMOS grid voltages V_{gsn}=0V and PMOS grid voltage V_{gsp}=V_{dd}。
3rd switches off, second switch closure, i.e. the first DC power cathode of another termination of voltmeter.Now circuit etc. Imitate is to be connected again with PMOS after load resistance R and NMOS in parallel.
Step 7, ammeter and voltmeter measure the electric current I of load resistance_{Rp}With the voltage V at load resistance two ends_{Rp}。
Because load resistance R is in parallel with NMOS, NMOS sourcedrain voltage V_{dsn}, meet relational expression：
V_{dsn}=V_{Rn}
In the present embodiment, the voltage V at the load resistance R two ends that voltmeter is measured_{Rn}=3.02V.
Due to for NMOS, V_{gsp}＜ V_{thn}And V_{ds}＞ V_{gs}V_{thn}, now NMOS is in by area, NMOS electric conduction Hinder R_{n}Tend to be infinitely great.
Due to load resistance R resistance R_{r}Far smaller than NMOS conducting resistance R_{p}, therefore load resistance R is in parallel with NMOS Equivalent resistance R_{e2}, meet relational expression：
Now equivalent resistance R_{e2}On equivalent current I_{e2}For：
Wherein, V_{e2}It is equivalent resistance R_{e2}On voltage, V_{e2}With the voltage V on load resistance R_{Rp}It is equal.
Because circuit equivalent is to be connected again with PMOS after load resistance R and NMOS parallel connection, equivalent to equivalent resistance R_{e1}With PMOS connects, therefore PMOS source leakage current I_{dsp}, meet condition：
I_{dsp}=I_{e2}=I_{Rp}
In the present embodiment, the electric current I of ammeter measurement stream overload resistance_{Rp}=15.1mA.
Due to PMOS and equivalent resistance R_{e1}The sourcedrain voltage satisfaction of series connection, then PMOS：
V_{dsp}=V_{Rp}V_{dd}
Step 8, electric current I is passed through_{Rp}With voltage V_{Rp}, calculate PMOS mutual conductance COEFFICIENT K_{p}。
Because PMOS meets V_{gsn}＞ V_{thp}And V_{dsn}＞ V_{gsn}V_{thp}, now PMOS is in linear zone, therefore PMOS meets line Property area formula：
Therefore PMOS mutual conductance coefficient formulas is：
In this example, PMOS mutual conductance COEFFICIENT K is calculated_{p}=0.0934.
Above description is only example of the present invention, it is clear that for those skilled in the art, is being understood After present invention and principle, it may all carry out in form and details in the case of without departing substantially from the principle of the invention, structure Various modifications and variations, but these modifications and variations based on inventive concept are still in the claims of the present invention Within.
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JP2002270768A (en) *  20010308  20020920  Nec Corp  Cmos reference voltage circuit 
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CN101846723A (en) *  20090325  20100929  普诚科技股份有限公司  Measuring method of transconductance parameters 
CN202083773U (en) *  20110118  20111221  上海理工大学  Semiconductor parameter testing system 
CN102565650A (en) *  20101207  20120711  中国科学院微电子研究所  Measuring system of GaN HEMT device transconductance frequency scattering characteristic and method thereof 
CN105513984A (en) *  20140924  20160420  北大方正集团有限公司  Test method and device for practical channel length of MOS tubes 

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Patent Citations (6)
Publication number  Priority date  Publication date  Assignee  Title 

JP2002270768A (en) *  20010308  20020920  Nec Corp  Cmos reference voltage circuit 
CN101303390A (en) *  20080623  20081112  上海集成电路研发中心有限公司  Method for judging MOS device performance degeneration 
CN101846723A (en) *  20090325  20100929  普诚科技股份有限公司  Measuring method of transconductance parameters 
CN102565650A (en) *  20101207  20120711  中国科学院微电子研究所  Measuring system of GaN HEMT device transconductance frequency scattering characteristic and method thereof 
CN202083773U (en) *  20110118  20111221  上海理工大学  Semiconductor parameter testing system 
CN105513984A (en) *  20140924  20160420  北大方正集团有限公司  Test method and device for practical channel length of MOS tubes 
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