CN107134266A - Display driver circuit, display drive method and display device - Google Patents
Display driver circuit, display drive method and display device Download PDFInfo
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- CN107134266A CN107134266A CN201710335131.9A CN201710335131A CN107134266A CN 107134266 A CN107134266 A CN 107134266A CN 201710335131 A CN201710335131 A CN 201710335131A CN 107134266 A CN107134266 A CN 107134266A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
Abstract
The present invention provides a kind of display driver circuit, display drive method and display device.The display driver circuit includes powered-off fault monitoring unit and drive control unit；Power circuit persistently exports the first level after powered-off fault control signal is received in the first level output end of discharge time section control；Sequential control circuit is after the powered-off fault control signal is received, in discharge time section, the first level exported according to the first level output end, control clock signal output terminal exports the first level, to cause gate driving circuit to control the multirow grid line to open simultaneously；Data drive circuit controls output predetermined discharge level to a plurality of data lines after the powered-off fault control signal is received.The present invention can be in powered-off fault in pixel electrode residual charge be discharged to data wire, remove residual charge.
Description
Technical field
The present invention relates to display actuation techniques field, more particularly to a kind of display driver circuit, display drive method and aobvious
Showing device.
Background technology
With developing rapidly for liquid crystal display industry, requirement more and more higher of the people to mobile electronic product is lightening, high
Resolution ratio, performance is stable to turn into the primary demand of consumer gradually so that One-chip (chip) IC with high integration
(Gate On Array are arranged at the raster data model electricity on array base palte by (Integrated Circuit, integrated circuit) and GOA
Road) design and arise at the historic moment.
Data drive circuit, sequential control circuit and Power IC (power circuit) are integrated in by new One-Chip IC
On source driving chip, space is reduced, overall cost is reduced, but process complexity and design requirement are improved,
But controlled well without each individual devices when tackling some abnormal special circumstances.As client ESD (electrostatic protection) requirement compared with
Gao Shi, ESD experiment can cause disorder to the signal and voltage of system, can directly influence the normal work of display device, at this moment collect
One-Chip IC higher Cheng Du, which can be easier to be interfered, causes operation irregularity, when now to abnormal signal at IC inside
Reason and protection mechanism are particularly important, and IC may have the liquid crystal reversion in the protection mechanism of oneself, but Panel (display panel)
Be by data drive circuit output and GOA circuit output co- controllings, IC can direct power down protection, but can so cause display surface
Liquid crystal polarization on plate, has scintillation during point screen again.Other end product also often has the situation for forcing power-off, such a feelings
Condition will also result in residual charge on display panel, cause the bad generation of boot flash, and bad generation will cause visitor when more
Tell, be all unfavorable to brand influence and product promotion.
The content of the invention
It is a primary object of the present invention to provide a kind of display driver circuit, display drive method and display device, solve
Residual charge in pixel electrode can not be effectively discharged during display device powered-off fault in the prior art, so that when causing to put screen again
Produce the problem of splashette is bad.
In order to achieve the above object, the invention provides a kind of display driver circuit, applied to display device, the display
Multirow grid line and multiple columns of data lines are provided with the display base plate that device includes；The display driver circuit include power circuit,
Sequential control circuit, the data drive circuit being connected with multiple columns of data lines and the raster data model electricity being connected with the multirow grid line
Road, the power circuit includes the first level output end being connected with the sequential control circuit, first level output end
For exporting the first level in the display period, first level is to be used to open the film in pixel region on the grid line
The maximum on-state voltage of transistor, the sequential control circuit includes the clock signal output being connected with the gate driving circuit
End, the display driver circuit also includes powered-off fault monitoring unit and drive control unit；
The powered-off fault monitoring unit, which is used to work as, to be determined by the power voltage input terminal input of the power circuit
The first powered-off fault indication signal is exported when the magnitude of voltage of power supply voltage signal is not in the range of scheduled voltage, when determining
The second powered-off fault is exported when stating digital data signal and/or the data sampling clock signal interruption that sequential control circuit is received
Indication signal, when determining the current potential for the external reset signal that the sequential control circuit is received not in the range of predetermined potential
When export the 3rd powered-off fault indication signal；
The drive control unit is connected with the powered-off fault monitoring unit, is fallen for that ought receive first exception
When at least one of electric indication signal, the second powered-off fault indication signal, described 3rd powered-off fault indication signal, output
Powered-off fault control signal；
The power circuit is connected with the drive control unit, for receiving the powered-off fault control signal
Afterwards, the first level is persistently exported in discharge time section control first level output end；
The sequential control circuit is connected with the drive control unit, for receiving the powered-off fault control letter
After number, in discharge time section, the first level exported according to first level output end controls the clock signal output terminal
The first level is exported, to cause the gate driving circuit to control the multirow grid line to open simultaneously；
The data drive circuit is connected with the drive control unit, for receiving the powered-off fault control letter
Control exports predetermined discharge level to a plurality of data lines after number.
During implementation, the powered-off fault control signal includes the first level output end current potential and maintains signal, clock signal control
Signal processed and data voltage control signal；
The drive control unit receives the first powered-off fault indication signal, second exception specifically for working as
When at least one of power down indication signal, described 3rd powered-off fault indication signal, the first level is exported to the power circuit
Export terminal potential and maintain signal, and clock signal control signal is exported to the sequential control circuit, to data-driven electricity
Road output data voltage control signal；
The power circuit is specifically for after the first level output end current potential maintenance signal is received, in electric discharge
Between section control first level output end persistently to export the first level；
The sequential control circuit is specifically for after the clock signal control signal is received, according to the described first electricity
First level of flat output end output, controls the clock signal output terminal to export the first level, to cause the raster data model
Circuit controls the multirow grid line to open simultaneously；
The data drive circuit is put specifically for control output is predetermined after the data voltage control signal is received
Level is to a plurality of data lines.
During implementation, the predetermined discharge level is ground level.
During implementation, the discharge time section was sustained for longer than or equal to the duration of a frame display picture.
During implementation, the power voltage input terminal includes 3.3V DC voltage input ends, 1.8V DC voltage input ends, just
Liquid crystal drive voltage input and negative liquid crystal drive voltage input；
The scheduled voltage scope makes a reservation for including the first scheduled voltage scope, the second scheduled voltage scope, the 3rd
Range of voltage values and the 4th scheduled voltage scope；
The powered-off fault monitoring unit determines what is inputted by the 3.3V DC voltage input ends specifically for working as
First powered-off fault is exported when the magnitude of voltage of 3.3V d. c. voltage signals is not in the range of the first scheduled voltage and indicates letter
Number, when determining the magnitude of voltage of the 1.8V d. c. voltage signals inputted by 1.8V DC voltage input ends not in the second predetermined voltage
The first powered-off fault indication signal is exported when in the range of value, is inputted when determining by the positive liquid crystal drive voltage input
Positive liquid crystal drive voltage signal magnitude of voltage not in the range of the 3rd scheduled voltage when export first powered-off fault and refer to
Show signal, do not existed by the magnitude of voltage of the negative liquid crystal drive voltage signal of the negative liquid crystal drive voltage input input when determining
The first powered-off fault indication signal is exported when in the range of the 4th scheduled voltage.
Present invention also offers a kind of display drive method, applied to above-mentioned display driver circuit, the display driving
Method includes：
Powered-off fault judgment step：When powered-off fault monitoring unit determine it is defeated by the power voltage input terminal of power circuit
The first powered-off fault indication signal is exported when the magnitude of voltage of the power supply voltage signal entered is not in the range of scheduled voltage, works as exception
When the digital data signal and/or data sampling clock signal that down Monitor Unit unit judges are received to sequential control circuit are interrupted
The second powered-off fault indication signal is exported, when powered-off fault monitoring unit determines the outside that the sequential control circuit is received
The 3rd powered-off fault indication signal is exported when the current potential of reset signal is not in the range of predetermined potential；
Powered-off fault rate-determining steps：When drive control unit receives the first powered-off fault indication signal, described
When at least one of two powered-off fault indication signals, described 3rd powered-off fault indication signal, the drive control unit output
Powered-off fault control signal；
Power supply step：After the power circuit receives the powered-off fault control signal, the power circuit
The first level is persistently exported in discharge time section control first level output end；
Clock control step：After the sequential control circuit receives the powered-off fault control signal, the sequential
The first level for controlling circuit to be exported in discharge time section according to first level output end, control clock signal output terminal is defeated
Go out the first level, to cause the drive circuit to control a plurality of grid line to open simultaneously；
Data drive control step：It is described after the data drive circuit receives the powered-off fault control signal
Data drive circuit control exports predetermined discharge level to a plurality of data lines.
During implementation, the powered-off fault control signal includes the first level output end current potential and maintains signal, clock signal control
Signal processed and data voltage control signal；
The powered-off fault rate-determining steps are specifically included：When the drive control unit receives first powered-off fault
When at least one of indication signal, the second powered-off fault indication signal, described 3rd powered-off fault indication signal, the drive
Dynamic control unit exports the first level output end current potential to the power circuit and maintains signal, and defeated to the sequential control circuit
Go out clock signal control signal, to the data drive circuit output data voltage control signal；
The power supply step is specifically included：The first level output end current potential dimension is received in the power circuit
Hold after signal, the power circuit persistently exports the first level in discharge time section control first level output end；
The clock control step is specifically included：The clock signal control signal is received in the sequential control circuit
Afterwards, the first level that the sequential control circuit is exported according to first level output end, controls the clock signal output
The first level of end output, to cause the gate driving circuit to control the multirow grid line to open simultaneously；
The data drive control step is specifically included：The data voltage control is received in the data drive circuit
After signal, the data drive circuit control output predetermined discharge level to a plurality of data lines.
During implementation, the discharge time section was sustained for longer than or equal to the duration of a frame display picture.
During implementation, when the power voltage input terminal include 3.3V DC voltage input ends, 1.8V DC voltage input ends,
When positive liquid crystal drive voltage input and negative liquid crystal drive voltage input, the scheduled voltage scope includes the first predetermined electricity
Pressure value scope, the second scheduled voltage scope, the 3rd scheduled voltage scope and the 4th scheduled voltage scope；
The powered-off fault monitoring unit of working as is determined by the supply voltage of the power voltage input terminal input of power circuit
The first powered-off fault indication signal step is exported when the magnitude of voltage of signal is not in the range of scheduled voltage to be included：The exception is fallen
Pyroelectric monitor unit is specifically for when the electricity for determining the 3.3V d. c. voltage signals inputted by the 3.3V DC voltage input ends
The first powered-off fault indication signal is exported when pressure value is not in the range of the first scheduled voltage, when determining by 1.8V direct currents
Described the is exported when the magnitude of voltage of the 1.8V d. c. voltage signals of voltage input end input is not in the range of the second scheduled voltage
One powered-off fault indication signal, when determining by the positive liquid crystal drive voltage signal of the positive liquid crystal drive voltage input input
Magnitude of voltage not in the range of the 3rd scheduled voltage when export the first powered-off fault indication signal, when determining by described
The magnitude of voltage of the negative liquid crystal drive voltage signal of negative liquid crystal drive voltage input input is not in the range of the 4th scheduled voltage
When export the first powered-off fault indication signal.
Present invention also offers a kind of display device, including above-mentioned display driver circuit.
Compared with prior art, described in the embodiment of the present invention display driver circuit, display drive method and display device
Residual charge that can be in powered-off fault in pixel electrode is discharged to data wire, removes residual charge, can effectively prevent display from filling
Film flicker is bad when causing to put screen again due to the polarization of liquid crystal residual charge when putting abnormal work, to improving display device complete machine
The splashette that ESD (electrostatic protection) is caused has better effects, can also meet the requirement that client forced interruption restarts no splashette again.
Brief description of the drawings
Fig. 1 is the structure chart of the display driver circuit described in the embodiment of the present invention；
Fig. 2 is the structure chart of display device that is applied to of a specific embodiment of display driver circuit of the present invention；
Fig. 3 is the signal waveforms of present invention display device as shown in Figure 2；
Fig. 4 is the flow chart of the display drive method described in the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
Display driver circuit described in the embodiment of the present invention, applied to display device, the display that the display device includes
Multirow grid line and multiple columns of data lines are provided with substrate；
As shown in figure 1, the display driver circuit includes power circuit 101, sequential control circuit 102 and multi-column data
The data drive circuit 103 of line (not shown in figure 1) connection and the grid being connected with the multirow grid line (not shown in figure 1) drive
Dynamic circuit 104；
The power circuit 101 includes the first level output end VO1 being connected with the sequential control circuit 102；
The first level output end VO1 is used to export the first level in the display period, and first level is described
It is used for the maximum on-state voltage for opening the thin film transistor (TFT) in pixel region on grid line；
The sequential control circuit 102 includes the clock signal output terminal CLKO being connected with the gate driving circuit 104；
The display driver circuit described in the embodiment of the present invention also includes powered-off fault monitoring unit 11 and drive control
Unit 12；
The powered-off fault monitoring unit 11 is connected with the power circuit 101 and the sequential control circuit 102 respectively,
Determined for working as by the power supply voltage signal of the power voltage input terminal (not shown in figure 1) input of the power circuit 101
Magnitude of voltage not in the range of scheduled voltage when export the first powered-off fault indication signal, when determining SECO electricity
The digital data signal and/or data sampling clock signal that road 102 is received export the second powered-off fault indication signal when interrupting,
Exported when determining the current potential for the external reset signal that the sequential control circuit 102 is received not in the range of predetermined potential
3rd powered-off fault indication signal；
The drive control unit 12 is connected with the powered-off fault monitoring unit 11, for different when receiving described first
When at least one of normal power down indication signal, the second powered-off fault indication signal, described 3rd powered-off fault indication signal,
Output abnormality power down control signal；
The power circuit 101 is connected with the drive control unit 12, for receiving the powered-off fault control
After signal, the first level is persistently exported in discharge time section control the first level output end VO1；
The sequential control circuit 102 is connected with the drive control unit 12, for receiving the powered-off fault
After control signal, the first level exported according to the first level output end VO1 controls the clock signal output terminal CLKO
The first level is exported, to cause the gate driving circuit to control the multirow grid line to open simultaneously；
The data drive circuit 103 is connected with the drive control unit 12, for receiving the powered-off fault
Control exports predetermined discharge level to a plurality of data lines (not shown in figure 1) after control signal.
In practical operation, the scheduled voltage scope can be set according to actual conditions, and mask body specific as follows is real
Apply cited by example, but specific embodiment, only to scheduled voltage scope explanation for example, is not limited thereto below；
In practical operation, the predetermined potential scope can be set according to actual conditions, and mask body specific as follows is implemented
Example is cited, but specific embodiment, only to scheduled voltage scope explanation for example, is not limited thereto below.
Display driver circuit described in the embodiment of the present invention includes powered-off fault monitoring unit 11 and drive control unit 12,
When the magnitude of voltage that powered-off fault monitoring unit 11 determines the power supply voltage signal of power voltage input terminal input is abnormal, when different
When normal down Monitor Unit unit 11 determines the digital data signal and/or data sampling that the sequential control circuit 102 is received
Clock signal interruption, when powered-off fault monitoring unit 11 determines the electricity for the external reset signal that sequential control circuit 102 is received
When position is abnormal, the output abnormality power down indication signal of powered-off fault monitoring unit 11, drive control unit 12 is receiving
Output abnormality power down control signal after powered-off fault indication signal is stated, to control the power circuit 101 to be controlled in discharge time section
Make the first level output end VO1 and persistently export the first level, sequential control circuit 102 causes output according to first level
Current potential to the clock signal of gate driving circuit is also the first level, so that gate driving circuit controls a plurality of grid line same
When open (namely the film crystalline substance for causing the gate drive signal of gate driving circuit output to enable to be connected with corresponding line grid line
Body pipe is all turned on), the control output predetermined discharge level after data drive circuit 103 receives the powered-off fault control signal
To a plurality of data lines (such as data wire can be caused to access ground level) so that the residual charge in pixel electrode is discharged to data
Line, removes residual charge, is effectively improved splashette bad.
In practical operation, when the thin film transistor (TFT) in pixel region is n-type transistor, first level can be
High level.
In the common powered-off fault of display device (namely when not using the display driver circuit described in the embodiment of the present invention),
The slow power down of high level (low level is gradually reduced to by high level) of first level output end VO1 outputs, the sequential control
Circuit 102 processed is exported to the clock signal also slow power down, data of gate driving circuit 104 by clock signal output terminal CLKO
Drive circuit 103 exports the data voltage also slow power down to data wire, so that the residual charge in pixel electrode has little time
Discharge, residual charge is had on display panel and easily causes liquid crystal polarization, can occur splashette when screen is put again next time.
And in powered-off fault monitoring unit 11 to determine input signal different for the display driver circuit described in the embodiment of the present invention
Chang Shi, sends powered-off fault indication signal, and drive control unit 12 is receiving powered-off fault indication signal output abnormality power down
Control signal, postpones the first level output end VO1 power down time with controlling power circuit 101 using residual charge, that is, causes
Power circuit 101 is in discharge time section still control VO1 outputs high level, to cause sequential control circuit 102 in discharge time
Section output to the current potential of the clock signal of gate driving circuit is pulled to high level immediately, so that gate driving circuit exists
The current potential of the gate drive signal of discharge time section output is all pulled to high level, and data drive circuit 103 is exported immediately
Ground level can so to carry out display panel after powered-off fault effective sweep-black to data wire, and remove residual charge,
It is effectively improved splashette bad.
After in the discharge time, section terminates, the first level of the first level output end VO1 outputs of power circuit 101 is opened
Beginning power down, thus the sequential control circuit 102 by clock signal output terminal CLKO export to gate driving circuit 104 when
Clock signal also begins to power down.
In practical operation, the power circuit 101, the sequential control circuit 102 and the data drive circuit 103
It is integrated on source drive IC (Integrated Circuit, integrated circuit), the gate driving circuit 104 is arranged at display
On substrate.
The embodiment of the present invention controls module by adding powered-off fault on source drive IC, and the powered-off fault controls mould
Group includes powered-off fault observation circuit and drive control circuit, and powered-off fault observation circuit is the power supply received to power circuit
Digital data signal and/or data sampling clock signal that voltage, sequential control circuit are received, sequential control circuit are received
External reset signal whether occur it is abnormal be monitored, drive control circuit powered-off fault monitoring circuit monitors to it is abnormal when
Output abnormality power down control signal, with the defeated of controlling power circuit 101, sequential control circuit 102 and data drive circuit 103
Go out signal, to clearly show that residual charge on panel, the occurrence of effectively can solving splashette.
In the specific implementation, the powered-off fault control signal can include the first level output end current potential maintain signal,
Clock signal control signal and data voltage control signal；
The drive control unit 12 specifically for when receiving the first powered-off fault indication signal, it is described second different
When at least one of normal power down indication signal, described 3rd powered-off fault indication signal, first is exported to the power circuit 101
Level output end current potential maintains signal, and exports clock signal control signal to the sequential control circuit 102, to the data
The output data voltage control signal of drive circuit 103；
The power circuit 101 is specifically for after the first level output end current potential maintenance signal is received, putting
The electric period controls the first level output end VO1 persistently to export the first level；
The sequential control circuit 102 is specifically for after the clock signal control signal is received, according to described
First level of one level output end VO1 outputs, controls the clock signal output terminal CLKO to export the first level, to cause
Stating gate driving circuit controls the multirow grid line to open simultaneously；
The data drive circuit 103 after the data voltage control signal is received specifically for controlling output predetermined
Discharge level is to a plurality of data lines.
Specifically, the predetermined discharge level can be ground level.
In the preferred case, discharge time section be sustained for longer than or equal to a frame display picture it is lasting when
Between, such discharge time section duration is long, and residual charge eradicating efficacy is preferable.
According to a kind of embodiment, it is straight that the power voltage input terminal includes 3.3V DC voltage input ends, 1.8V
Flow voltage input end, positive liquid crystal drive voltage input and negative liquid crystal drive voltage input；
The scheduled voltage scope makes a reservation for including the first scheduled voltage scope, the second scheduled voltage scope, the 3rd
Range of voltage values and the 4th scheduled voltage scope；
The powered-off fault monitoring unit determines what is inputted by the 3.3V DC voltage input ends specifically for working as
First powered-off fault is exported when the magnitude of voltage of 3.3V d. c. voltage signals is not in the range of the first scheduled voltage and indicates letter
Number, when determining the magnitude of voltage of the 1.8V d. c. voltage signals inputted by 1.8V DC voltage input ends not in the second predetermined voltage
The first powered-off fault indication signal is exported when in the range of value, is inputted when determining by the positive liquid crystal drive voltage input
Positive liquid crystal drive voltage signal magnitude of voltage not in the range of the 3rd scheduled voltage when export first powered-off fault and refer to
Show signal, do not existed by the magnitude of voltage of the negative liquid crystal drive voltage signal of the negative liquid crystal drive voltage input input when determining
The first powered-off fault indication signal is exported when in the range of the 4th scheduled voltage.
Illustrate display driver circuit of the present invention below by a specific embodiment.
As shown in Fig. 2 a specific embodiment of display driver circuit of the present invention includes power circuit 101, sequential
Control circuit 102, data drive circuit 103, powered-off fault monitoring unit 11, drive control unit 12 and gate driving circuit
(not shown in Fig. 2)；
The display device that the specific embodiment of display driver circuit of the present invention is applied to also includes system interface
20th, external power source integrated circuit 21, source electrode driver 22 and liquid crystal display panel 23；
Power circuit 101, sequential control circuit 102, data drive circuit 103, powered-off fault monitoring unit 11, driving control
Unit 12 processed is integrated on the source electrode driver 22；
Multirow grid line (not shown in Fig. 2), multiple columns of data lines is provided with the liquid crystal display panel 23 (in Fig. 3 not show
Go out) and gate driving circuit (not shown in Fig. 2, the gate driving circuit be GOA (Gate On Array, are arranged on array base
Gate driving circuit on plate) circuit), wherein, the gate driving circuit is connected with the multirow grid line, the data-driven
Circuit 103 is connected with the multiple columns of data lines；
The power circuit 101 includes the first level output end VO1 being connected with the sequential control circuit 102；
The first level output end VO1 is used in display period output high level VGH；
The sequential control circuit 102 includes the clock signal being connected with the gate driving circuit (not shown in Fig. 2)
Output end CLKO；
The 1.8V d. c. voltage signals VDD1V8 inputted from system side (mainboard of complete machine) is defeated by the system interface 20
Enter to power circuit 101, (in practical operation, the 3.3V is straight by the 3.3V d. c. voltage signals VDD3V3 inputted from system side
The power circuit 101 that stream voltage signal VDD3V3 can also be accessed inside source electrode driver) inputted by the system interface 20
The external power source integrated circuit 21, the external power source integrated circuit 21 generates positive liquid crystal drive voltage VSP and negative liquid crystal drives
Dynamic voltage VSN, and VSP and VSN are exported to the power circuit 101；
MIPI (the Mobile Industry Processor Interface, mobile Industry Processor inputted from system side
Interface) input signal inputted to the sequential control circuit 102 by the system interface 20；
The MIPI input signals include digital data signal and data sampling clock signal；
The external reset signal Reset inputted from system side is inputted to sequential control circuit by the system interface 20
102；
In practical operation, the external reset signal Reset can be that sequential control circuit can be returned to
State, the signal for running simultaneously each several part in system.
The powered-off fault monitoring unit 11 includes detector, and six registers (are stored with corresponding to 3.3V DC voltages
First register of the first threshold voltage of signal, be stored with corresponding to 1.8V d. c. voltage signals second threshold voltage
Two registers, be stored with corresponding to positive liquid crystal drive voltage VSP the 3rd threshold voltage the 3rd register, being stored with corresponds to
4th register of negative liquid crystal drive voltage VSN the 4th threshold voltage, the interruption being stored with corresponding to MIPI signals judge to refer to
The 5th register and the 6th register that is stored with corresponding to external reset signal Reset reset threshold voltage of order), compare
Device and judge module, wherein,
It is stored with first register and corresponds respectively to four first threshold voltages of four gears, for example, correspondence
It is 2.0V in the first threshold voltage of the first gear, the first threshold voltage corresponding to the second gear is 2.2V, corresponding to the 3rd
The first threshold voltage of gear is 2.4V, and the first threshold voltage corresponding to fourth speed position is 2.6V；
It is stored with second register and corresponds respectively to four second threshold voltages of four gears, for example, correspondence
It is 1.0V in the second threshold voltage of the first gear, the second threshold voltage corresponding to the second gear is 1.2V, corresponding to the 3rd
The first threshold voltage of gear is 1.4V, and the first threshold voltage corresponding to fourth speed position is 1.6V；
It is stored with 3rd register and corresponds respectively to four the 3rd threshold voltages of four gears, for example, correspondence
It is 4V in the 3rd threshold voltage of the first gear, the 3rd threshold voltage corresponding to the second gear is 4.5V, corresponding to third gear
3rd threshold voltage of position is 5.0V, and the 3rd threshold voltage corresponding to fourth speed position is 5.5V；
It is stored with 4th register and corresponds respectively to four the 4th threshold voltages of four gears, for example, correspondence
It is -4V in the 4th threshold voltage of the first gear, the 4th threshold voltage corresponding to the second gear is -4.5V, corresponding to the 3rd
4th threshold voltage of gear is -5.0V, and the 4th threshold voltage corresponding to fourth speed position is -5.5V；
There is the data sampling clock signal interruption decision instruction being stored with corresponding to the first gear in 5th register,
And interrupt decision instruction corresponding to the digital data signal of the second gear；
It is stored with 6th register and corresponds respectively to four reset threshold voltages of four gears, for example, correspondence
It is 1.0V in the reset threshold voltage of the first gear, the reset threshold voltage corresponding to the second gear is 1.2V, corresponding to the 3rd
The reset threshold voltage of gear is 1.4V, and the reset threshold voltage corresponding to fourth speed position is 1.6V；
The detector is used to detecting the magnitudes of voltage of the 3.3V d. c. voltage signals, the 1.8V d. c. voltage signals
Magnitude of voltage, the magnitude of voltage of the positive liquid crystal drive voltage VSP, the magnitude of voltage of the negative liquid crystal drive voltage VSN, the data are adopted
The magnitude of voltage of sample clock signal, the digital data signal and the external reset signal Reset；
The comparator respectively with first register, second register, the 3rd register, the described 4th
Register, the 6th register and detector connection；
For example, when the selected gear of the first register is the second gear, the comparator detector detection
The magnitude of voltage and 2.2V of obtained 3.3V d. c. voltage signals, when the comparator relatively obtains what the detector detection was obtained
When the magnitude of voltage of 3.3V d. c. voltage signals is less than 2.2V, the comparator exports the first powered-off fault indication signal and driven to described
Dynamic control unit 12；When the selected gear of the second register is third gear, the comparator detector detection
The magnitude of voltage and 1.4V of obtained 1.8V d. c. voltage signals, when the comparator relatively obtains what the detector detection was obtained
When the magnitude of voltage of 1.8V d. c. voltage signals is less than 1.4V, the comparator exports the first powered-off fault indication signal and driven to described
Dynamic control unit 12；When the selected gear of the 3rd register is the first gear, the comparator detector detection
Obtained positive liquid crystal drive voltage VSP magnitude of voltage and 4V, when the comparator relatively obtains what the detector detection was obtained
When positive liquid crystal drive voltage VSP magnitude of voltage is less than 4V, the comparator exports the first powered-off fault indication signal and driven to described
Dynamic control unit 12；When the selected gear of the 4th register is fourth speed position, the comparator detector detection
Obtained negative liquid crystal drive voltage VSN magnitude of voltage and -4V, when the comparator relatively obtains what the detector detection was obtained
When negative liquid crystal drive voltage VSN magnitude of voltage is more than -4V, the comparator exports the first powered-off fault indication signal and driven to described
Dynamic control unit 12；When the selected gear of the 6th register is the first gear, the comparator detector
Obtained external reset signal Reset magnitude of voltage and 1.0V is detected, when the comparator relatively obtains the detector detection
When obtained external reset signal Reset magnitude of voltage is less than 1.0V, the comparator exports the 3rd powered-off fault indication signal
To the drive control unit 12；
The judge module is connected with the 5th register and the detector respectively；
When the selected gear of the 5th register is the first gear, the judge module judges the detector detection
Whether obtained data sampling clock signal interrupts, the judge module when determine the data sampling clock signal interrupt when,
The judge module exports the second powered-off fault indication signal to the drive control unit 12；When the choosing of the 5th register
When determining gear for the second gear, the judge module judges whether the digital data signal that the detector detection is obtained interrupts,
The judge module is when determining data sampling clock signal interruption, and the judge module exports the second powered-off fault and indicated
Signal is to the drive control unit 12；
The drive control unit 12 is receiving the first powered-off fault indication signal, the second powered-off fault instruction letter
Number, at least one in the 3rd powered-off fault indication signal when, export the first level output end current potential to the power circuit 101
Signal is maintained, and clock signal control signal is exported to the sequential control circuit 102, it is defeated to the data drive circuit 103
Go out data voltage control signal；
After the power circuit 101 receives the first level output end current potential maintenance signal, residual charge is utilized
Postpone the first level output end VO1 power down time, i.e., as shown in Figure 3, it is ensured that the first level output end of power circuit 101
VO1 continues to output high level to sequential control circuit 102 in discharge time section Td, and the discharge time section Td durations are big
In or equal to a frame display picture duration；
When the sequential control circuit 102 receives the clock signal control signal, as shown in figure 3, the sequential
The high level that control circuit 102 is exported in discharge time section Td according to first level output end, controls the clock signal
It is high level that output end, which is exported to the current potential of the clock signal clk of the gate driving circuit, so that the raster data model
The current potential of the gate drive signal of circuit output is all pulled to high level, to cause whole grid lines to open, namely liquid crystal
Show that the grid in the pixel region of panel 23 and the thin film transistor (TFT) of grid line connection are all opened；
After the data drive circuit 103 receives the data voltage control signal, as shown in figure 3, the data
Drive circuit 103 exports ground level GND to data wire DL immediately, so that display panel shows black picture, and causes pixel
The electric charge remained in electrode is discharged to data wire by the thin film transistor (TFT) of opening, in the same of the sweep-black effective to display panel
When, residual charge is removed, splashette is effectively improved bad.
As shown in figure 3, in discharge time section Td, 1.8V d. c. voltage signal VDD1V8 power down, 3.3V direct currents
Press signal VDD3V3 power down, external reset signal Reset power down；
After in the discharge time, section Td terminates, the current potential of the first level of VO1 outputs is gradually reduced to 0, CLK current potential
It is gradually lowered as 0.
Display drive method described in the embodiment of the present invention, applied to above-mentioned display driver circuit, as shown in figure 4, institute
Stating display drive method includes：
Powered-off fault judgment step S1：When powered-off fault monitoring unit determines the power voltage input terminal by power circuit
The first powered-off fault indication signal is exported when the magnitude of voltage of the power supply voltage signal of input is not in the range of scheduled voltage, when different
The digital data signal and/or data sampling clock signal that normal down Monitor Unit unit judges are received to sequential control circuit are interrupted
When export the second powered-off fault indication signal, when powered-off fault monitoring unit determine that the sequential control circuit receives it is outer
The 3rd powered-off fault indication signal is exported when the current potential of portion's reset signal is not in the range of predetermined potential；
Powered-off fault rate-determining steps S2：The first powered-off fault indication signal is received when drive control unit, it is described
When at least one of the second powered-off fault indication signal, described 3rd powered-off fault indication signal, the drive control unit is defeated
Go out powered-off fault control signal；
Power supply step S3：After the power circuit receives the powered-off fault control signal, the power supply electricity
Road persistently exports the first level in discharge time section control first level output end；
Clock control step S4：After the sequential control circuit receives the powered-off fault control signal, when described
The first level that sequence control circuit is exported according to first level output end, control clock signal output terminal the first electricity of output
It is flat, to cause the drive circuit to control a plurality of grid line to open simultaneously；
Data drive control step S5：After the data drive circuit receives the powered-off fault control signal, institute
Data drive circuit control output predetermined discharge level is stated to a plurality of data lines.
Specifically, the powered-off fault control signal, which can include the first level output end current potential, maintains signal, clock letter
Number control signal and data voltage control signal；
The powered-off fault rate-determining steps are specifically included：When the drive control unit receives first powered-off fault
When at least one of indication signal, the second powered-off fault indication signal, described 3rd powered-off fault indication signal, the drive
Dynamic control unit exports the first level output end current potential to the power circuit and maintains signal, and defeated to the sequential control circuit
Go out clock signal control signal, to the data drive circuit output data voltage control signal；
The power supply step is specifically included：The first level output end current potential dimension is received in the power circuit
Hold after signal, the power circuit persistently exports the first level in discharge time section control first level output end；
The clock control step is specifically included：The clock signal control signal is received in the sequential control circuit
Afterwards, the first level that the sequential control circuit is exported according to first level output end, controls the clock signal output
The first level of end output, to cause the gate driving circuit to control the multirow grid line to open simultaneously；
The data drive control step is specifically included：The data voltage control is received in the data drive circuit
After signal, the data drive circuit control output predetermined discharge level to a plurality of data lines.
It is preferred that, the discharge time section was sustained for longer than or equal to the duration of a frame display picture.
Specifically, when the power voltage input terminal include 3.3V DC voltage input ends, 1.8V DC voltage input ends,
When positive liquid crystal drive voltage input and negative liquid crystal drive voltage input, the scheduled voltage scope includes the first predetermined electricity
Pressure value scope, the second scheduled voltage scope, the 3rd scheduled voltage scope and the 4th scheduled voltage scope；
The powered-off fault monitoring unit of working as is determined by the supply voltage of the power voltage input terminal input of power circuit
The first powered-off fault indication signal step is exported when the magnitude of voltage of signal is not in the range of scheduled voltage to be included：The exception is fallen
Pyroelectric monitor unit is specifically for when the electricity for determining the 3.3V d. c. voltage signals inputted by the 3.3V DC voltage input ends
The first powered-off fault indication signal is exported when pressure value is not in the range of the first scheduled voltage, when determining by 1.8V direct currents
Described the is exported when the magnitude of voltage of the 1.8V d. c. voltage signals of voltage input end input is not in the range of the second scheduled voltage
One powered-off fault indication signal, when determining by the positive liquid crystal drive voltage signal of the positive liquid crystal drive voltage input input
Magnitude of voltage not in the range of the 3rd scheduled voltage when export the first powered-off fault indication signal, when determining by described
The magnitude of voltage of the negative liquid crystal drive voltage signal of negative liquid crystal drive voltage input input is not in the range of the 4th scheduled voltage
When export the first powered-off fault indication signal.
Display device described in the embodiment of the present invention includes above-mentioned display driver circuit.
Described above is the preferred embodiment of the present invention, it is noted that for those skilled in the art
For, on the premise of principle of the present invention is not departed from, some improvements and modifications can also be made, these improvements and modifications
It should be regarded as protection scope of the present invention.
Claims (10)
1. a kind of display driver circuit, applied to display device, multirow is provided with the display base plate that the display device includes
Grid line and multiple columns of data lines；The display driver circuit includes power circuit, sequential control circuit, is connected with multiple columns of data lines
Data drive circuit and the gate driving circuit being connected with the multirow grid line, the power circuit include and the SECO
First level output end of circuit connection, first level output end is used to export the first level in the display period, described
First level is the maximum on-state voltage for being used to open the thin film transistor (TFT) in pixel region on the grid line, the SECO
Circuit includes the clock signal output terminal being connected with the gate driving circuit, it is characterised in that the display driver circuit is also
Including powered-off fault monitoring unit and drive control unit；
The powered-off fault monitoring unit is used for the power supply inputted when the power voltage input terminal determined by the power circuit
The first powered-off fault indication signal is exported when the magnitude of voltage of voltage signal is not in the range of scheduled voltage, when determining described
The digital data signal and/or data sampling clock signal that sequence control circuit is received export the instruction of the second powered-off fault when interrupting
Signal, it is defeated when determining the current potential for the external reset signal that the sequential control circuit is received not in the range of predetermined potential
Go out the 3rd powered-off fault indication signal；
The drive control unit is connected with the powered-off fault monitoring unit, is referred to for that ought receive first powered-off fault
When showing at least one of signal, the second powered-off fault indication signal, described 3rd powered-off fault indication signal, output abnormality
Power down control signal；
The power circuit is connected with the drive control unit, for after the powered-off fault control signal is received,
Discharge time section control first level output end persistently exports the first level；
The sequential control circuit is connected with the drive control unit, for receiving the powered-off fault control signal
Afterwards, in discharge time section, the first level exported according to first level output end controls the clock signal output terminal defeated
Go out the first level, to cause the gate driving circuit to control the multirow grid line to open simultaneously；
The data drive circuit is connected with the drive control unit, for after the powered-off fault control signal is received
Control exports predetermined discharge level to a plurality of data lines.
2. display driver circuit as claimed in claim 1, it is characterised in that the powered-off fault control signal includes the first electricity
Flat output terminal potential maintains signal, clock signal control signal and data voltage control signal；
The drive control unit receives the first powered-off fault indication signal, second powered-off fault specifically for working as
When at least one of indication signal, described 3rd powered-off fault indication signal, the output of the first level is exported to the power circuit
Terminal potential maintains signal, and exports clock signal control signal to the sequential control circuit, defeated to the data drive circuit
Go out data voltage control signal；
The power circuit is specifically for after the first level output end current potential maintenance signal is received, in discharge time section
First level output end is controlled persistently to export the first level；
The sequential control circuit is defeated according to first level specifically for after the clock signal control signal is received
Go out the first level of end output, control the clock signal output terminal to export the first level, to cause the gate driving circuit
The multirow grid line is controlled to open simultaneously；
The data drive circuit is specifically for the control output predetermined discharge electricity after the data voltage control signal is received
Put down to a plurality of data lines.
3. display driver circuit as claimed in claim 1, it is characterised in that the predetermined discharge level is ground level.
4. display driver circuit as claimed in claim 2, it is characterised in that the discharge time section be sustained for longer than or
Equal to the duration of a frame display picture.
5. the display driver circuit as described in any claim in Claims 1-4, it is characterised in that the supply voltage
Input includes 3.3V DC voltage input ends, 1.8V DC voltage input ends, positive liquid crystal drive voltage input and negative liquid crystal
Driving voltage input；
The scheduled voltage scope includes the first scheduled voltage scope, the second scheduled voltage scope, the 3rd predetermined voltage
It is worth scope and the 4th scheduled voltage scope；
The powered-off fault monitoring unit is specifically for straight by the 3.3V of 3.3V DC voltage input ends input when determining
The first powered-off fault indication signal is exported when flowing the magnitude of voltage of voltage signal not in the range of the first scheduled voltage, when sentencing
The magnitude of voltage broken to the 1.8V d. c. voltage signals inputted by 1.8V DC voltage input ends is not in the second scheduled voltage scope
The first powered-off fault indication signal is exported when interior, when determining by the positive liquid of the positive liquid crystal drive voltage input input
The first powered-off fault indication signal is exported when the magnitude of voltage of crystal driving voltage signal is not in the range of the 3rd scheduled voltage,
It is pre- not the 4th by the magnitude of voltage of the negative liquid crystal drive voltage signal of the negative liquid crystal drive voltage input input when determining
The first powered-off fault indication signal is exported when determining in range of voltage values.
6. a kind of display drive method, applied to the display driver circuit as described in any claim in claim 1 to 5,
Characterized in that, the display drive method includes：
Powered-off fault judgment step：When powered-off fault monitoring unit is determined by the power voltage input terminal input of power circuit
The first powered-off fault indication signal is exported when the magnitude of voltage of power supply voltage signal is not in the range of scheduled voltage, works as powered-off fault
Monitoring unit is exported when determining digital data signal and/or the data sampling clock signal interruption that sequential control circuit is received
Second powered-off fault indication signal, when powered-off fault monitoring unit determines the external reset that the sequential control circuit is received
The 3rd powered-off fault indication signal is exported when the current potential of signal is not in the range of predetermined potential；
Powered-off fault rate-determining steps：The first powered-off fault indication signal is received when drive control unit, it is described second different
When at least one of normal power down indication signal, described 3rd powered-off fault indication signal, the drive control unit output abnormality
Power down control signal；
Power supply step：After the power circuit receives the powered-off fault control signal, the power circuit is being put
The electric period controls first level output end persistently to export the first level；
Clock control step：After the sequential control circuit receives the powered-off fault control signal, the SECO
The first level that circuit is exported in discharge time section according to first level output end, control clock signal output terminal output the
One level, to cause the drive circuit to control a plurality of grid line to open simultaneously；
Data drive control step：After the data drive circuit receives the powered-off fault control signal, the data
Drive circuit control exports predetermined discharge level to a plurality of data lines.
7. display drive method as claimed in claim 6, it is characterised in that the powered-off fault control signal includes the first electricity
Flat output terminal potential maintains signal, clock signal control signal and data voltage control signal；
The powered-off fault rate-determining steps are specifically included：Indicated when the drive control unit receives first powered-off fault
When at least one of signal, the second powered-off fault indication signal, described 3rd powered-off fault indication signal, the driving control
Unit processed to the power circuit export the first level output end current potential maintain signal, and to the sequential control circuit export when
Clock signal control signal, to the data drive circuit output data voltage control signal；
The power supply step is specifically included：The first level output end current potential, which is received, in the power circuit maintains letter
After number, the power circuit persistently exports the first level in discharge time section control first level output end；
The clock control step is specifically included：After the sequential control circuit receives the clock signal control signal,
The first level that the sequential control circuit is exported according to first level output end, controls the clock signal output terminal defeated
Go out the first level, to cause the gate driving circuit to control the multirow grid line to open simultaneously；
The data drive control step is specifically included：The data voltage control signal is received in the data drive circuit
Afterwards, the data drive circuit control exports predetermined discharge level to a plurality of data lines.
8. display drive method as claimed in claim 7, it is characterised in that the discharge time section be sustained for longer than or
Equal to the duration of a frame display picture.
9. the display drive method as described in any claim in claim 6 to 8, it is characterised in that when power supply electricity
Input is pressed to include 3.3V DC voltage input ends, 1.8V DC voltage input ends, positive liquid crystal drive voltage input and negative liquid
During crystal driving voltage input, the scheduled voltage scope includes the first scheduled voltage scope, the second scheduled voltage model
Enclose, the 3rd scheduled voltage scope and the 4th scheduled voltage scope；
The powered-off fault monitoring unit of working as is determined by the power supply voltage signal of the power voltage input terminal input of power circuit
Magnitude of voltage not in the range of scheduled voltage when export the first powered-off fault indication signal step and include：The powered-off fault prison
Unit is surveyed specifically for when the magnitude of voltage for determining the 3.3V d. c. voltage signals inputted by the 3.3V DC voltage input ends
The first powered-off fault indication signal is exported when not in the range of the first scheduled voltage, when determining by 1.8V DC voltages
It is different that described first is exported when the magnitude of voltage of the 1.8V d. c. voltage signals of input input is not in the range of the second scheduled voltage
Normal power down indication signal, when the electricity for determining the positive liquid crystal drive voltage signal by the positive liquid crystal drive voltage input input
The first powered-off fault indication signal is exported when pressure value is not in the range of the 3rd scheduled voltage, when determining by the negative liquid
It is defeated when the magnitude of voltage of the negative liquid crystal drive voltage signal of crystal driving voltage input input is not in the range of the 4th scheduled voltage
Go out the first powered-off fault indication signal.
10. a kind of display device, it is characterised in that including the display driving as described in any claim in claim 1 to 5
Circuit.
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| CN201710335131.9A CN107134266B (en) | 2017-05-12 | 2017-05-12 | Display driver circuit, display driving method and display device |
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| CN107909979A (en) * | 2017-12-08 | 2018-04-13 | 南京中电熊猫平板显示科技有限公司 | Liquid crystal display device and the method for improving display panel power down splashette |
| CN108153370A (en) * | 2017-12-28 | 2018-06-12 | 杭州迪普科技股份有限公司 | A kind of lower electric time sequence control device and method |
| CN109192164A (en) * | 2018-10-10 | 2019-01-11 | 惠科股份有限公司 | Display device and its method for eliminating shutdown ghosting image |
| CN109300446A (en) * | 2018-12-12 | 2019-02-01 | 惠科股份有限公司 | Guard method, display panel and the computer readable storage medium of display panel |
| CN110767192A (en) * | 2019-11-07 | 2020-02-07 | 京东方科技集团股份有限公司 | Control device and control method of display module and display device |
| CN110784571A (en) * | 2019-10-31 | 2020-02-11 | 维沃移动通信有限公司 | Electronic equipment and image display method |
| CN111681606A (en) * | 2020-07-22 | 2020-09-18 | 宁波视睿迪光电有限公司 | Protection control power supply, OLED screen control system and OLED screen |
| CN112150976A (en) * | 2019-06-28 | 2020-12-29 | 格科微电子（上海）有限公司 | Power-down screen cleaning method for liquid crystal display screen |
| CN113205772A (en) * | 2020-02-02 | 2021-08-03 | 联詠科技股份有限公司 | Display device driving method and related driving circuit |
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| CN111681606A (en) * | 2020-07-22 | 2020-09-18 | 宁波视睿迪光电有限公司 | Protection control power supply, OLED screen control system and OLED screen |
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