CN106952949B - Graphene field effect transistor and forming method thereof - Google Patents
Graphene field effect transistor and forming method thereof Download PDFInfo
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1606—Graphene
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
A kind of graphene field effect transistor and forming method thereof, wherein the forming method of the graphene field effect transistor includes: offer substrate, and the substrate includes first area, second area and the third region between first area and second area；Graphite material is formed on the substrate；The graphite material is handled, multiple graphene layers are formed；A part of the multiple graphene layers of the first area and second area is removed from thickness direction, forms single-layer graphene layer or bilayer graphene layer；Gate dielectric layer is formed in the multi-layer graphene layer surface in third region；The single-layer graphene layer of the first area and second area or a part of bilayer graphene layer are removed, source region and drain region are respectively formed；Electrode is respectively formed on source region, drain region and gate dielectric layer.The embodiment of the present invention realizes the growth in situ of graphene, using top-down graphene preparation method, simplifies process, technique is easily controllable.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of graphene field effect transistor and its formation sides
Method.
Background technique
Graphene is a kind of New Two Dimensional nano material with plane benzene ring structure, and single-layer graphene thickness only has about one
A atomic layer level thickness；Due to the band structure of its zero band gap, electron mobility can reach the 31 percent of the light velocity at room temperature,
Resistivity ratio copper or silver are lower, and due to the effect of chemical bond between carbon atom, the mechanical strength of graphene is more taller than steel
100 times.Just because of these excellent performances that the special construction of graphene is showed, graphene has been applied at present
In fields such as transistor, transparent electrode, display screen, supercapacitor, solar batteries, and achieve good results.
However, the plurality of advantages of graphene can not answer since single-layer graphene or bilayer graphene itself do not have energy gap
For in field effect transistor.And hydrogenate (Hydrogenated) graphene and multilayer (three layers or more) graphene has can
The energy gap of adjusting, therefore may be directly applied under room temperature in the manufacture of field effect transistor.For single-layer graphene or the double-deck stone
Black alkene can also generate energy gap in the case where carrying out quantum confinement to it, such as form single-layer graphene nanobelt or double-layer graphite
Alkene nanobelt enables it to be applied to graphene field effect transistor.
At present in the manufacture craft of graphene field effect transistor, the preparation method of graphene mainly includes micromechanics stripping
From method, chemical stripping method, silicon carbide epitaxial growth method and chemical vapour deposition technique.Wherein chemical vapour deposition technique includes: to adopt
With chemical vapour deposition technique by graphene growth on the metallic substrate, then graphene is transferred to from metal substrate nonmetallic
It is used on substrate.Micromechanics stripping method includes: using micromechanics stripping method from highly oriented pyrolytic graphite (Highly
Oriented Pyrolytic Graphene, HOPG) in obtain graphene, transfer on nonmetallic substrate.However both
All there are obvious drawbacks for method, because inevitably introducing some non-ideal factors during graphene transfer,
Such as fold, broken hole, impurity, these can all have an impact to the electric property of device, and in addition to this, the graphene of transfer is often
It is difficult to form good Ohmic contact with nonmetallic substrate.
Summary of the invention
Present invention solves the technical problem that being to propose a kind of graphene field effect transistor and forming method thereof, stone is simplified
The preparation flow of black alkene field effect transistor, and preparation process is easily controllable.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of forming method of graphene field effect transistor,
Include: offer substrate, the substrate include first area, second area and between first area and second area
Three regions；Graphite material is formed on the substrate；The graphite material is handled, multiple graphene layers are formed；From thickness
Direction removes a part of the multiple graphene layers of the first area and second area, forms single-layer graphene layer or the double-deck stone
Black alkene layer；Gate dielectric layer is formed in the multi-layer graphene layer surface in third region；Remove the first area and second area
Single-layer graphene layer or bilayer graphene layer a part, be respectively formed source region and drain region；In source region, drain region and gate medium
Electrode is respectively formed on layer.
Optionally, the graphite material is highly oriented pyrolytic graphite；The thickness range of the highly oriented pyrolytic graphite isExtremely
Optionally, the processing graphite material, the method for forming multiple graphene layers include being carved using atomic layer
Etching method performs etching, and the thickness range for forming the multiple graphene layers isExtremely
Optionally, a part of the multiple graphene layers of the first area and second area, shape are removed from thickness direction
It include: to form patterned layer on the multiple graphene layers in third region at single-layer graphene layer or bilayer graphene layer,
Expose the multiple graphene layers of first area and second area to be etched；Using the patterned layer as mask, using atom
The multiple graphene layers of layer lithographic method etching first area and second area, form single-layer graphene layer or bilayer graphene
Layer；Remove the patterned layer.
Optionally, the single-layer graphene layer of the formation or the thickness range of bilayer graphene layer areExtremely
Optionally, the one of the single-layer graphene layer or bilayer graphene layer of the removal first area and second area
Part, the method for being respectively formed source region and drain region include: along perpendicular to orientation, remove the first area respectively
The single-layer graphene layer of a part and second area of single-layer graphene layer or bilayer graphene layer or bilayer graphene layer
A part forms the single-layer graphene nanobelt or bilayer graphene nanobelt for being located at first area and second area, makees respectively
For source region and drain region.
Optionally, the single-layer graphene nanobelt of formation or bilayer graphene nanobelt are along perpendicular to transistor channel
The size range of length direction isExtremely
Optionally, the single-layer graphene layer of the first area and second area or a part of bilayer graphene layer are removed
Method include use atomic layer lithographic method.
Optionally, the atomic layer lithographic method includes using dry etching and wet etching step.
Optionally, the etching gas of the dry etching includes using containing any one in zinc, copper, iron, cadmium and silver
Any one gas in the plasma or nitrogen of the organic compound of metal ion species, fluorine gas, oxygen and chlorine.
Optionally, the wet etching includes being performed etching using hydrochloric acid, hydrofluoric acid, phosphoric acid, sulfuric acid or nitric acid.
Optionally, the atomic layer lithographic method is carried out under Raman spectrum monitoring.
Correspondingly, the embodiment of the present invention also provides a kind of graphene field effect transistor, comprising: substrate, the substrate packet
Include first area, second area and the third region between first area and second area；Positioned at first area and
The single-layer graphene nanobelt or bilayer graphene nanobelt in two regions, the single layer stone positioned at first area and second area
Black alkene nanobelt or bilayer graphene nanobelt constitute source region and the drain region of the field effect transistor, positioned at the more of third region
Layer graphene layer；Positioned at the gate dielectric layer of the multi-layer graphene layer surface in third region；Positioned at source region, drain region and gate dielectric layer
On electrode.
Optionally, the thickness range of the single-layer graphene nanobelt or bilayer graphene nanobelt isExtremelyThe single-layer graphene nanobelt or bilayer graphene nanobelt are along the size perpendicular to transistor channel length direction
Range isExtremely
Optionally, the thickness range of the multiple graphene layers isExtremely
Optionally, the substrate includes substrate and the lining positioned at substrate, and the material of the lining is SiOX,
The value of middle X is between 0.5 to 3.
Optionally, the SiOXThickness range be 200nm to 350nm.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
In the forming method of the embodiment of the present invention, by the way that graphite material is formed on the substrate, using graphite material system
Multiple graphene layers and single-layer graphene layer or bilayer graphene layer needed for standby formation graphene field effect transistor, realize
The growth in situ of graphene overcomes during graphene is shifted substrate, and the non-ideal factor of introducing is to graphene field
The destruction of effect transistor performance；And the embodiment of the present invention uses top-down graphene preparation method, simplifies preparation
Process, and preparation process is easily controllable.
Optionally, the embodiment of the present invention utilizes atomic layer etching side using highly oriented pyrolytic graphite as graphite material
Legal system takes multiple graphene layers and single-layer graphene layer or bilayer graphene, has the graphene planes formed more smooth, single
The advantages that one lattice region is larger, and graphene can be easily separated between layers；Micromechanics stripping method is overcome by highly directional pyrolysis
Graphite produces the uncontrollable of multiple graphene layers and area during single-layer graphene layer or bilayer graphene layer and quality, and
Graphene is easy impaired disadvantage in transmitting transfer process.
The graphene field effect transistor of the embodiment of the present invention, by single-layer graphene nanobelt or the double-deck stone with energy gap
Black alkene nanobelt as source-drain area, multiple graphene layers between source-drain area so that between source-drain area and with single layer stone
The single-layer graphene layer or the double-deck stone in multiple graphene layers that black alkene nanobelt or bilayer graphene nanobelt are located on the same floor
Black alkene layer is as channel region.Since single-layer graphene layer or bilayer graphene have the ballistic transport ability of carrier, and it is very high
Carrier mobility so that being formed by graphene field effect transistor with very high carrier mobility.
Detailed description of the invention
Fig. 1 to Fig. 9 is cuing open for the intermediate structure of the forming method of the graphene field effect transistor of one embodiment of the invention
Face schematic diagram.
Specific embodiment
The present invention provides a kind of graphene field effect transistor and forming method thereof, is subject to reference to the accompanying drawing specifically
It is bright.
Fig. 1 to Fig. 9 is cuing open for the intermediate structure of the forming method of the graphene field effect transistor of one embodiment of the invention
Face schematic diagram.
With reference to Fig. 1, substrate 100 is provided, the substrate 100 includes first area 100a, second area 100b and is located at
Third region 100c between first area 100a and second area 100b；The substrate 100 includes substrate 101 and lining
102, the lining 102 is formed on substrate 101；Graphite material 110 is formed in the substrate 100.
In embodiments of the present invention, the substrate 101 can be on silicon substrate, silicon-Germanium substrate, silicon carbide substrates, insulator
Silicon substrate, germanium substrate on insulator or III-V compound substrate, such as gallium nitride substrate or gallium arsenide substrate etc.；The lining
Bottom 101 can also be the substrate formed by other semiconductor materials；The substrate 101 is also selected from epitaxial layer or extension
Layer silicon-on.In the present embodiment, the substrate 101 is monocrystalline substrate.
The lining 102 can be SiOx, wherein the value of X is between 0.5 to 3.The SiO of formationxThe thickness range of lining is
200nm to 350nm.It should be noted that the lining 102 is used to be determined with Raman spectrum by highly oriented pyrolytic graphite subsequent
When the number of plies of graphene obtained, it is resolved out the structure of graphene.In the present embodiment, the material of the lining 102
For SiO2, form the SiO2With a thickness of 300nm.
The material of the graphite material 110 is highly oriented pyrolytic graphite (HOPG).The thickness of the highly oriented pyrolytic graphite
Spending range isExtremelySpecifically, highly oriented pyrolytic graphite described in the present embodiment with a thickness of
With reference to Fig. 2, the highly directional pyrolysis stone is handled using atomic layer etching (Atomic Layer Etch, ALE) method
Ink carries out the removing of monoatomic layer to it, to obtain multiple graphene layers 120.
The atomic layer lithographic method includes dry etching and wet etching step: first sputtering institute with dry etching gas
State the surface of highly oriented pyrolytic graphite；At again with the reagent of wet etching to the surface of the highly oriented pyrolytic graphite after sputtering
Reason, so repeats the above steps, until obtaining the multiple graphene layers 120 that number of plies uniformity is preferable and defect is less.It needs
Illustrate, the multiple graphene layers 120 are made of n-layer single-layer graphene layer 121, and wherein n is more than or equal to 3.
The gas of the dry etching includes using containing any one metal ion in zinc, copper, iron, cadmium and silver
Any one gas in the plasma or nitrogen of organic compound, fluorine gas, oxygen and chlorine, the flow of etching gas
For 1sccm to 5000sccm, power is 100W to 1000W, and bias voltage is 0V to 500V, and frequency is 2MHz to 4GHz, etching
Temperature is -140 DEG C to 200 DEG C, and pressure is 1mTorr to 1000Torr, and sputtering time is 1s to 100s.The wet etching
Reagent includes one of hydrochloric acid, hydrofluoric acid, phosphoric acid, sulfuric acid or nitric acid or any combination thereof, the wet etching reagent with
H2The volume ratio of O is 1:1 to 1:1000, and the processing time is 1s to 500s.The thickness model of the multiple graphene layers 120 formed
Enclose forExtremely
In the present embodiment, the gas of the dry etching is oxygen, and the flow of gas is 20sccm, power 500W, partially
Setting voltage is 200V, and frequency 5MHz, etching temperature is 50 DEG C, pressure 20Torr, sputtering time 50s.The wet process is carved
Erosion using hydrochloric acid as etching agent, H in the hydrochloric acid solution2The volume ratio of O and HCl is 200:1, and the processing time is 100s.Shape
At the multiple graphene layers 120 with a thickness of
It further include utilizing Raman spectrum pair while handling the highly oriented pyrolytic graphite using atomic layer lithographic method
The structure of highly oriented pyrolytic graphite in processing is identified, the number of plies of obtained multiple graphene layers 120 is etched with determination, together
When control atomic layer lithographic method cycle-index.
With reference to Fig. 3, mask layer is formed on 120 surface of multiple graphene layers of the third region 100c of the substrate 100
130, the mask layer 130 is photoresist layer.The multiple graphene layers 120 of the first area 100a and second area 100b divide
It is not used to form source region and drain region, the multiple graphene layers 120 of the third region 100c are used to form channel region.The mask
Layer 130 is for protecting the multiple graphene layers 120 of third region 100c during subsequent etching.
It is mask with the mask layer 130 with reference to Fig. 4, first area 100a and the is etched using atomic layer lithographic method
The multiple graphene layers 120 of two region 100b obtain single-layer graphene layer or bilayer graphene layer 121.
The atomic layer lithographic method includes dry etching and wet etching step.The gas of the dry etching includes adopting
With plasma or nitrogen, the fluorine of the organic compound containing any one metal ion in zinc, copper, iron, cadmium and silver
Any one gas in gas, oxygen and chlorine, the flow of etching gas are 1sccm to 5000sccm, power be 100W extremely
1000W, bias voltage are 0V to 500V, and frequency is 2MHz to 4GHz, and etching temperature is -140 DEG C to 200 DEG C, and pressure is
1mTorr to 1000Torr, sputtering time are 1s to 100s.The reagent of the wet etching includes hydrochloric acid, hydrofluoric acid, phosphoric acid, sulphur
One of acid or nitric acid or any combination thereof, the wet etching reagent and H2The volume ratio of O is 1:1 to 1:1000, place
The reason time is 1s to 500s.Formed the single-layer graphene layer or bilayer graphene layer 121 with a thickness ofExtremely
In the present embodiment, the gas of the dry etching is oxygen, and the flow of gas is 20sccm, power 500W, partially
Setting voltage is 200V, and frequency 5MHz, etching temperature is 50 DEG C, pressure 200Torr, sputtering time 50s.The wet process is carved
Erosion using hydrochloric acid as etching agent, H in the hydrochloric acid solution2The volume ratio of O and HCl is 200:1, and the processing time is 100s.Shape
At the single-layer graphene layer 121 with a thickness of
While handling multiple graphene layers 120 using atomic layer lithographic method, also while Raman spectrum is utilized
The number of plies of multiple graphene layers 120 in processing is identified, to determine obtained single-layer graphene layer or bilayer graphene
The number of plies of layer 121 and the cycle-index for controlling atomic layer lithographic method.
Fig. 5 and Fig. 6 is the schematic diagram of the section structure of the Fig. 4 along the direction AA ' (or BB ').
With reference to Fig. 5, it can be seen that be located at the single layer of first area 100a (or second area 100b) after above-mentioned technique
Graphene layer or bilayer graphene layer 121 are at it along perpendicular to orientation, i.e. perpendicular to electron-transport side in channel region
Upward relative size is larger.It should be noted that since single-layer graphene layer or bilayer graphene layer 121 itself do not have energy
Gap, therefore can not directly be applied in the manufacture of field effect transistor.And research achievement in recent years shows mono-layer graphite
Alkene layer or bilayer graphene are under conditions of quantum limitation effect (Quantum Confinement Effects), it can be achieved that energy
Semiconductive is presented in the opening of gap.Therefore the single-layer graphene layer or bilayer graphene layer 121 to acquisition are needed in the present embodiment
Quantum confinement is carried out, to realize its semiconductive.For positioned at the multiple graphene layers 120 of third region 100c, due to
Itself have energy gap, therefore channel region material can be directly used as applied in the manufacture of graphene field effect transistor.
It is the single-layer graphene layer or bilayer graphene for removing first area 100a and second area 100b with reference to Fig. 6, Fig. 6
A part of 121 (as shown in Figure 5) of layer, the structural schematic diagram after quantum confinement has been carried out to it.
To 121 (such as Fig. 5 of single-layer graphene layer or bilayer graphene layer for being located at first area 100a and second area 100b
It is shown) at it along perpendicular to orientation, i.e. perpendicular to quantum confinement is carried out in channel region on electron-transport direction, with shape
At the single-layer graphene nanobelt or bilayer graphene nanobelt for being located at first area 100a and second area 100b
(Graphene Nanoribbon) 121a and 121b, respectively as source region and drain region.
Specifically, in the present embodiment using the method removal part that photoetching and atomic layer etch be located at first area 100a and
The single-layer graphene layer or bilayer graphene layer 121 of second area 100b, comprising: need to form single-layer graphene nanobelt or
The region of bilayer graphene nanobelt 121a and 121b form patterned photoresist layer, the patterned photoresist layer exposure
It is adopted using the patterned photoresist layer as mask in 121 region of single-layer graphene layer or bilayer graphene layer for needing to remove out
Etch the single-layer graphene layer or bilayer graphene layer 121 with atomic layer lithographic method, formed single-layer graphene nanobelt or
Bilayer graphene nanobelt 121a and 121b.The single-layer graphene nanobelt or the edge bilayer graphene nanobelt 121a and 121b
Size range perpendicular to transistor channel length direction isExtremely
The atomic layer lithographic method includes dry etching and wet etching step.In the present embodiment, the dry etching
Gas be oxygen, the flow of gas is 20sccm, power 500W, bias voltage 200V, frequency 5MHz, etching temperature
It is 50 DEG C, pressure 200Torr, sputtering time 50s.For the wet etching using hydrochloric acid as etching agent, the hydrochloric acid is molten
H in liquid2The volume ratio of O and HCl is 200:1, and the processing time is 100s.Formed the single-layer graphene nanobelt 121a and
The edge 121b is perpendicular to the size in transistor channel length direction
With reference to Fig. 7, be respectively formed source region and drain region single-layer graphene nanobelt or bilayer graphene nanobelt 121a and
After 121b, it is located between source-drain area, and with single-layer graphene nanobelt or bilayer graphene nanobelt 121a and 121b
Single-layer graphene layer or bilayer graphene layer 121c in the multiple graphene layers 120 of same layer is as channel region.Due to single layer
Graphene or bilayer graphene have the ballistic transport ability of carrier, so that being formed by graphene field effect transistor has
Very high carrier mobility.
With reference to Fig. 8, the electrode 161 of source electrode and the electrode 162 of drain electrode are formed.
In the present embodiment, the material of the electrode 162 of the electrode 161 and drain electrode of the source electrode is gold.Form the electrode
161 and 162 processing step includes using chemical vapor deposition, electron beam lithography and deep-UV lithography.First using chemistry
Vapor deposition method is in source region and drain region deposition of electrode material layer, then etches the electrode material layer to form the electrode 161
With 162.Specifically, in single-layer graphene nanobelt or bilayer graphene nanobelt 121a and 121b table far from source region and drain region
When face, the electrode material layer is performed etching using deep-UV lithography；It is received in the single-layer graphene close to source region and drain region
Rice band or the surface bilayer graphene nanobelt 121a and 121b at, using electron beam lithography to the remaining electrode material layer into
Row etching, to avoid in etching process to the single-layer graphene nanobelt or bilayer graphene nanobelt 121a of source region and drain region and
It is damaged caused by 121b.
Then, the mask layer 130 is removed.
With reference to Fig. 9, gate dielectric layer 150 is formed on 120 surface of multiple graphene layers；In 150 surface shape of gate dielectric layer
At the electrode 163 of grid.
The material of the gate dielectric layer 150 includes silica and high dielectric constant material, the gate dielectric layer 150 of formation
Thickness range beExtremelyHigh dielectric constant material described in the present embodiment is hafnium oxide；Form the silica
Technique is chemical vapor deposition, formed the silica with a thickness ofThe technique for forming the hafnium oxide is atomic layer deposition
Product, formed the hafnium oxide with a thickness of
The material for forming the electrode 163 of the grid is copper or gold.In the present embodiment, the electrode 163 of grid is formed
Material is gold, and the processing step for forming the electrode 163 of the grid includes using chemical vapor deposition, electron beam lithography and depth
Ultraviolet photolithographic, specific forming method is similar with the method for electrode 162 of the electrode 161 and drain electrode that are previously formed source electrode, herein not
It repeats again.
Correspondingly, the present embodiment also provides a kind of structure of graphene field effect transistor.
With continued reference to Fig. 9, the graphene field effect transistor includes: substrate 100, and the substrate 100 includes the firstth area
Domain 100a, second area 100b and the third region 100c between first area 100a and second area 100b；Single layer
Graphene nanobelt or bilayer graphene nanobelt, the list including being located at the first area 100a and second area 100b
Layer graphene nanobelt or bilayer graphene nanobelt 121a and 121b, respectively as source region and drain region；Positioned at the third area
The multiple graphene layers 120 of domain 100c, as channel region；Gate dielectric layer 150, positioned at the multiple graphene layers of third region 100c
120 surfaces；And electrode 161, the electrode 162 of drain electrode and the electrode 163 of grid of source electrode, it is located at source region, drain region and grid
The surface of dielectric layer 150.
The substrate 100 includes substrate 101 and the lining 102 on substrate 101.The material of the lining 102
For SiOX, wherein the value of X is between 0.5 to 3；The SiOXThickness range be 200nm to 350nm.It is described in the present embodiment
The material of lining 102 is SiO2, the SiO2With a thickness of 300nm.
It should be noted that the single-layer graphene nanobelt or bilayer graphene nanobelt as source region and drain region
121a and 121b, be along perpendicular to the single-layer graphene nanobelt that have passed through quantum confinement on transistor channel length direction or
Bilayer graphene nanobelt has energy gap, has the requirement of semiconductive with this to meet the material for preparing field effect transistor.
The thickness range of the single-layer graphene nanobelt or bilayer graphene nanobelt 121a and 121b isExtremelyIt is described
Single-layer graphene nanobelt or bilayer graphene nanobelt 121a and 121b are along perpendicular to the ruler on transistor channel length direction
Very little range isExtremelyThe thickness range of the multiple graphene layers 120 isExtremely
In one embodiment, the single-layer graphene nanobelt or bilayer graphene nanobelt 121a and 121b are single layer
Graphene nanobelt, with a thickness ofSingle-layer graphene the nanobelt 121a and 121b are along perpendicular to transistor channel length
Size on direction isThe multiple graphene layers 120 with a thickness of
The material of the gate dielectric layer 150 includes silica and high dielectric constant material, the thickness of the gate dielectric layer 150
Range isExtremelyIn one embodiment, the material of the gate dielectric layer 150 be silica and hafnium oxide, it is described
Silica with a thickness ofThe hafnium oxide with a thickness of
The material of the electrode 162 of the electrode 161 and drain electrode of the source electrode is gold, and the material of the electrode 163 of the grid is
Copper or gold.In the present embodiment, the electrode 161 of the source electrode, the electrode 162 of drain electrode, grid the material of electrode 163 be gold.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (17)
1. a kind of forming method of graphene field effect transistor characterized by comprising
Substrate is provided, the substrate include first area, second area and between first area and second area the
Three regions；
Graphite material is formed on the substrate；
The graphite material is handled, multiple graphene layers are formed；
A part of the multiple graphene layers of the first area and second area is removed from thickness direction, forms single-layer graphene
Layer or bilayer graphene layer；
Gate dielectric layer is formed in the multi-layer graphene layer surface in third region；
The single-layer graphene layer of the first area and second area or a part of bilayer graphene layer are removed, source is respectively formed
Area and drain region；
Electrode is respectively formed on source region, drain region and gate dielectric layer.
2. forming method as described in claim 1, which is characterized in that the graphite material is highly oriented pyrolytic graphite；Institute
The thickness range for stating highly oriented pyrolytic graphite isExtremely
3. forming method as described in claim 1, which is characterized in that the processing graphite material forms multilayer stone
The method of black alkene layer includes being performed etching using atomic layer lithographic method, and the thickness range for forming the multiple graphene layers isExtremely
4. forming method as described in claim 1, which is characterized in that remove the first area and the secondth area from thickness direction
A part of the multiple graphene layers in domain, forms single-layer graphene layer or bilayer graphene layer includes:
Patterned layer is formed on the multiple graphene layers in third region, exposes first area and the secondth area to be etched
The multiple graphene layers in domain；
Using the patterned layer as mask, using the multi-layer graphene of atomic layer lithographic method etching first area and second area
Layer forms single-layer graphene layer or bilayer graphene layer；
Remove the patterned layer.
5. forming method as claimed in claim 4, which is characterized in that the single-layer graphene layer or bilayer graphene of the formation
Layer thickness range beExtremely
6. forming method as described in claim 1, which is characterized in that the list of the removal first area and second area
A part of layer graphene layer or bilayer graphene layer, the method for being respectively formed source region and drain region includes: along perpendicular to ditch road length
Degree direction removes the single-layer graphene layer of the first area or a part and second area of bilayer graphene layer respectively
Single-layer graphene layer or bilayer graphene layer a part, formed and be located at the single-layer graphene of first area and second area and receive
Rice band or bilayer graphene nanobelt, respectively as source region and drain region.
7. forming method as claimed in claim 6, which is characterized in that the single-layer graphene nanobelt of formation or the double-deck stone
Black alkene nanobelt edge is perpendicular to the size range in transistor channel length directionExtremely
8. forming method as claimed in claim 6, which is characterized in that remove the single layer stone of the first area and second area
The method of a part of black alkene layer or bilayer graphene layer includes using atomic layer lithographic method.
9. the forming method as described in claim 3,4 or 8, which is characterized in that the atomic layer lithographic method includes using dry
Method etching and wet etching step.
10. forming method as claimed in claim 9, which is characterized in that the etching gas of the dry etching includes using to contain
Have the organic compound of any one metal ion in zinc, copper, iron, cadmium and silver plasma or nitrogen, fluorine gas,
Any one gas in oxygen and chlorine.
11. forming method as claimed in claim 9, which is characterized in that the wet etching include using hydrochloric acid, hydrofluoric acid,
Phosphoric acid, sulfuric acid or nitric acid perform etching.
12. the forming method as described in claim 3,4 or 8, which is characterized in that the atomic layer lithographic method is in Raman light
Spectrum monitoring is lower to be carried out.
13. a kind of graphene field effect transistor characterized by comprising
Substrate, the substrate include first area, second area and the third area between first area and second area
Domain；
Single-layer graphene nanobelt or bilayer graphene nanobelt positioned at first area and second area, it is described to be located at the firstth area
The single-layer graphene nanobelt or bilayer graphene nanobelt of domain and second area constitute the field effect transistor source region and
Drain region, the multiple graphene layers positioned at third region；
Positioned at the gate dielectric layer of the multi-layer graphene layer surface in third region；
Electrode on source region, drain region and gate dielectric layer.
14. graphene field effect transistor as claimed in claim 13, which is characterized in that the single-layer graphene nanobelt or
The thickness range of bilayer graphene nanobelt isExtremelyThe single-layer graphene nanobelt or bilayer graphene are received
Rice band edge is perpendicular to the size range in transistor channel length directionExtremely
15. graphene field effect transistor as claimed in claim 13, which is characterized in that the thickness of the multiple graphene layers
Range isExtremely
16. graphene field effect transistor as claimed in claim 13, which is characterized in that the substrate includes substrate and position
In the lining of substrate, the material of the lining is SiOX, wherein the value of X is between 0.5 to 3.
17. graphene field effect transistor as claimed in claim 16, which is characterized in that the SiOXThickness range be
200nm to 350nm.
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