CN106933766A - A kind of bus marco implementation method - Google Patents
A kind of bus marco implementation method Download PDFInfo
- Publication number
- CN106933766A CN106933766A CN201511013476.XA CN201511013476A CN106933766A CN 106933766 A CN106933766 A CN 106933766A CN 201511013476 A CN201511013476 A CN 201511013476A CN 106933766 A CN106933766 A CN 106933766A
- Authority
- CN
- China
- Prior art keywords
- bus
- level
- comparator
- signal
- patterns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000001914 filtration Methods 0.000 claims abstract description 25
- 238000004891 communication Methods 0.000 claims abstract description 20
- 230000011664 signaling Effects 0.000 claims description 39
- 230000000630 rising effect Effects 0.000 claims description 5
- 238000001514 detection method Methods 0.000 abstract description 4
- 239000000779 smoke Substances 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 3
- 101100464782 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CMP2 gene Proteins 0.000 description 2
- 101100464779 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CNA1 gene Proteins 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Small-Scale Networks (AREA)
- Dc Digital Transmission (AREA)
Abstract
The present invention relates to a kind of network type smoke detection field, specifically a kind of bus marco implementation method, including：Judge that bus protocol is two level or three level；Configuration relevant parameter；Open the Enable Pin of comparator；Compare bus voltage and threshold voltage；Judge that reception pattern is up patterns or down patterns；Carry out burr filtering process；Last bus communication module carries out Communication processing.The present invention can not only solve two level bus protocols, and can solve the problem that three level bus protocols, and can filter the burr of different in width.
Description
Technical field
The present invention relates to network type smoke detection field, and in particular to a kind of bus marco implementation method in smoke detection field.
Background technology
In network type smoke detection field, master controller and each connected by two-wire bus from general between detector.Two-wire bus support the two kinds or three kinds bus protocols of level state.There was only 0,1 two kind of encoding state during the bus protocol signaling of two kinds of level, the length of cooperation time is needed to realize different codings, and can have 0 during the bus protocol signaling of three kinds of level, 1,2 three kind of encoding state, it is not necessary to coordinating the length of time can just realize more codings.Identical coding is realized within a period of time, three kinds of bus protocols of level are more shorter than the bus protocol code length of two kinds of level, and code efficiency is higher, therefore system, when realizing, three kinds of bus protocols of level can greatly shorten polling cycle of the main frame to slave.Existing bus marco implementation method can only process two kinds of bus protocols of level, and communication is difficult to for the bus protocol of three kinds of level.
As shown in Figure 1, it is the schematic diagram of existing bus marco implementation method, this method only supports that the only two kinds bus protocols of level state, main frame carry out signaling communication by changing bus voltage to slave, by comparator all the way（Referred to as CMP）By bus voltage（Referred to as VLN24）With threshold voltage（Referred to as VTH）It is compared, threshold voltage（VTH）Configured by receiving threshold voltage register, threshold voltage（VTH）It is defined as an absolute value, if VLN24>VTH
, the comparator signaling output signal after comparing（Referred to as rxd signals）It is high level, conversely, the rxd signals after comparing are low level, the rxd signals after comparing are directly entered bus communication module and are communicated as input signal.
Existing bus marco implementation method there is problems in addition to it can only process two kinds of bus protocols of level：One when being that main frame carries out signaling using different signaling patterns, and existing bus marco implementation method is processed respectively using up reception patterns and down reception patterns, wastes follow-up hardware spending；Two is the interference that noise can not be eliminated in bus marco to communicating, and this is to provide analog filtering to this problem, existing method, can not be filtered because of short duration bus voltage fluctuation is excessive in the external electric capacity in LN24CAP ports, but this method（Miss signaling）, sending mode when return code current drag down the burr that bus voltage reason etc. causes.
The content of the invention
The purpose of the present invention is exactly to solve the problems, such as prior art, so as to provide a kind of bus marco implementation method, the method is not only suitable in the bus protocols communication that there is two kinds or three kinds level states on two-wire bus, while the burr of different in width can be filtered in bus and burr width range is adjustable.
In order to solve the above-mentioned technical problem, the technical solution adopted in the present invention is：A kind of bus marco implementation method, based on the digital signal processing module in bus circuit, reception pattern mask register（RXMODE）, bus protocol level state mask register（RXVTH）, two-way comparator（CMP1 and CMP2）, two-way comparator difference it is corresponding receive threshold voltage register and bus communication module, it is characterised in that comprise the following steps：（1）The bus protocol for judging host side signaling is two kinds of level or three kinds of level；（2）If two kinds of level, then bus protocol level state selection signal is configured by bus protocol level state mask register（RXVTH）Be 1, i.e. RXVTH=1；If three kinds of level, then bus protocol level state selection signal is configured by bus protocol level state mask register（RXVTH）Be 0, i.e. RXVTH=0；（3）If two kinds of level, then the Enable Pin of any comparator all the way is opened；If three kinds of level, then the Enable Pin of two-way comparator is opened；（4）Per comparator all the way by bus voltage（VLN24）With the threshold voltage for receiving the setting of threshold voltage register（VTH）It is compared the signaling signal for obtaining the comparator（rxd）, and this signaling signal is sent to the numerical portion of bus communication module；（5）Judge the reception pattern mask register（RXMODE）Reception pattern, the reception pattern mask register defines two kinds of reception patterns, respectively down patterns and up patterns, and down patterns are high level when referring to bus normal work, are low level during signaling；It is low level when up patterns refer to bus normal work, is high level during signaling；If reception pattern mask register（RXMODE）In be provided that 1（That is high level）, then reception pattern is up patterns；If Mode Selection register（RXMODE）In be provided that 0（That is low level）, then reception pattern is down patterns；（6）Enter row selection signal treatment to reception pattern, if up patterns, by step（4）The signaling signal of middle comparator（rxd）Follow-up filtering process is carried out by digital signal processing module after being carried out after negating；If down patterns, by step（4）The signaling signal of middle comparator directly carries out follow-up filtering process by digital signal processing module；（7）Signaling signal after after filtering is carried out into Communication processing by bus communication module.
The control method that above-mentioned two-way comparator Enable Pin is opened is as follows：The two-way comparator Enable Pin gates structure control by two-way, is made up of two selector concatenations per gating structure all the way, is divided into front end selector and rear end selector, and the input of the front end selector is high level（I.e. 1）, low level（I.e. 0）With the output selection signal of two comparator results（RXD_SEL）, the output selection signal of two comparator results（RXD_SEL）Refer to one of them of the signaling signal rxd of selection two-way comparator；The input of the rear end selector is low level（I.e. 0）, front end selector output and step（1）The value of the RXVTH of middle setting；The output of the rear end selector is to should be used as opening the enable end signal of comparator, and set its output to enable end signal is low level（I.e. 0）Effectively.
Above-mentioned digital signal processing module includes digital filter, 8 digit counters and digital filter registers, the step（6）Implementation process it is as follows：The width of the burr to be filtered is set by digital filtering register（Abbreviation M）, counter is by the step（4）The starting of the signaling signal for obtaining is started counting up along beginning from 0, when detecting edge（Whether rising edge or trailing edge）, counter resets, restart count；Compare the count value of counter（Abbreviation K）With burr width, as K ≠ M, the state that the signal after noise was kept for a upper moment is filtered out；As K=M, it is filtered after signal input bus communication module carries out the treatment of next step again, and close digital filtering function.The digital signal processing module can filter the burr of different in width, it is also possible to close digital filtering function by configuring digital filtering register for 0.
The beneficial effects of the invention are as follows：It is two kinds of bus signals of level state that the present invention can not only process bus protocol, it is also possible to which it is three kinds of bus signals of level state to process bus protocol, is completely suitable for the communication of two-wire bus；No matter it is that bus is received in the present invention for which kind of pattern, the signaling signal of back-end processing is the signal of down patterns, simplifies remaining processing sequences, reduces extra data processing overheads；Digital filter in the present invention can be filtered because bus voltage fluctuation is larger（Miss signaling）Or time code current drags down the burr that the filter of the analog filterings such as bus voltage is not fallen, and the width of burr is adjustable, and with stronger configuration flexibility, the signaling signal for obtaining is also purer.
Brief description of the drawings
Fig. 1, a kind of implementation schematic diagram of the invention；
A kind of control structure schematic diagram of the Enable Pin of two-way comparator is opened in Fig. 2, Fig. 1.
Specific embodiment
Below in conjunction with the accompanying drawings and preferred scheme is described in further detail to specific embodiment of the invention.
Embodiment：When main frame carries out signaling communication to slave by changing bus voltage, can be by reception pattern mask register（RXMODE）To set different reception patterns, down patterns and up patterns can be defined as, down patterns are high level when referring to bus normal work, are low level during signaling, and the bus burst time is time of the bus trailing edge to rising edge；It is low level when up patterns refer to bus normal work, is high level during signaling, the bus burst time is time of the bus rising edge to trailing edge, can be expressed as：RXMODE=0, down pattern；RXMODE=1, up pattern.
A kind of implementation method of bus control circuit of the invention has two comparators as shown in Figure 1, in Fig. 1（CMP1 and CMP2）, bus voltage（VLN24）Respectively with two threshold voltages（VTH1And VTH2）It is compared, the value that the threshold point of two comparators can read register by microcontroller is respectively provided with.The enable end signal of two comparators（CMP1_EN and CMP2_EN）Can be by the output selection signal of two comparator results（RXD_SEL）And RXVTH is controlled as the selector structure of gate control signal, its implementation is as shown in Figure 2.Bus protocol level state mask register（RXVTH）Bus protocol level number can be configured, RXVTH=0, bus only has two kinds of level of height in bus protocol；RXVTH=1, there is three kinds of level states on bus protocol.RXD_SEL can with two kinds of level states of controlling bus when selection CMP1_EN or CMP2_EN opening, through comparator relatively after signaling signal be respectively rxd1 and rxd2.
The reception pattern of different main frames may be different, judge the signaling signal starting edge of up reception patterns and down reception patterns in bus communication module and terminate also different along algorithm,, by rxd1/rxd2 signals reverses, rxd1/rxd2, (~ rxd1)/(~ rxd2) are respectively as selector for phase inverter in Fig. 1（MUX）Two input signals, wherein selected by RXMODE signals, RXMODE=0 (dow patterns) selection outputs rxd1/rxd2, RXMODE=1（Up patterns）Selection output (~ rxd1)/(~ rxd2), this implementation method makes the signaling signal rxd1_in/rxd2_in of subsequent treatment all be down patterns.
Rxd1_in/rxd2_in is by digital filter（D-rxfilter）Filtering, the width of the burr to be filtered is set by configuring digital filtering register（M）, counter is started counting up along beginning in the starting of rxd1_in/rxd2_in from 0, when detecting edge（Whether rising edge or trailing edge）, counter resets, restart count；Compare the count value of counter（K）With burr width（ M）, as K ≠ M, rxd1_filt/rxd2_filt kept the state at a upper moment；As K=M, rxd1_filt/rxd2_filt is equal to rxd1_in/rxd2_in, after filtering after signal rxd1_filt/rxd2_filt input bus communication module carries out the treatment of next step again.The digital filtering can filter the burr of different in width, it is also possible to which register configuration is closed into digital filtering function into 0.
Enable Pin in the present invention is to refer to allow integrated package to work or idle port.
There is two-way comparator in circuit of the invention, no matter bus signaling pattern is up patterns or down patterns, the signaling signal of subsequent treatment is set all to be down patterns by increasing a phase inverter and selector, signaling signal can filter burr by a digital filter, the width of burr can by digital filtering register configuration into different in width, while can also configuration register be 0 to close digital filtering function.
Claims (4)
1. a kind of bus marco implementation method, based on the digital signal processing module in bus circuit, reception pattern mask register, bus protocol level state mask register, two-way comparator, corresponding reception threshold voltage register and the bus communication module of two-way comparator difference, it is characterised in that it includes following steps：
（1）The bus protocol for judging host side signaling is two kinds of level or three kinds of level；
（2）If two kinds of level, then it is 1 to configure bus protocol level state selection signal by bus protocol level state mask register；If three kinds of level, then bus protocol level state selection signal 0 is configured by bus protocol level state mask register；
（3）If two kinds of level, then the Enable Pin of any comparator all the way is opened；If three kinds of level, then the Enable Pin of two-way comparator is opened；
（4）Bus voltage and the threshold voltage for receiving the setting of threshold voltage register are compared every comparator all the way the signaling signal for obtaining the comparator, and this signaling signal is sent to the numerical portion of bus communication module；
（5）Judge the reception pattern of the reception pattern mask register, the reception pattern mask register defines two kinds of reception patterns, respectively down patterns and up patterns, down patterns are high level when referring to bus normal work, are low level during signaling；It is low level when up patterns refer to bus normal work, is high level during signaling；If being provided that high level in reception pattern mask register, reception pattern is up patterns；If being provided that low level in Mode Selection register, reception pattern is down patterns；
（6）Enter row selection signal treatment to reception pattern, if up patterns, by step（4）The signaling signal of middle comparator carries out follow-up filtering process after negating by digital signal processing module；If down patterns, by step（4）The signaling signal of middle comparator directly carries out follow-up filtering process by digital signal processing module；
（7）Signaling signal after after filtering is carried out into Communication processing by bus communication module.
2. bus marco implementation method according to claim 1, it is characterised in that the control method that the two-way comparator Enable Pin is opened is as follows：The two-way comparator Enable Pin gates structure control by two-way, it is made up of two selector concatenations per gating structure all the way, it is divided into front end selector and rear end selector, the input of the front end selector is the output selection signal of high level, low level and two comparator results, and the output selection signal of two comparator results refers to one of them for the signaling signal for selecting two-way comparator；The input of the rear end selector is low level, the output of front end selector and step（1）The bus protocol level state selection signal of middle setting；The output of the rear end selector is to should be used as opening the enable end signal of comparator, and set its output to enable end signal is Low level effective.
3. bus marco implementation method according to claim 1, it is characterised in that the step（6）In digital signal processing module include digital filter, 8 digit counters and digital filter registers, the step（6）Implementation process it is as follows：The width of the burr to be filtered is set by digital filtering register, and counter is by the step（4）The starting of the signaling signal for obtaining is started counting up along beginning from 0, when detecting edge（Whether rising edge or trailing edge）, counter resets, restart count；Compare the count value and burr width of counter, when count value and burr width are not waited, be filtered out the state that the signal after noise was kept for a upper moment；When count value is equal with burr width, it is filtered after signal input bus communication module carries out the treatment of next step again, and close digital filtering function.
4. bus marco implementation method according to claim 3, it is characterised in that the digital filtering register configuration closes digital filtering function into by configuring digital filtering register for 0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511013476.XA CN106933766B (en) | 2015-12-31 | 2015-12-31 | bus control implementation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511013476.XA CN106933766B (en) | 2015-12-31 | 2015-12-31 | bus control implementation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106933766A true CN106933766A (en) | 2017-07-07 |
| CN106933766B CN106933766B (en) | 2019-12-06 |
Family
ID=59458612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201511013476.XA Active CN106933766B (en) | 2015-12-31 | 2015-12-31 | bus control implementation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106933766B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111385172A (en) * | 2018-12-27 | 2020-07-07 | 杭州萤石软件有限公司 | Control system, control method and storage medium based on bus |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1434945A (en) * | 2000-06-02 | 2003-08-06 | 汤姆森特许公司 | Bus operation with integrated circuits in unpowered state |
| US20090326829A1 (en) * | 2005-04-29 | 2009-12-31 | Liamos Charles T | Method and System for Monitoring Consumable Item Usage and Providing Replenishment Thereof |
| CN201917898U (en) * | 2011-01-20 | 2011-08-03 | 电子科技大学 | A kind of I2C bus interface circuit module |
| CN203608227U (en) * | 2013-11-07 | 2014-05-21 | 北京机械设备研究所 | Bidirectional buffering 1553B/CAN bus protocol converter |
| CN103955419A (en) * | 2014-04-28 | 2014-07-30 | 电子科技大学 | Logic analyzer with serial bus protocol on-line real-time detection analysis function |
| CN204576502U (en) * | 2015-04-13 | 2015-08-19 | 无锡新硅微电子有限公司 | Be applied to the dynamic threshold comparator circuit of M-BUS interface communication |
-
2015
- 2015-12-31 CN CN201511013476.XA patent/CN106933766B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1434945A (en) * | 2000-06-02 | 2003-08-06 | 汤姆森特许公司 | Bus operation with integrated circuits in unpowered state |
| US20090326829A1 (en) * | 2005-04-29 | 2009-12-31 | Liamos Charles T | Method and System for Monitoring Consumable Item Usage and Providing Replenishment Thereof |
| CN201917898U (en) * | 2011-01-20 | 2011-08-03 | 电子科技大学 | A kind of I2C bus interface circuit module |
| CN203608227U (en) * | 2013-11-07 | 2014-05-21 | 北京机械设备研究所 | Bidirectional buffering 1553B/CAN bus protocol converter |
| CN103955419A (en) * | 2014-04-28 | 2014-07-30 | 电子科技大学 | Logic analyzer with serial bus protocol on-line real-time detection analysis function |
| CN204576502U (en) * | 2015-04-13 | 2015-08-19 | 无锡新硅微电子有限公司 | Be applied to the dynamic threshold comparator circuit of M-BUS interface communication |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111385172A (en) * | 2018-12-27 | 2020-07-07 | 杭州萤石软件有限公司 | Control system, control method and storage medium based on bus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106933766B (en) | 2019-12-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101874765B1 (en) | Multi-wire single-ended push-pull link with data symbol transition based clocking | |
| US9374216B2 (en) | Multi-wire open-drain link with data symbol transition based clocking | |
| US9203599B2 (en) | Multi-lane N-factorial (N!) and other multi-wire communication systems | |
| CN107534548B (en) | Clock and data recovery for a pulse-based multiline | |
| US8432981B1 (en) | High frequency and idle communication signal state detection | |
| US20150234774A1 (en) | Coexistence of legacy and next generation devices over a shared multi-mode bus | |
| WO2014138640A1 (en) | Clock recovery circuit for multiple wire data signals | |
| WO2016126466A1 (en) | Receive clock calibration for a serial bus | |
| CN100561407C (en) | USB device and USB device control method | |
| CN103856384A (en) | Bit-timing symmetrization | |
| WO2016145401A1 (en) | Farewell reset and restart method for coexistence of legacy and next generation devices over a shared multi-mode bus | |
| TW201702894A (en) | Independent UART BRK detection | |
| US20160124896A1 (en) | Simultaneous edge toggling immunity circuit for multi-mode bus | |
| US8391420B1 (en) | Low frequency communication signal state detection | |
| CN102938744B (en) | A kind of implementation method of universal serial transceiver | |
| CN106933766A (en) | A kind of bus marco implementation method | |
| CN110098897B (en) | Serial communication method, device, computer equipment and storage medium | |
| WO2015126983A1 (en) | Technique to avoid metastability condition and avoid unintentional state changes of legacy i2c devices on a multi-mode bus | |
| CN109543811B (en) | Counting circuit, counting method and chip | |
| US9660795B2 (en) | Start-stop synchronous type serial data acquisition device and start-stop synchronous type serial data acquisition method | |
| US7936853B2 (en) | False frequency lock detector | |
| WO2017099848A1 (en) | Serial data multiplexing | |
| US9471523B2 (en) | Serial interface systems and methods having multiple modes of serial communication | |
| WO2016085600A1 (en) | Symbol transition clocking clock and data recovery to suppress excess clock caused by symbol glitch during stable symbol period | |
| JP2022132152A (en) | Timing detection and correction method for slave device in IO-Link communication, and slave device for IO-Link communication |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 214135 -6, Linghu Avenue, Wuxi Taihu international science and Technology Park, Wuxi, Jiangsu, China, 180 Patentee after: China Resources micro integrated circuit (Wuxi) Co.,Ltd. Address before: No.180-22, Linghu Avenue, Taihu International Science and Technology Park, Wuxi, Jiangsu, 214135 Patentee before: WUXI CHINA RESOURCES SEMICO Co.,Ltd. |
|
| CP03 | Change of name, title or address | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: A Bus Control Implementation Method Effective date of registration: 20231008 Granted publication date: 20191206 Pledgee: Bank of China Limited Wuxi Branch Pledgor: China Resources micro integrated circuit (Wuxi) Co.,Ltd. Registration number: Y2023980060027 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Granted publication date: 20191206 Pledgee: Bank of China Limited Wuxi Branch Pledgor: China Resources micro integrated circuit (Wuxi) Co.,Ltd. Registration number: Y2023980060027 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right |