CN106876448A - Titanium-doped high-quality silicon oxide film and preparation method therefor - Google Patents

Titanium-doped high-quality silicon oxide film and preparation method therefor Download PDF

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CN106876448A
CN106876448A CN201710031840.8A CN201710031840A CN106876448A CN 106876448 A CN106876448 A CN 106876448A CN 201710031840 A CN201710031840 A CN 201710031840A CN 106876448 A CN106876448 A CN 106876448A
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titanium
film
si
doped
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董鹏
宋宇
代刚
冯晓龙
李沫
张健
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中国工程物理研究院电子工程研究所
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed

Abstract

The invention provides a titanium-doped high-quality silicon oxide film and a preparation method therefor. A related device includes but is not limited to an MOS device and a bipolar transistor. Through the adding of titanium impurity to gate oxide or buried oxide, the combination between oxygen vacancy and hydrogen impurity can be weakened, and the inhibition of the release of protons follows. Finally, the forming of charges at a SiO2/Si interface state and in SiO2 is inhibited at the same time. Titanium-doped silicon oxide serves as the gate oxide or buried oxide, so the film can iron out the defects that the conventional Al, Cr, O and Si doping just can inhibit the forming of charges in the SiO2 but cannot remarkably reduce the SiO2/Si interface state, thereby remarkably improving the electrical performance of MOS and BJT and other silicon-base devices and the stability in a severe environment.

Description

一种基于钛掺杂的高质量氧化硅薄膜及其制备方法 And a high-quality silicon oxide film doped with a titanium-based preparation

技术领域 FIELD

[0001] 本发明属于元器件制备领域,具体涉及一种基于钛掺杂的高质量氧化硅薄膜及其制备方法。 [0001] The present invention belongs to the field of preparing components, particularly it relates to a high-quality silicon oxide film and a titanium doped preparation based.

背景技术 Background technique

[0002] 氧化硅(Si02)常被用作栅氧或者埋氧而广泛地应用于集成电路中。 [0002] Silicon oxide (Si02) is often used as a gate oxide or buried oxide widely used in integrated circuits. 但是,在实际使用过程中,往往会发现Si〇2中存在着电荷,并在Si〇V Si界面上形成界面态。 However, in actual use, often find Si〇2 exist in charge and interface states formed at the Si interface Si〇V. 具体地,在电场或者激光作用下,会在氧化硅中注入载流子。 Specifically, in the electric field or laser action, it will inject carriers in silicon oxide. 在正向偏压下,注入的电子从氧化层漂移到栅极;留下的空穴将在电场作用下,以较慢的迁移速度在Si〇2中迁移。 Under forward bias, electrons injected from a drift to the gate oxide layer; voids left will, at a slower rate of migration in the migration Si〇2 in the electric field. 当空穴到达Si/Si02 界面附近靠近Si〇2—侧时,被氧空位陷阱所俘获而成为正空间电荷。 When holes reach the vicinity of the Si / Si02 interface close Si〇2- side, is captured by the oxygen vacancies become positive space charge traps. 另外,一部分俘获了空穴的氧空位进一步与氧化硅中的氢原子结合,而释放出质子;质子在空间电场的作用下得到加速,轰击Si02/Si界面上的Si-H键,进而产生悬挂键,即产生Si〇2/Si界面态。 Further, a portion of the oxygen vacancy trapping holes further combined with a hydrogen atom in the silicon oxide, to release a proton; protons accelerated under the action of electric field, the bombardment of Si-H bonds on the Si02 / Si interface, and produce the suspension key, generating Si〇2 / Si interface states.

[0003] Si02/ Si界面态与Si02中的电荷都会对器件的电学性能产生不利的影响。 [0003] Si02 / Si interface states and charges in the Si02 will adversely affect the electrical performance of the device. 例如,界面态与Si02中的电荷就会引起金属-氧化物-半导体(Mis)器件阈值电压的偏移。 For example, the interface state of charge will cause Si02 metal - oxide - semiconductor (Mis) the offset value of the threshold voltage of the device. 与此同时, 界面态会作为载流子的复合中心,导致漏电流的增加,从而增加了MIS器件低频下的噪声信号。 At the same time, as the interface state will recombination centers of carriers, resulting in increase in leakage current, thereby increasing the noise signal at the low frequency MIS device. 在双极型晶体管中,埋氧中与埋氧/半导体界面上同样分别存在着电荷与界面态,导致基极漏电流的增加,从而导致增益系数的显著降低,最终使得集成电路的失效。 In the bipolar transistor, with the buried oxide on the buried oxide / semiconductor interface are the same interface states and charges exist, resulting in increase in the base current leakage, resulting in a significant reduction of the gain factor, such that the final failure of the integrated circuit. 随着器件特征线宽的进一步减小,界面态与Si〇2中电荷等缺陷对器件性能的影响将变得尤为显著。 As device features to further reduce the line width, the effect of charge and interface state of defects in the device performance Si〇2 become particularly significant.

[0004] 因此,有必要同时抑制Si02/ Si界面态与Si02中电荷的形成,以此提高硅基器件的电学性能及其恶劣环境下使用的稳定性。 [0004] Thus, while it is necessary to suppress the formation of Si02 / Si interface states and charges Si02, in order to improve the stability of the electrical properties of the silicon used in the device and the harsh environment. 为此,国内外的科学与产业界提出了通过Al、Cr、 〇、Si等离子注入工艺,在氧化硅中实现杂质掺杂。 To this end, domestic and international science and industry proposed by Al, Cr, square, Si ion implantation process and the like, implemented in silicon oxide doped with impurities. 研究发现,△1、〇、0、51等杂质离子都可以不同程度的降低氧化硅中的净电荷浓度(AU),并将其归因于杂质离子注入在氧化硅中引入的电子俘获陷阱所导致的负电荷,但是对界面态的形成则几乎没有影响。 Found, △ 1, square, and other impurity ions are 0,51 net charge concentration (AU) of different degrees of reduction of silicon oxide, and which is due to the impurity ions introduced in the injection of electrons trapped in the silicon oxide traps results in negative charge, but almost no influence on the formation of interface states. 显然,为了显著地提升硅基器件的电学性能,需要同时抑制Si〇2/Si界面态与Si02中电荷的形成。 Clearly, in order to significantly improve the electrical properties of silicon-based devices, it is necessary while suppressing formation Si〇2 / Si interface states and charges of Si02. 基于上述原因,A1、Cr、0、Si等离子注入并不能有效地满足硅基器件电学性能及其使用稳定性的需求。 For these reasons, A1, Cr, 0, Si ion implantation and the like can not effectively meet the electrical properties of the silicon device and needs stability.

[0005] 由于钛(Ti)原子与氢原子能够强有力的结合,Ti原子及其相关化合物被广泛地用作贮氢材料而用于燃料电池中。 [0005] since a strong binding and hydrogen atoms of titanium (Ti), Ti atoms, and related compounds are widely used as hydrogen storage materials used in fuel cells. 基于此,本发明创造性的提出在氧化硅中掺入Ti杂质。 Based on this, the present invention proposes incorporating the inventive Ti impurities in silicon oxide. 通过Ti杂质俘获H原子或分子,有效地抑制氧空位与氢杂质之间的结合,进而抑制其反应产物-质子的释放,从而削弱质子与Si/Si02界面处Si-H键之间的反应,由此降低Si02/Si界面态的形成。 H trapped atoms or molecules by Ti impurities, effectively inhibited the binding between the oxygen vacancies and hydrogen impurities, thereby inhibiting its reaction product - releasing a proton thereby weakening the reaction between protons and the Si / Si02 interface Si-H bonds, thereby reducing the formation of Si02 / Si interface states. 另一方面,Ti离子可以作为电子俘获陷阱,促进氧化硅中负电荷的形成,进而降低氧化硅中的电荷浓度。 On the other hand, Ti ions as electron capture trap may promote the formation of the negatively charged silicon oxide, thereby reducing the concentration of silicon oxide charge.

[0006]围绕以上所述的研宄思路,本发明提出一种基于钛掺杂的新型高质量氧化硅制备技术。 [0006] about a study based on the idea described above, the present invention provides a novel technique based on the preparation of high quality silicon oxide doped with titanium.

发明内容 SUMMARY

[0007]本发明为解决上述技术问题,提供一种基于钛掺杂的高质量氧化硅薄膜及其制备方法,基于相对于氧空位而言,钛杂质更容易与氢原子结合,由此抑制了氧空位-氢复合体的形成,该方法可以同时抑制Si02/Si界面态与Si02中电荷形成,克服以往△1、&、0、31等掺杂只能降低Si02中电荷形成的不足,进而显著提高元器件的电学性能及其恶劣使用环境下的稳定性。 [0007] The present invention is to solve the above problems, there is provided a high-quality titanium-doped silicon oxide film and a preparation method based, with respect to oxygen vacancy, the titanium impurities more easily combined with a hydrogen atom, thereby inhibiting oxygen vacancy - hydrogen complex is formed, while suppressing the method may Si02 / Si interface states and charges formed Si02 overcome conventional △ 1, amp &;, 0,31 only insufficient reduction of the doping charges formed in Si02, further significantly improved stability and electrical properties of components harsh environments.

[0008] 本发明的技术方案如下: 一种基于钛掺杂的高质量氧化桂制备方法,其特征在于: (1) 选取单晶硅片作为衬底; (2) 以纯氧作保护气氛,利用干氧或湿氧氧化工艺在硅片表面生长Si02薄膜; (3) 在步骤(2)生长的Si02薄膜表面生长钛薄膜,钛薄膜的厚度为10 - 50nm; (4) 利用氩气作为保护气氛,将生长有钛薄膜后的硅片在850-1150 °C下接受后续退火。 [0008] The aspect of the present invention is as follows: The method of preparing a high-quality oxide doped titanium based Gui, wherein: (1) selecting a monocrystalline silicon wafer as the substrate; (2) as a pure oxygen atmosphere, using dry oxygen oxidation process or wet oxidation film on the silicon wafer surface grown Si02; (3) in step (2) grown on the surface of the Si02 thin titanium film growth, the thickness of the titanium film is 10 - 50nm; (4) using argon as protective gas atmosphere , the growth of the silicon film after the titanium receiving subsequent annealing at 850-1150 ° C.

[0009] 作为优选,步骤(1)中所述的硅片导电类型是n型或者p型,电阻率为0.1-50 Q .cm〇 [0009] Advantageously, step (1) in the silicon conductivity type is n-type or p-type, the resistivity of 0.1-50 Q .cm〇

[0010] 作为优选,步骤(2)中所述的热氧化温度为900-1250 °C,Si02薄膜的厚度为3〇-300 nm。 [0010] Advantageously, step (2) in the thermal oxidation temperature of 900-1250 ° C, the thickness of the Si02 film is 3〇-300 nm.

[0011] 步骤(4)中所述的后续退火工艺,目的在于两个方面:一方面,通过在氩气中高温退火,可以有效的降低氧空位的浓度,进而提高元器件的电学性能及其恶劣使用环境下的稳定性;另一方面,高温退火使得钛杂质扩散进入到氧化硅中,实现氧化硅中的钛掺杂。 [0011] Step (4) in the subsequent annealing process, object of the two aspects: on the one hand, by high-temperature annealing in an argon gas, can effectively reduce the concentration of oxygen vacancies, thereby improving the electrical properties of components and stability in harsh environments; on the other hand, such high temperature annealing the titanium diffusion of impurities into the silicon oxide, titanium implemented doped silicon oxide. 相对于氧空位,钛杂质更容易与氢原子结合,由此抑制了氧空位-氢复合体的形成,同时伴随着抑制了质子的释放。 With respect to oxygen vacancy, titanium impurities more easily combined with a hydrogen atom, thereby suppressing the oxygen vacancy - hydrogen complex formation, accompanied by the release of protons is suppressed. 质子的释放被削弱,相应地,也削弱了质子对Si〇2/Si界面上的Si-H 键的轰击,由此抑制了Si〇2/Si界面态的形成。 Releasing a proton is weakened, accordingly, also weakens the proton bombardment of Si-H bonds on Si〇2 / Si interface, thereby suppressing the formation Si〇2 / Si interface states.

[0012] 通过上述方法,可以制备得到的氧化硅薄膜,该氧化硅薄膜中钛杂质浓度在1〇15/ cm3以上。 [0012] By the method described above, it can be prepared silicon oxide film obtained, the silicon oxide film of titanium impurity concentration 1〇15 / cm3 or more.

[0013] 本发明的有益效果为: 本发明利用这种钛掺杂的氧化硅作为栅氧或者埋氧层,可以显著的降低Si〇2/ Si界面态与Si02中电荷的形成,进而提高MOS、BJT等元器件的电学性能及其恶劣使用环境下的稳定性;这种栅氧制备方法与集成电路制备工艺相兼容,可以在大规模集成电路中得到推广使用。 [0013] Advantageous effects of the present invention are: the present invention using such a titanium-doped silicon oxide as the gate oxide, or a buried oxide layer, can significantly reduce the formation Si〇2 / Si interface states and charges Si02, thus improving MOS , stability in electrical properties and other components of the BJT and harsh environments; gate oxide method for preparing such preparation is compatible integrated circuits, can be used to promote the large-scale integrated circuits.

附图说明 BRIEF DESCRIPTION

[0014] 图1是本发明的制备流程示意图。 [0014] FIG. 1 is a schematic view of fabrication process of the present invention.

具体实施方式^ _ DETAILED DESCRIPTION ^ _

[0015] 本发明在原有的Si02薄膜生长工艺基础上进行改进,目的在于提高元器件的电学性能及其恶劣使用环境下的稳定性,原理如下:通过在Si〇2薄膜生长上生长钛薄膜,再经过后续高温退火后使得钛杂质扩散进入到氧化硅中,实现氧化硅中的钛掺杂。 [0015] The present invention may be modified in the original film growth process based on Si02, aimed at improving the stability of the electrical properties of components and harsh environments, works as follows: the film growth by growth on Si〇2 titanium film, after an additional subsequent high temperature anneal such that the titanium diffusion of impurities into the silicon oxide, titanium implemented doped silicon oxide. 相对于氧空位, 钛杂质更容易与氢原子结合,由此抑制了氧空位-氢复合体的形成,同时伴随着抑制了质子的释放。 With respect to oxygen vacancy, titanium impurities more easily combined with a hydrogen atom, thereby suppressing the oxygen vacancy - hydrogen complex formation, accompanied by the release of protons is suppressed. 质子的释放被削弱,相应地,也削弱了质子对Si〇2/Si界面上的Si-H键的轰击,进而抑制了Si〇2/Si界面态的形成。 Releasing a proton is weakened, accordingly, also weakens the proton bombardment of Si-H bonds on Si〇2 / Si interface, thereby inhibiting the formation Si〇2 / Si interface states.

[0016] 现举例说明具体的实施步骤,对本发明不构成任何限制。 [0016] To illustrate specific embodiments step of the present invention does not constitute any limitation.

[0017] 实施例1 (1) 选取晶向为<1〇〇>、电阻率为1〇Q .cm的p型硅; (2) 以纯氧作保护气氛,利用湿氧氧化工艺在步骤(1)所述的硅片表面上生长8:102薄膜,所采用的热氧化温度为900 °C,得到的氧化硅厚度为30 nm; (3) 在步骤(2)所述的氧化硅表面生长10 nm厚的钛薄膜; (4) 利用氩气作为保护气氛,将步骤(3)所述的硅片在850 °C下接受后续退火。 [0017] Example 1 (1) to select the crystal orientation <1〇〇> 1〇Q .cm resistivity of p-type silicon; (2) as a pure oxygen atmosphere, using a wet oxidation process in an oxygen step (1 ) grown on the surface of the silicon wafer 8: 102 thin film, thermal oxidation temperature employed was 900 ° C, the silicon oxide obtained had a thickness 30 nm; (3) in step (2) of the silicon oxide grown on the surface 10 nm thick titanium film; (4) using argon as protective gas atmosphere, in step (3) subsequent annealing of the silicon wafer to accept at 850 ° C.

[0018] 步骤(4)中所述的后续退火工艺,目的在于两个方面:一方面,通过氩气下的高温退火,降低氧空位的浓度,提高硅基器件的电学性能及其恶劣环境下使用的稳定性;另一方面,高温退火使得钛杂质扩散进入到氧化硅中,实现氧化硅中的钛掺杂,进而削弱氧空位与氢的结合,最终同时抑制Si02/ Si界面态与Si02中电荷的形成,提高器件的电学性能及其恶劣使用环境下的稳定性。 [0018] Step (4) in the subsequent annealing process, object of the two aspects: on the one hand, by high temperature annealing under argon, to reduce the concentration of oxygen vacancies, silicon-based devices to improve electrical performance in harsh environments and stability used; on the other hand, such high temperature annealing the titanium diffusion of impurities into the silicon oxide, titanium implemented doped silicon oxide, and thus impair the binding of oxygen vacancies and hydrogen, while suppressing the final Si02 / Si interface states and Si02 in charge formation, improved electrical performance stability in its harsh environment.

[0019] 实施例2 (1) 选取晶向为<1〇〇>、电阻率为50 n .cm的n型硅; (2) 以纯氧作保护气氛,利用湿氧氧化工艺在步骤(1)所述的硅片表面上生长Si〇2薄膜,所采用的热氧化温度为1250 °C,得到的氧化硅厚度为300 nm; (3) 在步骤(2)所述的氧化硅表面生长50 nm厚的钛薄膜; (4) 利用氩气作为保护气氛,将步骤(3)所述的硅片在1150 °C下接受后续退火。 [0019] Example 2 (1) to select the crystal orientation <1〇〇> 50 n .cm resistivity of n-type silicon; (2) as a pure oxygen atmosphere, using a wet oxidation process in an oxygen step (1) growing the silicon film surface Si〇2, thermal oxidation temperature employed is 1250 ° C, silicon oxide obtained had a thickness 300 nm; surface of the silica (2) to (3) in the step of growing 50 nm thick titanium film; (4) using argon as protective gas atmosphere, in step (3) subsequent annealing of the silicon wafer receiving at 1150 ° C.

[0020] 实施例3 (1) 选取晶向为〈1〇〇>、电阻率为0.1 D .cm的p型硅; (2) 以纯氧作保护气氛,利用湿氧氧化工艺在步骤(1)所述的硅片表面上生长Si〇2薄膜,所采用的热氧化温度为125〇°C,得到的氧化硅厚度为300 nm; (3) 在步骤(2)所述的氧化硅表面生长50 nm厚的钛薄膜; &amp; (4) 利用氩气作为保护气氛,将步骤(3)所述的硅片在1150 °C下接受后续退火。 [0020] Example 3 (1) to select the crystal orientation <1〇〇> 0.1 D .cm resistivity of p-type silicon; (2) as a pure oxygen atmosphere, using a wet oxidation process in an oxygen step (1) grown on the silicon wafer surface Si〇2 thin film, thermal oxidation temperature employed is 125〇 ° C, the silicon oxide obtained had a thickness 300 nm; (3) in step (2) of the silicon oxide grown on the surface 50 nm thick titanium film; & amp; (4) using argon as protective gas atmosphere, in step (3) subsequent annealing of the silicon wafer receiving at 1150 ° C.

Claims (6)

1.一种基于钛掺杂的高质量氧化硅薄膜,其特征在于:所述氧化硅薄膜中钛杂质浓度在l〇15/cm3以上。 A titanium-based high-doped silicon oxide film, wherein: the silicon oxide film of titanium impurity concentration l〇15 / cm3 or more.
2. —种基于钛掺杂的高质量氧化硅薄膜的制备方法,其特征在于包括以下步骤: (1) 选取单晶硅片作为衬底; (2) 以纯氧作保护气氛,利用千氧或湿氧氧化工艺在硅片表面生长Si02薄膜; (3) 在步骤(2)生长的Si02薄膜表面生长钛薄膜,钛薄膜的厚度为1〇- 5〇nm; (4) 利用氩气作为保护气氛,将生长有钛薄膜后的硅片在85〇-1150 °C下接受后续退火。 2. - preparation methods of titanium-doped silicon oxide film based on high-quality, characterized by comprising the steps of: (1) selecting a monocrystalline silicon wafer as the substrate; (2) as a pure oxygen atmosphere, using an oxygen or one thousand wet oxygen oxidation process on the silicon wafer surface grown Si02 thin film; (3) in step (2) grown on the surface of the Si02 thin titanium film growth, the thickness of the titanium film is 1〇- 5〇nm; (4) using argon as protective gas atmosphere , the wafer after the growth of the titanium film in the subsequent annealing receiving 85〇-1150 ° C.
3. 根据权利要求2所述的基于钛掺杂的高质量氧化娃薄膜的制备方法,其特征在于:步骤(1)中所述硅片导电类型是n型或者p型,电阻率为mo Q .cm。 The method for preparing the titanium-based oxide doped baby quality film according to claim 2, wherein: in step (1) of said conductivity type is n-type silicon or p-type, resistivity of the mo Q .cm.
4. 根据权利要求2所述的基于钛掺杂的高质量氧化桂薄膜的制备方法,其特征在于:步骤(2)中氧化工艺为热氧化工艺,热氧化温度为900-1250 °C,Si〇2薄膜厚度为30 - 300 nm〇 The preparation of high quality based on titanium oxide film doped Gui according to claim 2, wherein: the step (2) in the oxidation process as a thermal oxidation process, the thermal oxidation temperature of 900-1250 ° C, Si 〇2 film thickness 30--300 nm〇
5. 根据权利要求2所述的基于钛掺杂的高质量氧化娃薄膜的制备方法,其特征在于:所述Si02薄膜中钛杂质浓度在1015/cm3以上。 Titanium impurity concentration of the Si02 film in the 1015 / cm3 or more: 5. The method of claim 2 Preparation of titanium-doped oxide high quality film based on baby, characterized in that the claim.
6. 根据权利要求2所述的基于钛掺杂的高质量氧化娃薄膜的制备方法,其特征在于:该方法用于同时抑制Si〇2/ Si中界面态与Si〇2中电荷的形成,应用于不同环境下工作的娃基器件,具体器件类型包括M0S、B JT。 The method for preparing the titanium-based oxide doped baby quality film according to claim 2, characterized in that: the method for simultaneously inhibiting formation Si〇2 / Si interface in the state of charge in Si〇2, baby based devices used in different operating environments, specific device types include M0S, B JT.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184072B1 (en) * 2000-05-17 2001-02-06 Motorola, Inc. Process for forming a high-K gate dielectric
US20060118890A1 (en) * 2004-12-06 2006-06-08 Hong-Jyh Li Semiconductor device and method of manufacture thereof
US20060223337A1 (en) * 2005-03-29 2006-10-05 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
CN102446700A (en) * 2010-09-30 2012-05-09 中国科学院微电子研究所 Method for improving silicon substrate and obtained silicon substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184072B1 (en) * 2000-05-17 2001-02-06 Motorola, Inc. Process for forming a high-K gate dielectric
US20060118890A1 (en) * 2004-12-06 2006-06-08 Hong-Jyh Li Semiconductor device and method of manufacture thereof
US20060223337A1 (en) * 2005-03-29 2006-10-05 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
CN102446700A (en) * 2010-09-30 2012-05-09 中国科学院微电子研究所 Method for improving silicon substrate and obtained silicon substrate

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