CN106841964A - High-precision programmable voltage soft circuit - Google Patents
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Abstract
本发明提出一种高精度可编程电压软启动电路，现场可编程门阵列FPGA信号连接数字电位器,参考产生电路中的参考电压VREF经数字电位器连接第一运算放大器的同相输入端，第一运算放大器的同相输入端经分压电阻接地，第一运算放大器的反相输入端连接第一运算放大器的输出端，第一运算放大器的输出端连接第二运算放大器的同相输入端，输出电压依次经第一电阻、第二电阻接地，第一电阻和第二电阻之间连接第二运算放大器的反相输入端，第二运算放大器的反相输入端经校正器电路连接第二运算放大器的输出端，第二运算放大器的输出端信号连接脉宽调制器。本发明的有益效果为：可以实现电压软启动时间可编程设计以及输出电压软启动时间高精度设计。
The present invention proposes a high-precision programmable voltage soft-start circuit, the field programmable gate array FPGA signal is connected to a digital potentiometer, the reference voltage VREF in the reference generation circuit is connected to the non-inverting input terminal of the first operational amplifier through the digital potentiometer, and the first The non-inverting input terminal of the operational amplifier is grounded through a voltage dividing resistor, the inverting input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier, the output terminal of the first operational amplifier is connected to the non-inverting input terminal of the second operational amplifier, and the output voltages are sequentially The first resistor and the second resistor are grounded, the inverting input terminal of the second operational amplifier is connected between the first resistor and the second resistor, and the inverting input terminal of the second operational amplifier is connected to the output of the second operational amplifier through a corrector circuit terminal, and the output signal of the second operational amplifier is connected to the pulse width modulator. The beneficial effects of the invention are: the programmable design of the voltage soft-start time and the high-precision design of the output voltage soft-start time can be realized.
Description
技术领域technical field
本发明涉及半导体器件分析技术领域，特别是涉及一种高精度可编程电压软启动电路。The invention relates to the technical field of semiconductor device analysis, in particular to a high-precision programmable voltage soft-start circuit.
背景技术Background technique
随着半导体器件制造技术、电力电子技术的发展和复杂自动测试的需求，常规的电压-电流(IV)测量和电容-电压(CV)测量已经无法满足半导体器件测试需求，需要高精度大电流脉冲源来测试其动态性能特性。With the development of semiconductor device manufacturing technology, power electronics technology and the demand for complex automatic testing, conventional voltage-current (IV) measurement and capacitance-voltage (CV) measurement can no longer meet the needs of semiconductor device testing, and high-precision high-current pulses are required source to test its dynamic performance characteristics.
常用的直流输入大电流脉冲源框图，如图1所示：由DC-DC变换、脉冲产生、控制电路、驱动隔离电路、采样电路、辅助电源和人机接口组成。框图中有三个关键的电路：DC-DC变换、脉冲产生和控制电路，特别是DC-DC变换电路提供了整个输出的激励功率，在设计时通常采用大容量储能电容，来提高大电流脉冲的输出能力。但是大容量储能电容的使用，给DC-DC变换器的启动带来很大的困难。在DC-DC变换电路设计时，通常是利用PWM芯片的软启动引脚连接电容来实现软启动。常用的PWM芯片软启动内部部分电路，如图2所示：在引脚8连接有电容来实现输出电压软启动，软启动时间由外接电容、恒流源充电电流和电压参考(VREF)决定，由于连接电容误差、电压参考精度问题和PWM芯片内部恒流源的精度问题，造成输出电压软启动时间的高精度设计困难，以及无法实现输出电压软启动时间的可编程设计。The block diagram of a commonly used DC input high-current pulse source is shown in Figure 1: it consists of DC-DC conversion, pulse generation, control circuit, drive isolation circuit, sampling circuit, auxiliary power supply and man-machine interface. There are three key circuits in the block diagram: DC-DC conversion, pulse generation and control circuit, especially the DC-DC conversion circuit provides the excitation power of the entire output, and a large-capacity energy storage capacitor is usually used in the design to improve the high-current pulse. output capacity. However, the use of large-capacity energy storage capacitors brings great difficulties to the start-up of the DC-DC converter. In the design of DC-DC conversion circuit, the soft start pin of the PWM chip is usually used to connect the capacitor to realize the soft start. Commonly used PWM chip soft start internal part of the circuit, as shown in Figure 2: a capacitor is connected to pin 8 to achieve soft start of the output voltage, the soft start time is determined by the external capacitor, constant current source charging current and voltage reference (VREF). Due to the connection capacitance error, the accuracy of the voltage reference and the accuracy of the internal constant current source of the PWM chip, it is difficult to design the high-precision soft-start time of the output voltage, and it is impossible to realize the programmable design of the soft-start time of the output voltage.
发明内容Contents of the invention
本发明的目的在于提供一种高精度可编程电压软启动电路，解决电压软启动时间不能进行编程设计和输出电压软启动时间高精度设计困难的问题。The purpose of the present invention is to provide a high-precision programmable voltage soft-start circuit to solve the problems that the voltage soft-start time cannot be programmed and the output voltage soft-start time is difficult to design with high precision.
本发明提供一种高精度可编程电压软启动电路，包括现场可编程门阵列FPGA、可变电阻产生电路、参考产生电路、误差放大电路和脉宽调制电路，可变电阻产生电路包括数字电位器及可变电阻产生电路外围电路,现场可编程门阵列FPGA信号连接数字电位器,参考产生电路包括第一运算放大器，参考产生电路中的参考电压VREF经数字电位器连接第一运算放大器的同相输入端，第一运算放大器的同相输入端经分压电阻接地，第一运算放大器的反相输入端连接第一运算放大器的输出端，误差放大电路包括第二运算放大器，第一运算放大器的输出端连接第二运算放大器的同相输入端，输出电压依次经第一电阻、第二电阻接地，第一电阻和第二电阻之间连接第二运算放大器的反相输入端，第二运算放大器的反相输入端经校正器电路连接第二运算放大器的输出端，脉宽调制电路中包括脉宽调制器及脉宽调制外围电路，第二运算放大器的输出端信号连接脉宽调制器。The invention provides a high-precision programmable voltage soft-start circuit, including a field programmable gate array FPGA, a variable resistance generating circuit, a reference generating circuit, an error amplification circuit and a pulse width modulation circuit, and the variable resistance generating circuit includes a digital potentiometer And the peripheral circuit of the variable resistance generation circuit, the field programmable gate array FPGA signal is connected to the digital potentiometer, the reference generation circuit includes the first operational amplifier, and the reference voltage VREF in the reference generation circuit is connected to the non-inverting input of the first operational amplifier through the digital potentiometer terminal, the noninverting input terminal of the first operational amplifier is grounded through a voltage dividing resistor, the inverting input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier, the error amplifier circuit includes a second operational amplifier, and the output terminal of the first operational amplifier Connect the non-inverting input terminal of the second operational amplifier, the output voltage is grounded through the first resistor and the second resistor in turn, the inverting input terminal of the second operational amplifier is connected between the first resistor and the second resistor, and the inverting input terminal of the second operational amplifier The input terminal is connected to the output terminal of the second operational amplifier through the corrector circuit. The pulse width modulation circuit includes a pulse width modulator and a pulse width modulation peripheral circuit, and the output signal of the second operational amplifier is connected to the pulse width modulator.
进一步的，数字电位器的CLK端、SDI端、端和端分别连接现场可编程门阵列FPGA。Further, the CLK end, SDI end, End and The terminals are respectively connected to the field programmable gate array FPGA.
进一步的，可变电阻产生电路外围电路中，数字电位器的CLK端、SDI端、端和端分别经第三电阻连接电源。Further, in the peripheral circuit of the variable resistance generating circuit, the CLK terminal, the SDI terminal, and the digital potentiometer End and The terminals are respectively connected to the power supply through the third resistor.
进一步的，可变电阻产生电路外围电路中，数字电位器的电源端连接电源，电源经第一电容接地。Further, in the peripheral circuit of the variable resistance generating circuit, the power supply terminal of the digital potentiometer is connected to the power supply, and the power supply is grounded through the first capacitor.
进一步的，分压电阻为精度是0.1％的精密电阻。Further, the voltage dividing resistors are precision resistors with an accuracy of 0.1%.
进一步的，第一运算放大器的电源引脚连接电源，电源经第二电容接地。Further, the power supply pin of the first operational amplifier is connected to the power supply, and the power supply is grounded through the second capacitor.
进一步的，第二运算放大器的同相输入端经第三电容接地。Further, the non-inverting input terminal of the second operational amplifier is grounded through the third capacitor.
进一步的，校正器电路包括第四电容、第五电容和第四电阻，第二运算放大器的反相输入端一路经第四电容、第四电阻连接第二运算放大器的输出端，第二运算放大器的反相输入端另一路经第五电容连接第二运算放大器的输出端。Further, the corrector circuit includes a fourth capacitor, a fifth capacitor and a fourth resistor, the inverting input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier through the fourth capacitor and the fourth resistor, and the second operational amplifier The other path of the inverting input end of the second operational amplifier is connected to the output end of the second operational amplifier through the fifth capacitor.
与现有技术相比，本发明的高精度可编程电压软启动电路具有以下特点和优点：Compared with the prior art, the high-precision programmable voltage soft-start circuit of the present invention has the following characteristics and advantages:
本发明的高精度可编程电压软启动电路，可以实现电压软启动时间可编程设计以及输出电压软启动时间高精度设计。The high-precision programmable voltage soft-start circuit of the present invention can realize the programmable design of the voltage soft-start time and the high-precision design of the output voltage soft-start time.
结合附图阅读本发明的具体实施方式后，本发明的特点和优点将变得更加清楚。The features and advantages of the present invention will become clearer after reading the detailed description of the present invention in conjunction with the accompanying drawings.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are For some embodiments of the present invention, those skilled in the art can also obtain other drawings based on these drawings without creative work.
图1为常用的直流输入大电流脉冲源框图；Figure 1 is a block diagram of a commonly used DC input high current pulse source;
图2为常用的PWM芯片软启动内部部分电路；Figure 2 is the internal part of the soft start circuit of the commonly used PWM chip;
图3为本发明实施例中高精度可编程电压软启动电路。FIG. 3 is a high-precision programmable voltage soft-start circuit in an embodiment of the present invention.
具体实施方式detailed description
如图3所示，本实施例提供一种高精度可编程电压软启动电路，包括现场可编程门阵列FPGA、可变电阻产生电路、参考产生电路、误差放大电路和脉宽调制电路。As shown in FIG. 3 , this embodiment provides a high-precision programmable voltage soft-start circuit, including a field programmable gate array FPGA, a variable resistance generating circuit, a reference generating circuit, an error amplifier circuit and a pulse width modulation circuit.
可变电阻产生电路包括数字电位器D1及可变电阻产生电路外围电路,本实施例中的数字电位器D1采用ANALOG DEVICES公司的型号为AD5260BRUZ20的256位数字电位器D1，其引脚6、引脚7、引脚8和引脚9分别对应CLK端、SDI端、端和端，数字电位器D1的CLK端、SDI端、端和端分别经电阻R7、R6、R5、R4连接电源+5V，数字电位器D1的电源端连接电源，电源经电容C7接地，CLK端、SDI端、端和端分别连接现场可编程门阵列FPGA。引脚6、引脚7、引脚8和引脚9的控制信号由现场可编程门阵列FPGA产生，从而精确控制可变电阻产生电路的输出电阻值以及编程时间。The variable resistance generation circuit includes a digital potentiometer D1 and the peripheral circuit of the variable resistance generation circuit. The digital potentiometer D1 in this embodiment adopts the 256-bit digital potentiometer D1 of the model AD5260BRUZ20 of ANALOG DEVICES company, and its pin 6, lead Pin 7, pin 8 and pin 9 respectively correspond to CLK terminal, SDI terminal, End and Terminal, CLK terminal, SDI terminal of digital potentiometer D1, End and Terminals are respectively connected to the power supply +5V through resistors R7, R6, R5, R4, the power supply terminal of digital potentiometer D1 is connected to the power supply, the power supply is grounded through capacitor C7, CLK terminal, SDI terminal, End and The terminals are respectively connected to the field programmable gate array FPGA. The control signals of pin 6, pin 7, pin 8 and pin 9 are generated by field programmable gate array FPGA, so as to precisely control the output resistance value and programming time of the variable resistance generating circuit.
D2采用ANALOG DEVICES公司的低功耗、低噪声和低失真双运算放大器,包括第一运算放大器D2：1和第二运算放大器D2：2。D2 adopts ANALOG DEVICES company's low power consumption, low noise and low distortion dual operational amplifiers, including the first operational amplifier D2:1 and the second operational amplifier D2:2.
参考产生电路包括第一运算放大器D2：1及其外围电路，参考产生电路中的参考电压VREF采用LINEAR TECHNOLOGY公司的LT1009CZ产生2.5V参考电压信号，其参考电压最大初始精度为0.2％。参考电压VREF连接数字电位器D1的引脚2，参考电压VREF经以数字电位器D1为主要构成部件的可变电阻产生电路继续经引脚3连接第一运算放大器D2：1的同相输入端。第一运算放大器D2：1的同相输入端经分压电阻R9接地，分压电阻R9精度为0.1％的精密电阻。第一运算放大器D2：1的反相输入端连接第一运算放大器D2：1的输出端。参考电压VREF经可变电阻产生电路、分压电阻R9分压后，通过第一运算放大器D2：1产生参考信号REFVSET。The reference generation circuit includes the first operational amplifier D2:1 and its peripheral circuits. The reference voltage VREF in the reference generation circuit adopts LT1009CZ of LINEAR TECHNOLOGY Company to generate a 2.5V reference voltage signal, and the maximum initial accuracy of the reference voltage is 0.2%. The reference voltage VREF is connected to the pin 2 of the digital potentiometer D1, and the reference voltage VREF is connected to the non-inverting input terminal of the first operational amplifier D2:1 through the pin 3 through the variable resistance generating circuit with the digital potentiometer D1 as the main component. The non-inverting input terminal of the first operational amplifier D2:1 is grounded through the voltage dividing resistor R9, and the voltage dividing resistor R9 is a precision resistor with a precision of 0.1%. The inverting input terminal of the first operational amplifier D2:1 is connected to the output terminal of the first operational amplifier D2:1. After the reference voltage VREF is divided by the variable resistor generating circuit and the voltage dividing resistor R9, the reference signal REFVSET is generated by the first operational amplifier D2:1.
误差放大电路包括第二运算放大器D2：2及其外围电路，第一运算放大器D2：1的输出端连接第二运算放大器D2：2的同相输入端，第一运算放大器D2：1的电源引脚连接电源+5V，电源+5V经电容C8接地，第二运算放大器D2：2的同相输入端经电容C9接地。输出电压VO依次经电阻R11、电阻R12接地分压，电阻R11和电阻R12之间经电阻R13连接第二运算放大器D2：2的反相输入端，第二运算放大器D2：2的反相输入端经校正器电路连接第二运算放大器D2：2的输出端。本实施例中的校正器电路包括电容C10、电容C11和电阻R14，采用PI调节。第二运算放大器D2：2的反相输入端一路经电容C10、电阻R14连接第二运算放大器D2：2的输出端，第二运算放大器D2：2的反相输入端另一路经电容C11连接第二运算放大器D2：2的输出端。The error amplification circuit includes the second operational amplifier D2:2 and its peripheral circuits, the output terminal of the first operational amplifier D2:1 is connected to the non-inverting input terminal of the second operational amplifier D2:2, and the power supply pin of the first operational amplifier D2:1 Connect the power supply +5V, the power supply +5V is grounded through the capacitor C8, and the non-inverting input terminal of the second operational amplifier D2:2 is grounded through the capacitor C9. The output voltage VO is grounded and divided by the resistor R11 and the resistor R12 in turn, and the resistor R11 and the resistor R12 are connected to the inverting input terminal of the second operational amplifier D2: 2 through the resistor R13, and the inverting input terminal of the second operational amplifier D2: 2 The output of the second operational amplifier D2:2 is connected via a corrector circuit. The corrector circuit in this embodiment includes a capacitor C10, a capacitor C11 and a resistor R14, and adopts PI adjustment. The inverting input terminal of the second operational amplifier D2: 2 is connected to the output terminal of the second operational amplifier D2: 2 through the capacitor C10 and the resistor R14, and the other channel of the inverting input terminal of the second operational amplifier D2: 2 is connected to the second operational amplifier through the capacitor C11. The output terminal of the second operational amplifier D2:2.
输出电压V0经过电阻R11和电阻R12分压后和可变的参考信号REFVSET进行误差放大，产生误差控制信号COMP去控制脉宽调制器N1的COMP引脚。脉宽调制电路中包括脉宽调制器N1及脉宽调制外围电路，第二运算放大器D2：2的输出端信号连接脉宽调制器N1。脉宽调制器N1采用TEXAS INSTRUMENTS公司的型号为LM5035MH的脉宽调制器N1。脉宽调制器N1集成了半桥电路驱动以及同步整流驱动，其主要作用是将误差放大电路产生的误差控制信号COMP转化成为驱动信号通过HS端(引脚12)、HO端(引脚13)、LO端(引脚14)去驱动控制开关管，从而完成输出电压V0的闭环控制。After the output voltage V0 is divided by the resistor R11 and the resistor R12, the error is amplified with the variable reference signal REFVSET, and an error control signal COMP is generated to control the COMP pin of the pulse width modulator N1. The pulse width modulation circuit includes a pulse width modulator N1 and a pulse width modulation peripheral circuit, and the output terminal signal of the second operational amplifier D2:2 is connected to the pulse width modulator N1. The pulse width modulator N1 adopts the pulse width modulator N1 of model LM5035MH of TEXAS INSTRUMENTS company. The pulse width modulator N1 integrates half-bridge circuit drive and synchronous rectification drive. Its main function is to convert the error control signal COMP generated by the error amplifier circuit into a drive signal through the HS terminal (pin 12) and the HO terminal (pin 13). , LO terminal (pin 14) to drive and control the switching tube, thereby completing the closed-loop control of the output voltage V0.
综上，经现场可编程门阵列FPGA编程，通过上述的可变电阻产生电路、参考产生电路、误差放大电路和脉宽调制电路，实现电压软启动时间可编程设计以及输出电压V0软启动时间高精度设计。In summary, through the FPGA programming of the field programmable gate array, through the above-mentioned variable resistance generation circuit, reference generation circuit, error amplifier circuit and pulse width modulation circuit, the programmable design of the voltage soft-start time and the high soft-start time of the output voltage V0 are realized. Precision designed.
当然，上述说明并非是对本发明的限制，本发明也并不仅限于上述举例，本技术领域的技术人员在本发明的实质范围内所做出的变化、改型、添加或替换，也应属于本发明的保护范围。Of course, the above descriptions are not intended to limit the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or replacements made by those skilled in the art within the scope of the present invention shall also belong to the present invention. protection scope of the invention.
Claims (8)
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| CN111954329A (en) * | 2020-07-08 | 2020-11-17 | 中国电子科技集团公司第四十一研究所 | An FPGA-based continuous power closed-loop control device and method |
| CN115981402A (en) * | 2022-12-02 | 2023-04-18 | 中国人民解放军96962部队 | Programmable voltage drive circuit |
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