CN106816558A - Top emission organic electroluminescence display panel, manufacturing method thereof and display device - Google Patents

Top emission organic electroluminescence display panel, manufacturing method thereof and display device Download PDF

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CN106816558A
CN106816558A CN 201710243869 CN201710243869A CN106816558A CN 106816558 A CN106816558 A CN 106816558A CN 201710243869 CN201710243869 CN 201710243869 CN 201710243869 A CN201710243869 A CN 201710243869A CN 106816558 A CN106816558 A CN 106816558A
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planarization layer
layer
manufacturing method
plurality
mask
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CN 201710243869
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王辉锋
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京东方科技集团股份有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/32Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes [OLED]
    • H01L27/3241Matrix-type displays
    • H01L27/3244Active matrix displays
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/32Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes [OLED]
    • H01L27/3241Matrix-type displays
    • H01L27/3244Active matrix displays
    • H01L27/3258Insulating layers formed between TFT elements and OLED elements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L51/00Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
    • H01L51/50Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for light emission, e.g. organic light emitting diodes [OLED] or polymer light emitting devices [PLED];
    • H01L51/56Processes or apparatus specially adapted for the manufacture or treatment of such devices or of parts thereof
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2251/00Indexing scheme relating to organic semiconductor devices covered by group H01L51/00
    • H01L2251/50Organic light emitting devices
    • H01L2251/53Structure
    • H01L2251/5307Structure specially adapted for controlling the direction of light emission
    • H01L2251/5315Top emission

Abstract

The invention discloses a top emission organic electroluminescence display panel, a manufacturing method of the top emission organic electroluminescence display panel and a display device. The manufacturing method comprise the following steps: sequentially forming a plurality of film layers on a substrate to form a thin film transistor with a plurality of bulge structures on the surface; forming a flat layer on the thin film transistor; and using a mask plate to conduct the photolithography technique on the flat layer so as to flatten the flat layer, wherein the mask plate is provided with a pattern matched with the bulge structures. According to the manufacturing method provided by the embodiment of the invention, the mask plate with the pattern matched with the bulge structures on the surface of the thin film transistor is adopted, the flat layer is subjected to the photolithography technique to flatten the flat layer, then the flat performance of the flat layer is improved, the thickness of an OLED(Organic Light Emitting Diode)thin film manufactured on the flat layer is much evener, therefore, the uniformity of luminance within the pixel is improved, and the granular sensation of an OLED device is relieved.

Description

顶发射有机电致发光显示面板、其制作方法及显示装置 Top-emitting organic electroluminescence display panel and a display device manufacturing method

技术领域 FIELD

[0001]本发明涉及显示技术领域,尤指一种顶发射有机电致发光显示面板、其制作方法及显示装置。 [0001] The present invention relates to the field of display technology, particularly to a top-emitting organic electroluminescence display panel and a display device manufacturing method.

背景技术 Background technique

[0002] 在显不领域,有机电致发光器件(Organic Light-Emitting Diode,OLED)相对于液晶显示器(Liquid Crystal Display,LCD),具有自发光、反应快、视角广、亮度高、色彩艳、轻薄等优点,被认为是下一代显示技术。 [0002] In substantially no art, an organic electroluminescent device (Organic Light-Emitting Diode, OLED) with respect to a liquid crystal display (Liquid Crystal Display, LCD), having a self-emitting, fast response, wide viewing angle, high brightness, brilliant color, light, etc., is considered to be next generation display technology. 根据耦合出光方式的不同,0LED器件可以分为顶发射0LED器件和底发射0LED器件。 Depending on the coupling mode of the light, it can be divided into a top-emitting device 0LED 0LED 0LED emitting device and a bottom device. 相对于底发射0LED,顶发射0LED与TFT晶体管相结合用于主动矩阵显示时不会影响器件的开口率,因此这种顶发射结构的0LED更适合应用于主动矩阵显示。 0LED respect to the bottom emission, top emission 0LED used in combination with TFT transistors does not affect the aperture ratio of an active matrix display device, and therefore more suitable for this 0LED a top emission structure is applied to an active matrix display. 就目前的研究情况而言,顶发射0LED器件在主动显示领域的应用还受着诸多因素的制约,比如耦合出光率、色纯度、视角特性。 On the current study, the top emission device in the active display 0LED applications also is being affected by many factors, such as the optical coupling ratio, color purity, viewing angle characteristics.

[0003] 在顶发射0LED器件中,为了在薄膜晶体管(Thin-film transistor,TFT)之上制作0LED器件功能层,需要在TFT之上制作一层平坦层,然而,在平坦层平坦化性能不佳的情况下,平坦层的表面还是会存在凹凸不平的现象,因而导致像素区域内出现凹凸不平的现象。 [0003] In a top-emitting device 0LED in order to make the device function layer 0LED a thin film transistor (Thin-film transistor, TFT) above, one needs to create a planar layer over the TFT, however, the planarization layer planarizing performance is not under good conditions, the surface of the flat layer will still exist a phenomenon uneven, resulting in uneven phenomenon occurring within the pixel region.

[0004] 0LED器件的成膜方式主要有蒸镀制程和溶液制程。 [0004] The film formation device 0LED embodiment are mainly evaporation process and a solution process. 蒸镀制程在小尺寸应用较为成熟,蒸镀EL薄膜膜层平坦性较好。 Evaporation process applications more mature small size, thin film deposition EL good flatness. 溶液制程的成膜方式主要有喷墨打印、喷嘴涂覆、旋涂、丝网印刷等,其中喷墨打印技术由于其材料利用率较高、可以实现大尺寸化,被认为是大尺寸0LED器件实现量产的重要方式。 Solution deposition process embodiment mainly ink jet printing, nozzle coating, spin coating, screen printing, inkjet printing technology wherein the material because of its high efficiency, large size can be achieved, is considered to be a large-sized device 0LED an important way to mass production. 喷墨打印的0LED器件,0LED薄膜在像素内的厚度均匀性非常重要,它对0LED器件的寿命和效率有重要影响。 0LED inkjet printing device, 0LED film thickness uniformity in a pixel is very important, has an important impact on the life and efficiency of the device 0LED. 由于溶液制程中液滴自由流淌性特点,开口部像素内平坦性对墨滴液滴的分布影响较大,若平坦层上存在段差,进一步影响0LED膜层的厚度均匀性,从器件点亮来看造成器件像素内发光均匀性不均,颗粒感明显。 Since the process solution of the free flow characteristics of the droplets, the flatness of the pixel opening portion on spatial distribution of droplets of ink droplets is large step difference on the planar layer, if present, further affect the thickness uniformity of the film layer 0LED, from the lighting device to See causing the light emitting device pixel uniformity unevenness, graininess apparent.

发明内容 SUMMARY

[0005] 本发明实施例提供了一种顶发射有机电致发光显示面板、其制作方法及显示装置,用以解决现有技术中存在的由于平坦层平坦化性能不佳导致的像素内发光不均匀的问题。 [0005] The present invention provides a top-emitting organic electroluminescence display panel and a method of manufacturing a display device, the pixel is not to solve since the light emitting planar layer due to poor planarization performance prior art present uniform issue.

[0006] 本发明实施例提供了一种顶发射有机电致发光显示面板的制作方法,包括: [0006] The present invention provides a top-emitting organic electroluminescence display panel manufacturing method, comprising:

[0007] 在衬底基板上依次形成多个膜层以构成表面具有多个凸起结构的薄膜晶体管; [0007] The plurality of layers are sequentially formed on a base substrate to form a surface having a plurality of convex structures of a thin film transistor;

[0008] 在所述薄膜晶体管上形成平坦层; [0008] The planarization layer is formed on the thin film transistor;

[0009] 采用具有与多个所述凸起结构相匹配图形的掩模板,对所述平坦层进行光刻工艺,以平坦化所述平坦层。 [0009] The mask having the plurality of protrusions to match the pattern of structures, the planarization layer lithography process to planarize the planarization layer.

[0010] 在一种可能的实现方式中,在本发明实施例提供的上述制作方法中,在所述薄膜晶体管上形成平坦层之后,还包括: After [0010] In one possible implementation, in the manufacturing method according to an embodiment of the present invention, a planarization layer on the thin film transistor, further comprising:

[0011] 对所述平坦层进行光刻工艺,以在非显示区域形成多个过孔。 [0011] The photolithography process on the planarization layer to form a plurality of through holes in a non-display area.

[0012] 在一种可能的实现方式中,在本发明实施例提供的上述制作方法中,平坦化所述平坦层的光刻工艺,与形成多个所述过孔的光刻工艺为同一次光刻工艺;其中, [0012] In one possible implementation, in the manufacturing method according to an embodiment of the present invention, the planarization of the planarization layer lithography process, a plurality of through holes are formed with a photolithography process for the same photolithography process; wherein,

[0013] 所述光刻工艺采用的掩模板包括透光区域和非透光区域; [0013] The mask comprises a photolithography process using a light-transmitting region and a non-transparent region;

[0014] 与所述凸起结构对应的透光区域和与所述过孔对应的透光区域的透光率不同。 [0014] The convex structure corresponding to the light transmitting region and the light transmittance through the light-transmitting hole corresponding to the different regions.

[0015] 在一种可能的实现方式中,在本发明实施例提供的上述制作方法中,所述平坦层的材料为正性光刻胶; [0015] In one possible implementation, in the manufacturing method according to an embodiment of the present invention, the material of the flat layer is a positive photoresist;

[0016] 所述采用具有与多个所述凸起结构相匹配图形的掩模板,对所述平坦层进行光刻工艺,以平坦化所述平坦层,具体包括: [0016] The use of a plurality of said projections having a configuration that matches the pattern of the mask, the planarization layer lithography process to planarize the planarization layer comprises:

[0017] 采用具有与多个所述凸起结构相同图形的掩模板,对所述平坦层进行光刻工艺, 以平坦化所述平坦层。 [0017] The mask having the same pattern structure of a plurality of said projections, said flat layer of a photolithography process, to planarize the planarization layer.

[0018] 在一种可能的实现方式中,在本发明实施例提供的上述制作方法中,所述平坦层的材料为负性光刻胶; [0018] In one possible implementation, in the manufacturing method according to an embodiment of the present invention, the planar material is a negative photoresist layer;

[0019] 所述采用具有与多个所述凸起结构相匹配图形的掩模板,对所述平坦层进行光刻工艺,以平坦化所述平坦层,具体包括: [0019] The use of a plurality of said projections having a configuration that matches the pattern of the mask, the planarization layer lithography process to planarize the planarization layer comprises:

[0020] 采用具有与多个所述凸起结构互补图形的掩模板,对所述平坦层进行光刻工艺, 以平坦化所述平坦层。 [0020] The structure having a plurality of protrusions complementary to the pattern of the mask with the planarization layer lithography process to planarize the planarization layer.

[0021] 在一种可能的实现方式中,在本发明实施例提供的上述制作方法中,在所述采用具有与多个所述凸起结构相匹配图形的掩模板,对所述平坦层进行光刻工艺,以平坦化所述平坦层之前,还包括: [0021] In one possible implementation, in the manufacturing method according to an embodiment of the present invention, using the mask having the plurality of protrusions to match the pattern of structures, the planar layer photolithography process, prior to planarizing the planarization layer, further comprising:

[0022] 测量各所述凸起结构的高度,根据各所述凸起结构的高度确定对所述平坦层进行光刻的曝光量、曝光时间以及显影时间。 [0022] measure the height of each of the raised structure, determining the planarization layer lithography exposure amount depending on the height of each of the convex structure, the exposure time and development time.

[0023] 在一种可能的实现方式中,在本发明实施例提供的上述制作方法中,所述凸起结构的高度在l〇nm-lym之间; [0023] In one possible implementation, in the embodiment of the present invention, the above-described manufacturing method provided in the embodiment, the height of the raised structure is between l〇nm-lym;

[0024] 所述曝光量为1()mJ/cm2-5〇〇mJ/cm2,所述曝光时间为30s-150s,所述显影时间为10s_200s。 [0024] The exposure amount was 1 () mJ / cm2-5〇〇mJ / cm2, the exposure time was 30s-150s, the development time was 10s_200s.

[0025] 在一种可能的实现方式中,在本发明实施例提供的上述制作方法中,还包括: [0025] In one possible implementation, in the manufacturing method according to an embodiment of the present invention, further comprising:

[0026] 对光刻工艺后的所述平坦层进行烘烤。 [0026] The planarization layer after the baking photolithography process.

[0027] 本发明实施例还提供了一种顶发射有机电致发光显示面板,所述顶发射有机电致发光显示面板采用上述制作方法制作。 Example [0027] The present invention also provides a top-emitting organic electroluminescence display panel, the top emission organic EL display panel manufacturing method using the above-described production.

[0028] 本发明实施例还提供了一种显示装置,包括上述顶发射有机电致发光显示面板。 [0028] Embodiments of the present invention further provides a display apparatus comprising the above-described top-emitting organic electroluminescence display panel.

[0029] 本发明有益效果如下: [0029] Advantageous effects of the present invention are as follows:

[0030]本发明实施例提供了一种顶发射有机电致发光显示面板、其制作方法及显示装置,该制作方法包括:在衬底基板上依次形成多个膜层以构成表面具有多个凸起结构的薄膜晶体管;在薄膜晶体管上形成平坦层;采用具有与多个凸起结构相匹配图形的掩模板,对平坦层进行光刻工艺,以平坦化平坦层。 [0030] The present invention provides a top-emitting organic electroluminescence display panel and a display device manufacturing method, the manufacturing method comprising: sequentially forming a plurality of film layers on a base substrate to form a surface having a plurality of projections since the thin film transistor structure; forming a planarization layer on the thin film transistor; a plurality of projections having a structure employed to match the pattern mask, a photolithography process of the planarization layer to planarize planarization layer. 本发明实施例提供的制作方法,通过采用具有与薄膜晶体管表面上的多个凸起结构相匹配图形的掩模板,对平坦层进行光刻工艺,以平坦化该平坦层,能够提高平坦层的平坦性能,使在平坦上制作的0LED薄膜的厚度更加均匀,因而,可以提高像素内发光均匀性,缓解0LED器件的颗粒感。 Production method provided in the embodiment of the present invention, by employing a structure having a plurality of projections on the surface of a thin film transistor that matches the pattern of the mask on the planarization layer lithography process to planarize the planarization layer can be improved planarization layer flat performance, the thickness of the film on a flat 0LED made more uniform, and therefore, can improve the uniformity of the light emitting pixels, alleviate graininess 0LED device.

附图说明 BRIEF DESCRIPTION

[0031] 图1为本发明实施例提供的一种顶发射有机电致发光显示面板的制作方法的流程图; [0031] FIG INVENTION An embodiment of the present embodiment provides a top-emitting organic electroluminescence flowchart of a method of manufacturing a display panel;

[0032] 图2a为本发明实施例提供的制作方法的结构示意图之一; [0032] FIG. 2a structure manufacturing method according to an embodiment of the present invention, a schematic view of one;

[0033] 图2b为本发明实施例提供的制作方法的结构示意图之二; [0033] FIG. 2b embodiment of the manufacturing method of the structure provided in the present invention, a schematic diagram of the two;

[0034] 图2c为本发明实施例提供的制作方法的结构示意图之三; Structure manufacturing method according to an embodiment of the [0034] present invention. FIG. 2c a schematic view of the three;

[0035]图2d为本发明实施例提供的制作方法的结构示意图之四; [0035] Figure 2d is a schematic structural embodiment of the invention provides a method for manufacturing a schematic view of the four embodiment;

[0036]图3为本发明实施例提供的薄膜晶体管的俯视图; [0036] FIG. 3 is a plan view of a thin film transistor according to an embodiment of the present invention;

[0037]图4a和图4b分别为形成平坦层后对应图3中虚线AA'和BB'处的高度分布图; [0037] Figures 4a and 4b, respectively, a height distribution dashed lines in FIG. 3 AA 'and BB' is formed at the rear view of the planarization layer corresponding to;

[0038] 其中,、衬底基板;102、薄膜晶体管;1〇3、凸起结构;104、平坦层;105、掩模板; 106、凸起部位;200、子像素单元。 [0038] ,, wherein the base substrate; 102, a thin film transistor; 1〇3 raised structures; 104, planarization layer; 105, mask; 106, protruding parts; 200, sub-pixel units.

具体实施方式 detailed description

[0039] 针对现有技术中存在的由于平坦层平坦化性能不佳导致的像素内发光不均匀的问题,本发明实施例提供了一种顶发射有机电致发光显示面板、其制作方法及显示装置。 [0039] For the problems due to the pixel planarization layer planarizing the uneven light emission due to poor performance of the prior art, the present invention provides a top-emitting organic electroluminescence display panel and a display manufacturing method device. [0040]下面结合附图,对本发明实施例提供的背光模组及显示装置的具体实施方式进行详细地说明。 [0040] will be described below in detail in conjunction with the accompanying drawings, embodiments provide a backlight module and the display device of specific embodiments of the present invention. 附图中各膜层的厚度和形状不反映真实比例,目的只是示意说明本发明内容。 Thickness and shape of each drawing film layer does not reflect the true ratio of illustration only describe the present invention. [0041] 本发明实施例提供了一种顶发射有机电致发光显示面板的制作方法,如图1所示, 包括: [0041] The present invention provides a top-emitting organic electroluminescence display panel manufacturing method, shown in Figure 1, comprising:

[0042] S101、在衬底基板上依次形成多个膜层以构成表面具有多个凸起结构的薄膜晶体管; [0042] S101, a plurality of layers are sequentially formed on a base substrate to form a surface having a plurality of convex structures of a thin film transistor;

[0043] S102、在薄膜晶体管上形成平坦层; [0043] S102, a flat layer is formed on the thin film transistor;

[0044] S103、采用具有与多个凸起结构相匹配图形的掩模板,对平坦层进行光刻工艺,以平坦化平坦层。 [0044] S103, using a plurality of protrusions having a configuration that matches the pattern mask, a photolithography process on the planarization layer to planarize planarization layer.

[0045]本发明实施例提供的制作方法,通过采用具有与薄膜晶体管表面上的多个凸起结构相匹配图形的掩模板,对平坦层进行光刻工艺,以平坦化该平坦层,能够提高平坦层的平坦性能,使在平坦上制作的0LED薄膜的厚度更加均匀,因而,可以提高像素内发光均匀性, 缓解OLH)器件的颗粒感。 [0045] The manufacturing method according to an embodiment of the present invention, by employing a structure having a plurality of projections on the surface of a thin film transistor that matches the pattern of the mask, a photolithography process on the planarization layer to planarize the layer of planarization can be improved planarization performance flat layer, the thickness of the film 0LED fabricated on planar more uniform, and therefore, can improve the uniformity of the light emitting pixels, ease OLH is grainy) device.

[0046] 参照图2a_图2d,由于衬底基板101上的薄膜晶体管1〇2—般由多个膜层构成,例如可以包括栅极、源极、漏极以及栅极绝缘层等膜层,每个膜层都具有特定的图形,多个膜层叠加到一起就会出现多个凸起结构103,如图2a所示,凸起结构103的图形是由构成薄膜晶体管102的各个膜层的图形决定的,一般在凸起结构1〇3的高度在lOnm-lwn之间,因此,可以根据构成薄膜晶体管102各个膜层的图形来确定凸起结构1〇3的图形,从而确定后续步骤S103中掩模板的图形。 [0046] Referring to FIG 2a_ FIG. 2d, since the thin film transistor 101 on the base substrate composed of a plurality of layers 1〇2- as, for example, may include a gate, a source, a drain and a gate insulating film layer and the like each layer has a specific pattern, a plurality of superimposed layers with a plurality of projections occur structure 103, as shown, the raised pattern structure 103 is constituted by a thin film transistor of the respective layers in FIG. 2a 102 determined pattern, typically at a height between the raised structures 1〇3 lOnm-lwn, therefore, a protrusion pattern may be determined according to the structure 1〇3 pattern layer 102 constituting the respective thin film transistor, thereby determining the subsequent step graphics templates S103 in cover. 图3示出了各个子像素单元200中制作薄膜晶体管102之后的凸起结构103的图形,从图3可以看出,各个子像素单元200中的凸起结构103的图形基本相同。 FIG 3 shows a graphical convex structure after fabricating a thin film transistor 102 103 200 each subpixel units, can be seen from Figure 3, the graphical raised structures 200 each sub-pixel units 103 is substantially the same.

[0047]上述步骤S102中一般采用树脂类材料(例如光刻胶)来制作平坦层1〇4,制作平坦层104的材料一般具有一定的粘性和流动性,因而在形成的平坦层104上凸起结构1〇3对应的位置处也会有一定高度的凸起部位1〇6,如图2b所示,且平坦层1〇4上凸起部位106的高度小于薄膜晶体管102上凸起结构103的高度,可以根据薄膜晶体管1〇2上凸起结构103的高度以及平坦层104的厚度,来推算得到平坦层104上凸起部位106的高度。 [0047] step S102 commonly used resinous material (e.g., photoresist) layer fabricated 1〇4 flat, planar material layer 104 typically has a certain viscosity and flow characteristics, and thus the projections 104 formed on the planarization layer starting at a position corresponding to 1〇3 structure will have a certain height of the projection portion 1〇6, shown in Figure 2b, and the height of the protrusion portion 106 1〇4 planarization layer on the thin film transistor 102 is smaller than the raised structures 103 height, can height and the thickness of the flat layer 104 of the raised structures 103 on the thin film transistor 1〇2 to obtain the estimated height of the raised portion 106 on the planarization layer 104. 由上述步骤S101中薄膜晶体管102的结构可以确定步骤S103中的掩模板105,由于平坦层104—般为树脂类材料, 因此,可以采用光刻工艺去除平坦层104上的凸起部位106。 By the structure of the thin film transistor 102 may be determined in step S101 described above reticle 105 in step S103, since the planarization layer is generally from 104- resinous material, thus, can be removed using a photolithographic process on the planarization layer protruding parts 104,106.

[0048]图4a和图4b分别为形成平坦层104后对应图3中虚线AA'和BB'处的高度分布图,图4a中,H表示高度,X表示在水平方向上的位置,图4b中,H表示高度,Y表示在竖直方向上的位置。 Height profile corresponding to [0048] Figures 4a and 4b are formed in the planarization layer 104 after a dashed line AA 'and BB' of the 3, FIG. 4a, H represents the height, X represents the position in the horizontal direction, FIG. 4b , H represents height, Y represents a position in the vertical direction. 在具体实施时,可以按照与图4a和图4b类似的方式,得到平坦层104各个位置的高度分布,根据得到的平坦层104各个位置的高度分布来确定掩模板中透光区域的透光率,以正性光刻胶为例,可以设置高度值较大的位置的透光率较高,高度值较小的位置的透光率较低, 因而,使平坦层104上高度值较大的位置去除的较多,高度值较低的位置去除的较少,从而使平坦层104趋于平坦。 In a specific embodiment, it is possible in a similar manner to FIGS. 4a and 4b, the position of each obtained height distribution of the planarization layer 104, the light transmittance is determined in the light-transmitting mask areas according to the respective positions of the height distribution obtained planarization layer 104 , a positive photoresist, for example, the value may be set higher height position larger transmittance, low light transmittance value of smaller height position, therefore, the value of the height of the upper planar layer 104 larger more removed location, removing less height value lower position, so that the planarization layer 104 to flatten. 因而后续在平坦层104上制作功能层时,无论采用蒸镀制程还是溶液制程,得到的功能层都会比较均匀,从而避免由于功能层的厚度不均匀导致0LED器件的发光不均匀。 When thus making the subsequent functional layer on the planarization layer 104, regardless of the vapor deposition process or a solution process, will obtain a uniform functional layer, thereby avoiding non-uniform thickness of the functional layers leads to a light emitting device 0LED unevenness.

[0049] 在实际应用时,当平坦层104上的凸起部位106的高度基本相同时,如图4a所示,掩模板上各透光区域的透光率可以设置为相同,若平坦层104上各凸起部位106的高度相差较多时,可以取各高度的均值来设置统一的透过率,也可以根据不同位置的高度分别设置透过率,此处不做限定。 [0049] In practice, when the projection portion 104 on the planarization layer 106 of a height substantially the same time, as shown in FIG mask plate transmittance of each light-transmitting region may be set to the same 4a, when the planarization layer 104 the height of each projection portion 106 on the difference between the more highly may take the mean of each set of uniform transmittance, the transmittance may be separately provided at different positions according to the height is not limited here.

[0050] 进一步地,在上述步骤S102之后,还可以包括: [0050] Further, after the above-described step S102, it may further comprise:

[0051] 对所述平坦层进行光刻工艺,以在非显示区域形成多个过孔。 [0051] The photolithography process on the planarization layer to form a plurality of through holes in a non-display area.

[0052] 通过平坦层上的非显示区域形成多个过孔,可以使0LED器件的阳极与薄膜晶体管连接。 [0052] by a non-planar layer on the plurality of vias formed in the display region, the thin film transistor can 0LED the anode device is connected. 应该说明的是,制作过孔的光刻工艺可以在平坦化平坦层的光刻工艺之前,也可以在平坦化平坦层的光刻工艺之后,也可以同时制作,此处不对两次光刻的顺序进行限定。 It should be noted that the photolithographic process can be made via a photolithographic process prior to the planarizing flat layer, planarization may be performed after a photolithography process planarization layer may be produced simultaneously, not here two lithography sequence is defined.

[0053]更进一步地,平坦化所述平坦层的光刻工艺,与形成多个所述过孔的光刻工艺为同一次光刻工艺;其中, [0053] Still further, the planarizing layer is planar lithographic process, said lithographic process of forming a plurality of through holes is same photolithography process; wherein,

[0054] 所述光刻工艺采用的掩模板包括透光区域和非透光区域; [0054] The mask comprises a photolithography process using a light-transmitting region and a non-transparent region;

[0055] 与所述凸起结构对应的透光区域和与所述过孔对应的透光区域的透光率不同。 [0055] The convex structure corresponding to the light transmitting region and the light transmittance through the light-transmitting hole corresponding to the different regions. [0056] 通过采用特殊的掩模板,将两次光刻工艺合并为一次光刻工艺,可以节省一次工艺,从而节约成本,具体地,一般凸起结构的高度小于平坦层的厚度,而过孔等于平坦层的厚度,所以,可以设置掩模板上过孔对应位置的透光区域的透过率较高,例如可以设置为100%、95 %或90 %等,而凸起结构对应位置的透光区域的透过率较低,例如50 %、45 %或60%等,具体透过率的数值需要根据凸起结构的高度以及平坦层的厚度决定。 [0056] By using a special mask, the photolithography process two combined into a photolithography process, a process can be saved, cost savings, in particular, the general structure of the projection is smaller than the height of the thickness of the flat layer, and vias the higher the transmittance is equal to the thickness of the flat layer, it is possible to set the position of the mask plate through the hole of the transmissive area corresponding to, for example, set to 100%, 95%, 90%, or the like, convex structure corresponding to the position of the lens a lower light transmittance region, for example 50%, 45% or 60%, etc., the value determined according to the specific needs of the transmittance and the thickness of the planarization layer height of the raised structures.

[0057] 上述步骤S103中,掩模板105的图形与多个凸起结构103的图形相匹配,因而对平坦层104进行光刻工艺可以将平坦层104上的凸起部位106去除,以平坦化平坦层104,在具体实施时,掩模板105的图形与平坦层104的材料的性能有关,包括以下两种情况: [0057] In step S103, mask pattern 105 with a plurality of protrusion pattern match structure 103, and thus a photolithography process planarization layer 104 may be convex portions on the planarization layer 104 106 removed to planarize planarization layer 104, in the specific embodiment, the material properties associated with the mask pattern 104 of the planarization layer 105, includes the following two cases:

[0058] 情况一:平坦层104的材料为正性光刻胶; [0058] where a: flat material layer 104 is a positive photoresist;

[0059] 上述步骤S103,可以具体包括: [0059] The above-described step S103, the can comprises:

[0060]采用具有与多个凸起结构103相同图形的掩模板105,对平坦层104进行光刻工艺, 以平坦化平坦层104,如图2c所示。 [0060] The mask 105 has the same pattern of the plurality of raised structures 103, 104 of the planarization layer lithography process to planarize the planarization layer 104, shown in Figure 2c.

[0061]由于正性光刻胶曝光后可溶于对应的显影液,因此,采用与凸起结构1〇3相同图形的掩模板105对平坦层104进行曝光后,平坦层104对应于凸起结构103的部分溶于显影液, 因而去除平坦层104上的凸起部位106,从而提高了平坦层104的平坦性能。 [0061] Since the corresponding soluble positive photoresist developer after exposure, and therefore, using the same exposure pattern mask 1〇3 raised structures 105 pairs planar layer 104, the planarization layer 104 corresponding to the projections partial structure 103 was dissolved in a developing solution, thereby removing the protrusion portion 104 on the planarization layer 106 to improve the performance of the planarization layer 104 is flat.

[0062] 情况二:平坦层104的材料为负性光刻胶; [0062] Case 2: a flat material layer 104 is a negative photoresist;

[0063] 上述步骤S103,可以具体包括: [0063] The above-described step S103, the can comprises:

[0064] 采用具有与多个凸起结构103互补图形的掩模板105,对平坦层104进行光刻工艺, 以平坦化平坦层104,如图2d所示。 [0064] The plurality of protrusions 103 having a configuration complementary mask pattern 105, the planarization layer 104 of a photolithography process, to planarize the planarization layer 104, shown in Figure 2d.

[0065]由于负性光刻胶曝光后不溶于显影液,因此,采用与凸起结构103互补图形的掩模板105对平坦层104进行曝光后,平坦层104被曝光的部分(除凸起结构103以外的部分)不溶于显影液,而平坦层104对应于凸起结构103的部分溶于显影液,从而可以去除平坦层104上的凸起部位106,提高了平坦层104的平坦性能。 [0065] Since the insoluble negative resist solution after exposure, therefore, the use of post-exposure portion 103 and a complementary projection pattern mask 105 pairs of planar structure layer 104, the planarization layer 104 is exposed (except convex structure portion other than the 103) is not soluble in a developer, and the planarization layer 104 corresponding to the raised structure 103 of the portion soluble in a developer, thereby removing the protrusion portion 104 on the planarization layer 106 to improve the performance of the planarization layer 104 is flat.

[0066] 进一步地,为了更精确的去除平坦层上的凸起部位,在上述步骤S103之前,还可以包括: [0066] Furthermore, for more accurate removal of the tab of the planarization layer, prior to the above step S103, the may further comprises:

[0067]测量各凸起结构的高度,根据各凸起结构的高度确定对平坦层进行光刻的曝光量、曝光时间以及显影时间。 [0067] measuring the height of each raised structures, determination of the planarization layer lithography exposure amount, exposure time and development time depending on the height of each of the raised structures.

[0068] 在具体实施时,测量各凸起结构的高度,可以包括: [0068] In a specific embodiment, the height of each convex structure may include:

[0069] 采用台阶仪或光学测试的方式测量各凸起结构的高度。 [0069] The step apparatus or optical test way to measure the height of each protruding structures.

[0070] 通过确定各凸起结构的高度,从而可以根据各凸起结构的高度,确定去除平坦层上的凸起部位需要的曝光量、曝光时间以及显影时间,从而可以进一步提高平坦层的平坦性能。 [0070] By determining the height of each projection structure, so that according to the height of each protrusion structure, determining the amount of exposure is removed, the exposure time and development time projection portion on a flat layer needs to be further improved flat planar layer performance.

[0071]在实际应用时,如果各凸起结构的高度相差比较大,可以采用特殊的掩模板对平坦层进行曝光,可以根据凸起结构的高度来设置掩模板的透光区域的透光率,例如透光区域可以设置为50%透光、60%或75%透光等数值,以使不同高度的凸起结构有不同的曝光量,因而使平坦层更加平坦。 [0071] In practice, if the height of each projection is relatively large difference between the structure, may be employed a special pair of flat mask layer is exposed, it can be set a light transmittance of the mask region depending on the height of the raised structures , for example, the light-transmitting region may be set to 50% transmission, 60% or 75% transmission value, etc., so that different heights of the raised structures have different exposures, thus making more flat planar layer.

[0072] 在具体实施时,凸起结构的高度一般在10nm-lwn之间; [0072] In a specific embodiment, the raised height of the structures in general between 10nm-lwn;

[0073] 曝光量为10mJ/cm2-500mJ/cm2,曝光时间为30s-150s (优选为50s),显影时间为10s-200s〇 [0073] The exposure amount of 10mJ / cm2-500mJ / cm2, the exposure time of 30s-150s (preferably 50s), development time of 10s-200s〇

[0074]更具体地,曝光量优选为10011^/〇112-200111_1/〇112。 [0074] More specifically, the exposure amount is preferably 10011 ^ / 〇112-200111_1 / 〇112.

[0075] 更进一步地,本发明实施例提供的上述制作方法中,还可以包括: [0075] Still further, the above-described embodiment of the manufacturing method provided in the present invention, further comprising:

[0076] 对光刻工艺后的平坦层进行烘烤。 [0076] The planarization layer after the baking photolithography process.

[0077] 通过对光刻工艺后的平坦层进行烘烤,可以使平坦层固化,可以使平坦层的边缘位置进一步平坦化,从而提高平坦层的平坦性能。 [0077] The planarization layer by a photolithography process after the baking, the cured layer can be made flat, planar edge positions can be further planarized layer, thereby improving the performance of the flat planar layer.

[0078] 基于同一发明构思,本发明实施例还提供了一种顶发射有机电致发光显示面板, 该顶发射有机电致发光显示面板采用上述制作方法制作。 [0078] Based on the same inventive concept, an embodiment of the present invention further provides a top-emitting organic electroluminescence display panel, the top emission organic EL display panel manufacturing method using the above-described production. 由于该顶发射有机电致发光显示面板解决问题的原理与上述制作方法相似,因此该顶发射有机电致发光显示面板的实施可以参见上述制作方法的实施,重复之处不再赘述。 Since the top emission organic electroluminescent display panel similar principles to solve the problem with the above-described manufacturing method, so that the top emission organic EL display panel of embodiment can be found in the above-described manufacturing method of the embodiment, repeated description of which will not be repeated.

[0079] 基于同一发明构思,本发明实施例提供一种显示装置,包括上述顶发射有机电致发光显示面板,该显示装置可以应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。 [0079] Based on the same inventive concept, an embodiment of the present invention provides a display apparatus comprising the above-described top-emitting organic electroluminescence display panel, the display device can be used in mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frame , any product or other navigation means having a display function. 由于该显示装置解决问题的原理与上述顶发射有机电致发光显示面板相似,因此该显示装置的实施可以参见上述顶发射有机电致发光显示面板的实施,重复之处不再赘述。 Since the display principle of the above-described problem-solving means top-emitting organic electroluminescence display panel is similar and therefore the display device can be found in the above-described embodiment of a top-emitting embodiment has the organic electroluminescent display panel, repeated description of which will not be repeated.

[0080] 本发明实施例提供的顶发射有机电致发光显示面板、其制作方法及显示装置,通过米用具有与薄膜晶体管表面上的多个凸起结构相匹配图形的掩模板,对平坦层进行光刻工艺,以平坦化该平坦层,能够提高平坦层的平坦性能,使在平坦上制作的0LED薄膜的厚度更加均匀,因而,可以提高像素内发光均匀性,缓解〇mD器件的颗粒感。 [0080] The embodiment provides a top-emitting embodiment of the present invention is an organic electroluminescent display panel and a display device manufacturing method, by meter having a plurality of convex structures on the surface of a thin film transistor that matches the pattern of the mask on the planarization layer photolithography process is performed to planarize the planarization layer, can improve the performance of the flat planar layer, so 0LED film fabricated on planar more uniform thickness, and thus can improve the uniformity of the light emitting pixels, the device alleviate graininess 〇mD .

[0081] 显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。 [0081] Obviously, those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. 这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。 Thus, if these modifications and variations of the present invention fall within the claims of the invention and the scope of equivalents thereof, the present invention intends to include these modifications and variations.

Claims (10)

  1. 1. 一种顶发射有机电致发光显示面板的制作方法,其特征在于,包括: 在衬底基板上依次形成多个膜层以构成表面具有多个凸起结构的薄膜晶体管; 在所述薄膜晶体管上形成平坦层; 采用具有与多个所述凸起结构相匹配图形的掩模板,对所述平坦层进行光刻工艺,以平坦化所述平坦层。 A top-emitting organic electroluminescence display panel manufacturing method, characterized by comprising: a plurality of layers are sequentially formed on a base substrate to form a surface having a plurality of convex structures of a thin film transistor; said film a transistor formed on the planarization layer; using mask having a plurality of said protrusions matches the pattern of structures, the planar layer lithography process to planarize the planarization layer.
  2. 2. 如权利要求1所述的制作方法,其特征在于,在所述薄膜晶体管上形成平坦层之后, 还包括: 对所述平坦层进行光刻工艺,以在非显示区域形成多个过孔。 2. The manufacturing method according to claim 1, wherein, after forming the planarization layer on the thin film transistor, further comprising: a planarization layer the photolithography process to form a non-display area in the plurality of vias .
  3. 3.如权利要求2所述的制作方法,其特征在于,平坦化所述平坦层的光刻工艺,与形成多个所述过孔的光刻工艺为同一次光刻工艺;其中, 所述光刻工艺采用的掩模板包括透光区域和非透光区域; 与所述凸起结构对应的透光区域和与所述过孔对应的透光区域的透光率不同。 3. The manufacturing method according to claim 2, wherein said planarizing layer flat photolithographic process, the photolithographic process is formed with a plurality of holes for the same photolithography process; wherein said mask comprises a photolithography process using a light-transmitting region and a non-transparent region; different light transmittance of the light-transmissive region corresponding to the raised structure and the vias corresponding to the light-transmitting region.
  4. 4.如权利要求1所述的制作方法,其特征在于,所述平坦层的材料为正性光刻胶; 所述采用具有与多个所述凸起结构相匹配图形的掩模板,对所述平坦层进行光刻工艺,以平坦化所述平坦层,具体包括: 采用具有与多个所述凸起结构相同图形的掩模板,对所述平坦层进行光刻工艺,以平坦化所述平坦层。 4. The manufacturing method according to claim 1, characterized in that the flat material is a positive photoresist layer; using a mask having a plurality of said protrusions matches the pattern of structures of the said planar layer lithography process to planarize the planarization layer comprises: using a plurality of mask has the same pattern of the raised structure, said flat layer of a photolithography process, to planarize the planarization layer.
  5. 5. 如权利要求1所述的制作方法,其特征在于,所述平坦层的材料为负性光刻胶; 所述采用具有与多个所述凸起结构相匹配图形的掩模板,对所述平坦层进行光刻工艺,以平坦化所述平坦层,具体包括: 采用具有与多个所述凸起结构互补图形的掩模板,对所述平坦层进行光刻工艺,以平坦化所述平坦层。 5. The manufacturing method according to claim 1, characterized in that the flat material is a negative photoresist layer; using a mask having a plurality of said protrusions matches the pattern of structures of the said planar layer lithography process to planarize the planarization layer comprises: using a plurality of said projections having a configuration complementary patterns and mask, the planarization layer lithography process to planarize the planarization layer.
  6. 6. 如权利要求1-5任一项所述的制作方法,其特征在于,在所述采用具有与多个所述凸起结构相匹配图形的掩模板,对所述平坦层进行光刻工艺,以平坦化所述平坦层之前,还包括: 测量各所述凸起结构的高度,根据各所述凸起结构的高度确定对所述平坦层进行光刻的曝光量、曝光时间以及显影时间。 6. The manufacturing method of any one of claims 1-5, wherein, in use of the mask having the plurality of protrusions to match the structure of the pattern, the photolithography process planarization layer prior to planarizing the planarization layer, further comprising: measuring a height of each of the raised structure, determining the planarization layer lithography exposure amount depending on the height of each of the convex structure, the exposure time and development time .
  7. 7. 如权利要求6所述的制作方法,其特征在于,所述凸起结构的高度在1 Onm- lym之间; 所述曝光量为10mJ/cm2-500mJ/cm2,所述曝光时间为30s_150s,所述显影时间为10s- 200s。 7. The manufacturing method according to claim 6, characterized in that the height of the raised structure is between 1 Onm- lym; the exposure amount of 10mJ / cm2-500mJ / cm2, the exposure time is 30s_150s the development time was 10s- 200s.
  8. 8. 如权利要求1所述的制作方法,其特征在于,还包括: 对光刻工艺后的所述平坦层进行烘烤。 8. The manufacturing method according to claim 1, characterized in that, further comprising: a planarization layer after the baking photolithography process.
  9. 9. 一种顶发射有机电致发光显示面板,其特征在于,所述顶发射有机电致发光显示面板采用如权利要求1-8任一项所述的制作方法制作。 A top-emitting organic electroluminescence display panel, wherein the top emission organic EL display panel using a method as defined in claims 1-8 of the production.
  10. 10. —种显示装置,其特征在于,包括如权利要求9所述的顶发射有机电致发光显示面板。 10. - kind of display device, wherein said emission comprises a top as claimed in claim 9 An organic electroluminescent display panel.
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