CN106783887A - A kind of array base palte and preparation method thereof, display device - Google Patents

A kind of array base palte and preparation method thereof, display device Download PDF

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Publication number
CN106783887A
CN106783887A CN201710002822.7A CN201710002822A CN106783887A CN 106783887 A CN106783887 A CN 106783887A CN 201710002822 A CN201710002822 A CN 201710002822A CN 106783887 A CN106783887 A CN 106783887A
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CN
China
Prior art keywords
layer
array base
base palte
conductive layer
substrate
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CN201710002822.7A
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Chinese (zh)
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CN106783887B (en
Inventor
占建英
冯思林
张俊
沈奇雨
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to CN201710002822.7A priority Critical patent/CN106783887B/en
Publication of CN106783887A publication Critical patent/CN106783887A/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/127Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate

Abstract

The present invention provides a kind of array base palte and preparation method thereof, display device, is related to display technology field, can improve display effect.The array base palte includes:GOA regions, the GOA regions are provided with thin film transistor (TFT), and the thin film transistor (TFT) includes the grid, gate insulation layer, active layer, source electrode and the drain electrode that are successively set on substrate;The array base palte also includes being successively set on the passivation layer and conductive layer of the source electrode and the drain electrode away from the substrate side;Wherein, orthographic projection of the conductive layer orthographic projection over the substrate with the active layer over the substrate is Chong Die.

Description

A kind of array base palte and preparation method thereof, display device

Technical field

The present invention relates to display technology field, more particularly to a kind of array base palte and preparation method thereof, display device.

Background technology

Requirement more and more higher with the development of Display Technique, particularly small-size screen to narrow frame.With TFT The continuous improvement of (Thin Film Transistor, thin film transistor (TFT)) switching characteristic, prior art is frequently with by GOA (Gate Driver on Array, array base palte row actuation techniques) gate driving circuit is integrated in the neighboring area of array base palte, with Reduce the use of IC (integrated circuit, integrated circuit), it is possible to increase the integrated level of display device, realize narrow frame While design, cost of manufacture is reduced.

In the prior art, as shown in figure 1, array base palte viewing area and GOA regions, GOA regions are provided with film crystal Pipe, thin film transistor (TFT) includes setting gradually grid 11, gate insulation layer 12, active layer 13, source electrode 14, drain electrode on the substrate 10 15;Array base palte also includes being successively set on the passivation layer 16 of source electrode 14 and drain electrode 15 away from the side of substrate 10.Grid 11 is having Active layer 13 can form raceway groove 110 before grid with the interface of gate insulation layer 12, can be formed with the interface of passivation layer 16 in active layer 13 Raceway groove 120 after grid.When TFT is closed, preceding raceway groove 110 and rear raceway groove 120 can form larger GOA regions channel leakage stream, Display device is easily caused to occur showing bad.

The content of the invention

Embodiments of the invention provide a kind of array base palte and preparation method thereof, display device, can improve display effect.

To reach above-mentioned purpose, embodiments of the invention are adopted the following technical scheme that:

A kind of first aspect, there is provided array base palte, including GOA regions, the GOA regions are provided with thin film transistor (TFT), institute Stating thin film transistor (TFT) includes the grid, gate insulation layer, active layer, source electrode and the drain electrode that are successively set on substrate;The array base Plate also includes being successively set on the passivation layer and conductive layer of the source electrode and the drain electrode away from the substrate side;Wherein, institute State orthographic projection of the conductive layer orthographic projection over the substrate with the active layer over the substrate Chong Die.

Optionally, the conductive layer covers the GOA regions.

Optionally, the conductive layer includes openwork part, and conductive structure, the conductive knot are provided with the openwork part Structure insulate with the conductive layer.

Preferably, via is provided with the passivation layer, the conductive structure is electrically connected by the via with the drain electrode Connect.

Preferably, the conductive layer is metal conducting layer.

It is further preferred that the material of the metal conducting layer is light screening material.

A kind of second aspect, there is provided preparation method of array base palte, the array base palte includes GOA regions, the GOA areas Domain is formed with thin film transistor (TFT), grid that the thin film transistor (TFT) includes being sequentially formed on substrate, gate insulation layer, active layer, Source electrode and drain electrode;The array base palte also includes being sequentially formed at the source electrode and the drain electrode away from the blunt of the substrate side Change layer and conductive layer;Wherein, conductive layer orthographic projection over the substrate and the active layer be over the substrate just Projection is overlapped.

Optionally, the conductive layer covers the GOA regions.

Optionally, the conductive layer includes openwork part, and conductive structure, the conductive knot are formed with the openwork part Structure insulate with the conductive layer.

A kind of third aspect, there is provided display device, including the array base palte described in first aspect.

The embodiment of the present invention provides a kind of array base palte and preparation method thereof, display device, by thin in GOA regions The top of film transistor sets one layer of conductive layer so that conductive layer forms conductive layer back of the body ditch at active layer and gate insulator layer interface Road, the raceway groove before the conductive layer that active layer and passivation layer interface are formed.Conductive layer is input into low voltage signal, works as film crystal When pipe is closed, the leakage current that raceway groove is produced before the leakage current and grid of conductive layer back of the body raceway groove generation interacts and offsets;It is conductive The leakage current that the leakage current that raceway groove is produced before layer is produced with grid back of the body raceway groove interacts and offsets.So as to GOA regions can be reduced The leakage current of interior thin film transistor (TFT), when array base palte is applied into display device, it is ensured that the display effect of display device.

Brief description of the drawings

In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with Other accompanying drawings are obtained according to these accompanying drawings.

A kind of structural representation in array base palte GOA regions that Fig. 1 is provided for prior art;

Fig. 2 is a kind of structural representation one in array base palte GOA regions provided in an embodiment of the present invention;

Fig. 3 is a kind of structural representation two in array base palte GOA regions provided in an embodiment of the present invention;

Fig. 4 (a) is a kind of structural representation three in array base palte GOA regions provided in an embodiment of the present invention;

Fig. 4 (b) is a kind of schematic top plan view in array base palte GOA regions provided in an embodiment of the present invention;

Fig. 4 (c) is a kind of structural representation four in array base palte GOA regions provided in an embodiment of the present invention;

Fig. 5 is a kind of flow chart of the preparation method of conductive layer provided in an embodiment of the present invention;

Fig. 6 is a kind of schematic diagram one of the preparation method of conductive layer provided in an embodiment of the present invention;

Fig. 7 is a kind of schematic diagram two of the preparation method of conductive layer provided in an embodiment of the present invention;

Fig. 8 is a kind of schematic diagram three of the preparation method of conductive layer provided in an embodiment of the present invention;

Fig. 9 is a kind of schematic diagram four of the preparation method of conductive layer provided in an embodiment of the present invention;

Figure 10 is a kind of schematic diagram five of the preparation method of conductive layer provided in an embodiment of the present invention;

Figure 11 is a kind of structural representation one of array base palte provided in an embodiment of the present invention;

Figure 12 is a kind of structural representation two of array base palte provided in an embodiment of the present invention.

Reference:

10- substrates;11- grids;12- gate insulation layers;13- active layers;14- source electrodes;15- drains;16- passivation layers;17- leads Electric layer;171- membrane of conducting layer;18- conductive structures;191- photoresists;19- photoresist layers;Raceway groove before 110- grids;120- grid Carry on the back raceway groove in pole;210- conductive layers carry on the back raceway groove;Raceway groove before 220- conductive layers.

Specific embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made Embodiment, belongs to the scope of protection of the invention.

The embodiment of the present invention provides a kind of array base palte, including GOA regions, and GOA regions are provided with thin film transistor (TFT), such as scheme Shown in 2, thin film transistor (TFT) includes setting gradually grid 11 over the substrate 10, gate insulation layer 12, active layer 13, source electrode 14 and leakage Pole 15;Array base palte also includes being successively set on source electrode 14 and drain electrode 15 passivation layer 16 and conductive layer away from the side of substrate 10 17;Wherein, orthographic projection of the orthographic projection over the substrate 10 of conductive layer 17 with active layer 13 over the substrate 10 is Chong Die.

It should be noted that first, the specific material to conductive layer 17 is not defined, and conductive layer 17 connects VGL signals, such as Shown in Fig. 2, conductive layer 17 can form conductive layer back of the body raceway groove 210 in active layer 13 and the interface of gate insulation layer 12, in active layer 13 Raceway groove 220 before the conductive layer formed with the interface of passivation layer 16.

Second, not the concrete shape to conductive layer 17 be defined, its orthographic projection with active layer 13 over the substrate 10 has Lap.

Wherein, the thickness not to conductive layer 17 is defined, and is rationally set according to process conditions.

3rd, according to the difference of semiconductor active layer material, the thin film transistor (TFT) can for amorphous silicon film transistor, Polycrystalline SiTFT, metal oxide thin-film transistor, OTFT etc..On this basis, the film is brilliant Body pipe can also be staggered, reciprocal cross shift, coplanar type or anti-coplanar type etc..

Additionally, thin film transistor (TFT) can be source electrode 14 and 15 symmetric form thin film transistor (TFT)s of drain electrode, or U-shaped film crystalline substance Body pipe.Can be a thin film transistor (TFT) as a construction of switch, or the parallel connection conduct of two or more thin film transistor (TFT) One construction of switch.

4th, substrate 10 can be flexible substrate, or glass substrate, and other substrates are can also be certainly.If lining Bottom 10 is flexible substrate, then need to set bearing substrate below flexible substrate.

The embodiment of the present invention provides a kind of array base palte, and one is set by the top of the thin film transistor (TFT) in GOA regions Layer conductive layer 17 so that conductive layer 17 forms conductive layer back of the body raceway groove 210 in active layer 13 and the interface of gate insulation layer 12, active Raceway groove 220 before the conductive layer that layer 13 is formed with the interface of passivation layer 16.Conductive layer 17 is input into low voltage signal, works as film crystal When pipe is closed, raceway groove 110 is produced before leakage current and grid that conductive layer back of the body raceway groove 210 is produced leakage current interaction and support Disappear;The leakage current that the leakage current that raceway groove 220 is produced before conductive layer is produced with grid back of the body raceway groove 120 interacts and offsets.So as to The leakage current of thin film transistor (TFT) in GOA regions can be reduced, when array base palte is applied into display device, it is ensured that display device Display effect.

In order to reduce the requirement to the pattern etch of conductive layer 17, so that technology difficulty is reduced, it is cost-effective.The present invention is implemented Example is preferred, as shown in figure 3, conductive layer 17 covers the GOA regions.

That is, one layer of conductive layer 17 is covered in whole GOA regions.

Preferably, as shown in Fig. 4 (a) and Fig. 4 (b), conductive layer 17 includes openwork part, and the openwork part is provided with leads Electric structure 18, conductive structure 18 insulate with conductive layer 17.

Wherein, conductive structure 18 and conductive layer 17 are respectively provided with conducting function, and conductive structure 18 is arranged on openwork part, therefore Conductive structure 18 and conductive layer 17 want mutually insulated, then as shown in Fig. 4 (b), the orthographic projection over the substrate 10 of conductive structure 18 falls In the range of openwork part orthographic projection over the substrate 10.

Additionally, the specific pattern to conductive structure 18 and openwork part is not defined.

When needing in the setting conductive structure 18 on passivation layer 16, the embodiment of the present invention is set by conductive layer 17 Openwork part, and conductive structure 18 is arranged on openwork part, can both avoid conductive layer 17 from being contacted with conductive structure 18 and sent out Raw short circuit, can reduce the thickness of array base palte again, make array base palte lightening.

It is further preferred that as shown in Fig. 4 (b) and Fig. 4 (c), via is provided with passivation layer 16, conductive structure 18 passes through The via is connected with drain electrode electricity 15.

When needing that test electrode is set in GOA regions, to complete during the test to thin-film transistor performance, the present invention is real The conductive structure 18 for applying the openwork part for being arranged on conductive layer 17 in example is used as test electrode, can both reduce production cost, Array base palte can be made lightening again.

It is further preferred that conductive layer 17 is transparency conducting layer.

The embodiment of the present invention is set to transparency conducting layer by by conductive layer 17, can by conductive layer 17, conductive structure 18, And the electrode layer of viewing area is formed by with a patterning processes, can reduce technique number of times, improve production efficiency.

Optionally, conductive layer 17 is metal conducting layer.

Because the resistance of metal conducting layer is smaller, therefore the embodiment of the present invention is set to metallic conduction by by conductive layer 17 Layer, can reduce power consumption, reduce production cost.

It is further preferred that the material of metal conducting layer is light screening material.

That is, conductive layer 17 is lighttight metal level.

The embodiment of the present invention is metal light screening material by the way that the material of metal conducting layer is selected, and light can be avoided to irradiate To the channel region of active layer 13, so as to reduce influence of the illumination to the channel region of active layer 13, thin film transistor (TFT) is further reduced Leakage current.

The embodiment of the present invention also provides a kind of preparation method of array base palte, and the array base palte includes GOA regions, GOA Region is formed with thin film transistor (TFT), and shown in such as Fig. 2~4 (a), thin film transistor (TFT) includes sequentially forming grid over the substrate 10 11st, gate insulation layer 12, active layer 13, source electrode 14 and drain electrode 15;The array base palte also includes being sequentially formed at source electrode 14 and leakage Passivation layer 16 and conductive layer 17 of the pole 15 away from the side of substrate 10;Wherein, the orthographic projection over the substrate 10 of conductive layer 17 with it is active The orthographic projection over the substrate 10 of layer 13 is overlapped.

It should be noted that including as shown in figure 5, forming the conductive layer 17:

S10, as shown in fig. 6, on the substrate 10 for be formed with passivation layer 16 formed membrane of conducting layer 171.

Wherein, the generation type not to membrane of conducting layer 171 is defined, and the material reasonable selection according to conductive layer 17 is led The forming method of electric layer film 171.

S20, as shown in fig. 7, on the substrate 10 for be formed with membrane of conducting layer 171 coat photoresist 191.

For photoresist 191, its species is a lot, according to its chemical reaction mechanism and development principle, can divide negative photoresist and just The property class of glue two.Form insoluble material after illumination is negative photoresist;Conversely, being insoluble to some solvents, become after illumination Positive photoresist is into soluble substance.Different types of photoresist is to that should have different mask plates.The embodiment of the present invention is not to light The species of photoresist 191 is defined.

S30, as shown in figure 8, on the basis of S20, photoresist layer 19 is formed by exposure imaging technology.

Wherein, the pattern of photoresist layer 19 is identical with the pattern of conductive layer to be formed.

S40, as shown in figure 9, on the basis of S30, performed etching to membrane of conducting layer 171, form conductive layer 17.

Wherein, membrane of conducting layer 171 is performed etching, dry etching can be used, or wet etching, can be according to leading The material of electric layer film 171 carries out reasonable selection.

S40, as shown in Figure 10, on the basis of S40, photoresist layer 19 is peeled off.

The embodiment of the present invention provides a kind of preparation method of array base palte, by the thin film transistor (TFT) in GOA regions Top forms one layer of conductive layer 17 so that conductive layer 17 forms conductive layer back of the body raceway groove in active layer 13 and the interface of gate insulation layer 12 210, the raceway groove 220 before the conductive layer that active layer 13 and the interface of passivation layer 16 are formed.Conductive layer 17 is input into low voltage signal, When thin film transistor (TFT) is closed, the leakage current of the generation of raceway groove 110 is mutual before leakage current and grid that conductive layer back of the body raceway groove 210 is produced Act on and offset;The leakage current that the leakage current that raceway groove 220 is produced before conductive layer is produced with grid back of the body raceway groove 120 interacts and supports Disappear.So as to the leakage current of thin film transistor (TFT) in GOA regions can be reduced, when array base palte is applied into display device, it is ensured that aobvious The display effect of showing device.

In order to reduce the requirement to the pattern etch of conductive layer 17, so that technology difficulty is reduced, it is cost-effective.The present invention is implemented Example is preferred, and as shown in figure 11, conductive layer 17 covers the GOA regions.

Optionally, as shown in figure 12, conductive layer 17 includes openwork part, and conductive structure 18 is formed with openwork part, leads Electric structure 18 insulate with conductive layer 17.

When needing in the formation conductive structure 18 on passivation layer 16, the embodiment of the present invention is formed by conductive layer 17 Openwork part, and conductive structure 18 is formed in openwork part, can both avoid conductive layer 17 from being contacted with conductive structure 18 And be short-circuited, the thickness of array base palte can be reduced again, make array base palte lightening.

The embodiment of the present invention also provides a kind of display device, including above-mentioned array base palte.

Wherein, above-mentioned display device can be specifically OLED display, liquid crystal display, LCD TV, DPF, hand The product or part with any display function such as machine, panel computer, navigator.

The above, specific embodiment only of the invention, but protection scope of the present invention is not limited thereto, and it is any Those familiar with the art the invention discloses technical scope in, change or replacement can be readily occurred in, should all contain Cover within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.

Claims (10)

1. a kind of array base palte, including GOA region, the GOA regions are provided with thin film transistor (TFT), it is characterised in that described thin Film transistor includes the grid, gate insulation layer, active layer, source electrode and the drain electrode that are successively set on substrate;The array base palte is also Including being successively set on the passivation layer and conductive layer of the source electrode and the drain electrode away from the substrate side;
Wherein, orthographic projection of the conductive layer orthographic projection over the substrate with the active layer over the substrate is Chong Die.
2. array base palte according to claim 1, it is characterised in that the conductive layer covers the GOA regions.
3. array base palte according to claim 1 and 2, it is characterised in that the conductive layer is metal conducting layer.
4. array base palte according to claim 3, it is characterised in that the material of the metal conducting layer is light screening material.
5. the array base palte according to claim any one of 1-4, it is characterised in that the conductive layer includes openwork part, Conductive structure is provided with the openwork part, the conductive structure insulate with the conductive layer.
6. array base palte according to claim 5, it is characterised in that via, the conduction are provided with the passivation layer Structure is electrically connected by the via with the drain electrode.
7. a kind of preparation method of array base palte, the array base palte includes GOA regions, and it is brilliant that the GOA regions are formed with film Body pipe, it is characterised in that the thin film transistor (TFT) includes the grid, gate insulation layer, active layer, the source electrode that are sequentially formed on substrate And drain electrode;The array base palte also includes being sequentially formed at the passivation layer of the source electrode and the drain electrode away from the substrate side And conductive layer;
Wherein, orthographic projection of the conductive layer orthographic projection over the substrate with the active layer over the substrate is Chong Die.
8. preparation method according to claim 7, it is characterised in that the conductive layer covers the GOA regions.
9. preparation method according to claim 7, it is characterised in that the conductive layer includes openwork part, the hollow out Conductive structure is formed with part, the conductive structure insulate with the conductive layer.
10. a kind of display device, it is characterised in that including the array base palte described in claim any one of 1-6.
CN201710002822.7A 2017-01-03 2017-01-03 Array substrate, preparation method thereof and display device CN106783887B (en)

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