CN106711226A - Silicon-based germanium nano fin-shaped structure - Google Patents

Silicon-based germanium nano fin-shaped structure Download PDF

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Publication number
CN106711226A
CN106711226A CN201611072439.0A CN201611072439A CN106711226A CN 106711226 A CN106711226 A CN 106711226A CN 201611072439 A CN201611072439 A CN 201611072439A CN 106711226 A CN106711226 A CN 106711226A
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silicon
nano
fin structure
germanium
silicon germanium
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CN201611072439.0A
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Chinese (zh)
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刘丽蓉
王勇
丁超
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东莞市广信知识产权服务有限公司
东莞华南设计创新院
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Priority to CN201611072439.0A priority Critical patent/CN106711226A/en
Publication of CN106711226A publication Critical patent/CN106711226A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669Nanowires or nanotubes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention discloses a silicon-based germanium nanowire structure. The structure comprises a silicon-based substrate, a silicon oxide groove, a silicon nitride side wall structure formed in the silicon oxide groove, a silicon-germanium/germanium material growth layer which grows in the silicon oxide groove, and a high-quality germanium channel layer which grows on a silicon-germanium layer material.

Description

一种桂基错纳未轄状结构 Sodium lauryl one kind of mistake is not exempted structure

技术领域 FIELD

[0001] 本发明属于集成电路工艺制造技术领域,具体涉及一种娃基锗纳米鳍状结构。 [0001] The present invention belongs to the technical field of integrated circuit manufacturing processes, particularly, to a baby yl nano germanium fin structure.

背景技术 Background technique

[0002] 随着CMOS技术的不断进步,通过缩小特征尺寸,M0S器件的特性不断提升。 [0002] With the advances in CMOS technology, by reducing the feature size of the device characteristics M0S rising. 但是在7 纳米技术节点以后,硅基半导体面临诸多挑战:迀移率退化、源漏穿通漏电、热载流子效应等等。 But after 7 nm technology node, a silicon semiconductor face many challenges: Gan degradation rate shift, the source and drain through the drain, the hot carrier effect and the like. 其中迁移率退化是影响集成电路速度提升的主要难点。 Where the mobility degradation is affecting the main difficulties of integrated circuits faster. 为此,新型的沟道材料和器件结构被认为是推进硅基M0S器件继续提升性能的关键。 To this end, the new channel materials and device structures are considered key components continue to improve the performance of silicon-based M0S advance. 锗材料的电子迁移率和空穴迁移率都优于硅,与硅基半导体工艺兼容性好,从而被广泛关注。 Electron mobility and hole mobility than silicon germanium material have, good compatibility with the silicon semiconductor process, so as to be widespread concern. 目前,桂基鳍状结构的M0SFET器件己经广泛应用于CMOS技术中,在硅基半导体材料中集成锗纳米鳍状结构成为实现娃基锗沟道鳍状场效应晶体管的关键。 Currently, the device has M0SFET lauryl fin structure is widely used in CMOS technology, nano germanium fin structure integrated in a silicon semiconductor material to achieve a key baby yl germanium channel fin field effect transistor.

发明内容 SUMMARY

[0003] 为解决以上问题,本发明提供了一'种桂基错纳米嬉状结构。 [0003] In order to solve the above problems, the present invention provides a 'wrong kind lauryl play nano structure. 该结构主要利用娃基上的纳米尺寸二氧化硅槽和氮化硅侧墙结构实现高深宽比的槽,再利用外延生长生长娃锗缓冲层的优势,在该二氧化桂槽中,实现桂锗材料生长,最后实现纯的锗材料生长。 Nano-sized silicon dioxide and silicon nitride sidewall groove structure on the base structure mainly implemented using baby high aspect ratio of the groove, and then take advantage of epitaxially growing a germanium buffer layer grown baby, Gui dioxide tank, to achieve Gui germanium material growth, and finally achieve pure germanium material growth. 从而达到锗纳米鳍状结构的硅基集成,为硅基锗M0SFET器件的制作提供结构和材料保障。 So as to achieve integration of the silicon germanium fin structure nanometers, provide structure and materials for the production of silicon-germanium M0SFET protection device.

[0004] 技术方案 [0004] Technical Solution

[0005] 本发明提出的一种硅基锗纳米鳍状结构,该结构具体包括: [0005] The present invention proposes a silicon-based nano germanium fin structure, which structure comprises:

[0006] 一P型掺杂的硅基衬底; [0006] a P-type doped silicon substrate;

[0007] 一150纳米宽的二氧化硅槽; [0007] a 150 nm wide grooves silica;

[0008] 一在二氧化硅槽中形成的氮化硅侧墙; [0008] In a groove formed in the silicon nitride spacers of silica;

[0009] 一在二氧化硅槽中生长的硅锗缓冲层; [0009] In a silicon germanium buffer layer grown silicon dioxide tank;

[0010] 一在硅锗缓冲层上生长的锗纳米鳍状结构。 [0010] On a silicon germanium buffer layer grown nano-germanium fin structure.

[0011] 在本技术方案中,P型掺杂的硅基半导体材料的掺杂浓度为IX l〇18cm_3。 [0011] In this aspect, the doping concentration of the P-type doped semiconductor material is silicon l〇18cm_3 IX.

[0012] 在本技术方案中,二氧化娃槽是在厚度为300纳米的二氧化娃介质上,采用ICP刻蚀方法刻蚀而成的,该二氧化硅槽的侧壁陡直度大于8〇度。 [0012] In this aspect, the groove is on a baby doll dioxide medium dioxide having a thickness of 300 nm, using ICP etching method of etching from the side wall steepness of the groove is greater than 8 silica square degrees.

[0013] 在本技术方案中,氮化硅侧墙的形成过程为:采用PECVD的方法在槽内沉积50-70 纳米厚的氮化硅介质,然后采用ICP刻蚀的方法,对生长好的介质进行刻蚀,最后在二氧化硅槽内形成30-50纳米的氮化硅侧墙。 [0013] In this aspect, the process of forming the silicon nitride spacers are: a method using the PECVD silicon nitride dielectric deposited in the grooves 50-70 nm thick, then the ICP etching method, good growth etching medium, finally formation of 30-50 nm silicon nitride spacers on silica groove.

[0014] 在本技术方案中,在二氧化桂槽内生长的桂锗缓冲层的厚度为100纳米。 [0014] In this aspect, the thickness of the buffer layer is in Guangxi Gui germanium dioxide is 100 nm vessel growth.

[0015] 在本技术方案中,在硅锗缓冲层上生长的锗材料层厚度为25〇纳米。 [0015] In this aspect, the thickness of the layer of germanium material on a buffer layer of SiGe is grown 25〇 nanometers.

[0016] 有益效果_ [0016] beneficial effects _

[0017] 本发明通过在桂基半导体材料上制备二氧化桂高深宽比槽,然后米用超咼真空化学汽相沉积的方法,首先在槽内生长硅锗缓冲层,然后生长高质量的锗鳍状结构,为解决桂基外延高质量锗材料提供了一种有效方法,本发明制作简单,成本低,与现代桂基CM0S技术兼容,适应于22纳米技术节点以后锗沟道CMOS器件的制备技术。 Germanium [0017] The present invention is prepared by Guangxi dioxide in the high aspect ratio grooves lauryl semiconductor material, and a method super rice 咼 vacuum chemical vapor deposition, a silicon germanium buffer layer is first grown in the groove, and the growth of high quality fin structures, to solve lauryl quality epitaxial germanium material provides an effective method for preparing a CMOS device of the present invention, germanium channel simple manufacture, low cost, compatible with modern technology lauryl CM0S, adapted to the 22 nm technology node after technology.

附图说明 BRIEF DESCRIPTION

[0018] 图1为本发明实施例提出的硅基锗纳米鳍状结构图。 [0018] FIG 1 nanometer silicon germanium fin structure diagram of the proposed embodiment of the present invention.

[0019] 其中,101为硅衬底,102为二氧化硅层,103为氮化硅侧墙,104为硅锗缓冲层,105 为锗鳍状结构层。 [0019] wherein a silicon substrate 101, a silicon dioxide layer 102, silicon nitride spacers 103, 104 is a silicon germanium buffer layer 105 is a layer of germanium fin structure.

[0020] 具体实施方法 [0020] DETAILED DESCRIPTION Method

[0021] 下面通过具体实施例对本发明进一步进行描述 [0021] Next, the present invention is further described by way of specific embodiments

[0022] 一种硅基锗纳米鳍状结构,该结构具体包括: [0022] A nano silicon germanium fin structure, which structure comprises:

[0023] 一8英寸P型掺杂的硅基衬底片; [0023] 8 inches a P-type doped silicon substrate sheet;

[0024] 一在该8英寸硅片上制作完成的15〇纳米宽、3〇〇纳米深的二氧化硅槽; [0024] In a finished on the 8-inch silicon wafer 15〇 nm wide, silica 3〇〇 nanometers deep grooves;

[0025] 一在该150纳米宽的二氧化硅槽中形成的两边各5〇纳米厚的氮化硅侧墙,使得二氧化硅槽的宽度缩短至5〇纳米宽; [0025] a in the silicon nitride spacers 5〇 nm thick on both sides of the silicon dioxide 150 nanometers wide groove formed such that the width of the groove is reduced to a silica 5〇 nm wide;

[0026] 一在该50纳米宽的二氧化硅槽中生长的1〇〇纳米厚的硅锗缓冲层; [0026] In a silicon germanium 50 nm wide the groove silica grown 1〇〇 nm thick buffer layer;

[0027] 一在硅锗缓冲层上生长的厚度为25〇纳米的锗纳米鳍状结构。 [0027] thickness on a silicon germanium buffer layer is grown 25〇 nm nano germanium fin structure.

Claims (6)

1. 一种硅基锗纳米鳍状结构,该结构包括: 一P型掺杂的硅基衬底; 一150纳米宽的二氧化硅槽; 一在二氧化硅槽中形成的氮化硅侧墙; 一在二氧化娃槽中生长的硅锗缓冲层; 一在硅锗缓冲层上生长的锗纳米鳍状结构。 A nano silicon germanium fin structure, the structure comprising: a P-type doped silicon substrate; a 150 nm wide grooves silica; silica nitride groove formed in a side wall; on a silicon germanium buffer layer grown nano germanium fin structure; a silicon germanium buffer layer grown baby bath dioxide.
2. 根据权利要求1所述的一种硅基锗纳米鳍状结构,其特征在于150纳米宽的二氧化硅槽的深度为300纳米。 A nano silicon germanium fin structure according to claim 1, characterized in that the depth of the 150 nm wide grooves silica 300 nm.
3. 根据权利要求1所述的一种硅基锗纳米鰭状结构,其特征在于氮化硅侧墙的厚度为30-50纳米。 A nano silicon germanium fin structure according to claim 1, characterized in that the thickness of the silicon nitride spacers 30 to 50 nanometers.
4. 根据权利要求1所述的一种硅基锗纳米鳍状结构,其特征在于二氧化硅槽内形成了一个50-90纳米宽的硅槽结构。 A nano silicon germanium fin structure according to claim 1, characterized in that the groove is formed a silicon dioxide 50-90 nm wide silicon trench structure.
5. 根据权利要求1所述的一种硅基锗纳米鳍状结构,其特征在于硅锗缓冲层的厚度为100纳米。 A nano silicon germanium fin structure according to claim 1, characterized in that the thickness of the silicon germanium buffer layer is 100 nanometers.
6. 根据权利要求1所述的一种硅基锗纳米鳍状结构,其特征在于硅锗缓冲层上生长的锗纳米鰭状结构的厚度为25〇纳米。 A nano silicon germanium fin structure according to claim 1, wherein the thickness of the nano germanium fin structure grown on a SiGe buffer layer 25〇 nanometers.
CN201611072439.0A 2016-11-29 2016-11-29 Silicon-based germanium nano fin-shaped structure CN106711226A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101150054A (en) * 2007-11-06 2008-03-26 清华大学 A method for obtaining low bit discrepancy density extension thin film via using neck down extension
CN101300663A (en) * 2005-05-17 2008-11-05 琥珀波系统公司 Lattice-mismatched semiconductor structures with reduced dislocation defect densities related methods for device fabrication
US20100072515A1 (en) * 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
CN101866834A (en) * 2009-12-11 2010-10-20 清华大学 Method for preparing SiGe material of high-Ge component by low temperature reduced pressure chemical vapor deposition and selective epitaxy
CN102142454A (en) * 2010-09-27 2011-08-03 清华大学 Semiconductor device and manufacturing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101300663A (en) * 2005-05-17 2008-11-05 琥珀波系统公司 Lattice-mismatched semiconductor structures with reduced dislocation defect densities related methods for device fabrication
CN101150054A (en) * 2007-11-06 2008-03-26 清华大学 A method for obtaining low bit discrepancy density extension thin film via using neck down extension
US20100072515A1 (en) * 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
CN101866834A (en) * 2009-12-11 2010-10-20 清华大学 Method for preparing SiGe material of high-Ge component by low temperature reduced pressure chemical vapor deposition and selective epitaxy
CN102142454A (en) * 2010-09-27 2011-08-03 清华大学 Semiconductor device and manufacturing method thereof

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