CN106706134A - RAM palette pseudo color design method - Google Patents

RAM palette pseudo color design method Download PDF

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Publication number
CN106706134A
CN106706134A CN201710006770.0A CN201710006770A CN106706134A CN 106706134 A CN106706134 A CN 106706134A CN 201710006770 A CN201710006770 A CN 201710006770A CN 106706134 A CN106706134 A CN 106706134A
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China
Prior art keywords
ram
data
pind
address
palette
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CN201710006770.0A
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Chinese (zh)
Inventor
朱勇
王君
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金陵科技学院
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Priority to CN201710006770.0A priority Critical patent/CN106706134A/en
Publication of CN106706134A publication Critical patent/CN106706134A/en

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01JMEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRA-RED, VISIBLE OR ULTRA-VIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J5/00Radiation pyrometry
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01JMEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRA-RED, VISIBLE OR ULTRA-VIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J5/00Radiation pyrometry
    • G01J2005/0077Imaging

Abstract

A RAM palette pseudo color design method relates to the video image processing technology, and specifically relates to real time infrared thermal imagery processing and realization technology; the method comprises the following steps: 1, building an infrared thermal imaging device software and hardware system; 2, editing a palette file; 3, input/output signal expression; 4, RAM palette design; 5, compiling HDL core codes; 6, designing input; 7, compiling project; 8, function simulation; 9, downloading binary system stream files in step 7 and palette data to a FPGA configuration chip. The method is suitable for any mapping relation between input data and output pseudo color, can realize shift display, and can improve display resolution.

Description

Color palette ram pseudo-colours method for designing

Technical field

The present invention relates to video image processing technology, and in particular to REAL TIME INFRARED THERMAL IMAGE thermal imagery is processed and realizes technology.

Background technology

Infrared thermal imagery is corresponding with the heat distribution on testee surface, and the infrared energy of object radiation is visualized as into puppet Coloured image, i.e., represent the different temperatures of testee with different colours.It can directly display the temperature difference of target and background Not, the target of hiding camouflage is detected, is that equipment detection and target identification provide data-interface.

Thermal imagery information is thermal infrared imager final output result, on the one hand provides measured target objective characteristics data, while Also to user's displaying visualization temperature distribution information, field assay is contributed to diagnose.With infrared sensor quality and its application The continuous improvement of demand, it is desirable to which Computer Vision channel performance is matching in thermal infrared imager.Wherein, real time data processing The requirement exported with visualization, the hard real-time synchronization especially for pixel and row field granularity is born too for processor Weight, as system Main Bottleneck.

The content of the invention

To solve above-mentioned technical problem, the present invention devises color palette ram pseudo-colours and realizes (also referred to as look-up table).We Method is applied to any mapping relations of input data and output pseudo-colours, is whether linear relationship, or cannot even use letter The situation of number relationship expression can be solved using this method.By designing color palette ram False color mapping and its converter logic Module, and user logic bit stream file is generated in Altera Quartus integrated design enviroments, it is complete in downloading to fpga chip Shown in real time into infrared thermal imagery video.

Color palette ram pseudo-colours method for designing realizes many palette pseudo-color processings by multiple paletle storages, increases Strong effect of visualization.Off-line tools edit palette can be utilized, the mapping relations of arbitrarily complicated degree are generated.

" color palette ram " logic module completes data to the basic mapping relations of color, is encapsulated as pseudo-colours user logic IP Core (Intellectual Property Core, IP core) are reused, the design that adequately protects investment.

Beneficial effect

Design False color mapping and its conversion user logic, and be achieved on FPGA, reach infrared video thermal imagery real-time Display and the effect of image enhaucament.

Color palette ram is unrelated with the complexity of mapping, and the process of tabling look-up is just as every time, and required time is also consistent , real-time processing is good.

Above-mentioned Hardware Implementation can share processor processing load as system function module, solve system core Path bottleneck.Above-mentioned user logic IP Core are embedded into SoC (System on Chip, on-chip system), can be improved and be The autgmentability and integration of system.

Brief description of the drawings

Fig. 1 color palette ram pseudo-colours design system schematic diagrames;

The many color palette ram reservoir designs figures of Fig. 2;

1. outer sensor, 2. signal conditioning circuit, 3. Video Decoder, 4.FPGA, 5. data process method module, 6. 1. data Position direct connection user logic 2. color palette ram user logic, 7.LCD displays, 8. embedded system;D0, D1 are analog signal; D2, D3 and (R, G, B) are data signals, are processed by FPGA user logics.

Specific embodiment

Color palette ram pseudo-colours of the present invention designs the sampled data after being processed shown in Fig. 1, the color with display output Corresponding relation is stored in memory in advance, then takes out coloud coding in memory by index address of data, is completed pseudo-colours and is shown Show.Mapping table in memory is palette, and changing coded data therein just can form different palettes.In palette Color can use for reference the color of the effect and image software editor burnt in visible ray, effect is generally more linear than simple Relation will get well.

Step 1:Build the software and hardware system of thermal infrared imager

First, build the present invention required for hardware, IR sensors (1), signal conditioning circuit (2), video decoding circuit (3), FPGA (4) and display output part (7) are sequentially connected, and processor CPU (8) is connected with FPGA (4).As shown in Figure 1.Ensure Thermal infrared imager collecting sensor signal, data transfer caching passage, primary module data processing function and its display output are normal.

Hardware selects AlteraIII FPGA programmable chips (also can select other model FPGA);Software is adopted With Altera Quartus Prime integrated design enviroments (or design software of selected FPGA manufacturers offer).

Step 2:Edit palette file

Designer by image editing tools, or even can obtain color card from picture, in advance editor's pseudo-colours palette File, is stored as the form of software requirement according still further to palette data form, such as mif file downloads in FPGA so that will be defeated The mapping relations for entering data and display output color are stored in RAM memory.

If color resolution is 10, display output is 24 RGBs, then palette file should have 1024 (210= 1024) data, each data encoding is each 8 (3*8=24 of R, G, B;Free Bytes are represented).The data for starting item represent relatively low Sampled value, corresponding color coding should be cool tone.Respective color coding is further filled with successively.

Step 3:Input/output signal is represented

Color palette ram module is as shown in Figure 2.Wherein main signal includes address ram PInd, palette of colors PD and many tonings Plate selection signal PAL_Sel.Sampled data ISig after treatment is connected to PInd to be tabled look-up as address ram index, will be searched RAM memory output data the D [] output for obtaining is pseudo-colours output RGB;PAL_Sel0, PAL_Sel1, PAL_Sel2 believe Number different palettes output of selection, obtains different colors mappings;There is the color that oneself is defined in each palette;Wherein Content is that user is stored in advance in RAM;Realize " data-color " conversion.

This method is many color palette ram False color mappings (Fig. 2 is by taking 3 palettes as an example), by RAM_Pal signal behaviors not Same palette output, obtains different colors mappings.There is the color that oneself is defined in each palette.Wherein content is to use Family is stored in advance in RAM (see step 2).

Input/output signal is expressed as follows:Sampled data after treatment is expressed as ISig (x, y) ∈ { ISigi-1, ISigi-2,...,ISig1,ISig0, palette address position is expressed as PInd ∈ { PIndj-1,PIndj-2,...,PInd1, PInd0, palette of colors data bit is expressed as PD ∈ { PDm-1,PDm-2,...,PD1,PD0, wherein color data is R, G, B face Colouring component is combined, and specification is related to display interface.Digit i, the address size j and output PD colour bits of signal ISig (x, y) Number m can be with difference.

Step 4:Color palette ram is designed

The design hardware selects AlteraIII FPGA programmable chips, toning is realized using RAM on wherein piece Plate, makes full use of hardware resource;Software uses supporting Altera Quartus Prime integrated design enviroments, thus from wherein LPM_RAM_IO modules realize that its parameter is LPM_WIDTH=24, and (expression data width is 24 to LPM_WIDTHAD=10, right 24 R, G, B chrominance components are answered to export;Address width is 10, correspondence addressing range 1024).

Being mapping through between treatment post-sampling data and index address is directly connected to realize that is, small data value directly generates low Bit address, big data value correspondence high address;Content therein, i.e. False color mapping content is shown in step 2;The selection of many palettes Signal can be directly selected by I/O buttons, it is also possible to after being input into through human-computer interaction interface, be given by processor.

Step 5:Write HDL core codes

If treatment post-sampling data resolution is 12, with ISig [11:0] expression, color palette ram address realm and data width Respectively 10 and 24, respectively with PInd [9:0] and PD [23:0] represent.The palette data form for wherein storing is [RRRRRRRRGGGGGGGGBBBBBBBB]。

For realize gear shift show the need for and improve display resolution, case statement point multi gear display output can be used;The One gear:By the digit of color palette ram address PInd data, to sampled data ISig as binary data, from highest order The data for taking out corresponding number are assigned to address PInd;Second gear:Binary data is pressed to sampled data ISig, by highest order Taking-up determines whether ' 1 ', if ' 1 ' then indicates spilling, color palette ram address PInd is entered as into complete ' 1 ', if not ' 1 ' takes out the data of corresponding number from a secondary high position by the digit of address PInd, is assigned to address PInd;Third gear:To adopting Sample data ISig presses binary data, and highest order or secondary high-order taking-up are determined whether into ' 1 ', if ' 1 ' then indicates spilling, Color palette ram address PInd is entered as complete ' 1 ', corresponding number is taken out by the digit of address PInd otherwise from high-order 3rd Data, be assigned to address PInd;The like, find out corresponding pseudo-colours finally according to color palette ram address PInd PD is simultaneously exported.At most can the gear number of stepping be digit number and the color palette ram address PInd of sampled data ISig The difference of digit number adds 1.

HDL code for above-mentioned input and output is as follows:

Case (n) -- stepping shows, obtains optimum resolution

0:PInd=ISig [11:2];

1:PInd=ISig [11]B"1111111111":ISig[10:1];

2:PInd=(ISig [11] | ISig [10])B"1111111111":ISig[9:0];

default:PInd=B " 0000000000 ";

endcase

Explanation:Assume that gear is divided into 3 grades in example, this method is also applied for other gear digital display circuits.When stepping shows, will 12 input data ISig [11:0] 10 address ram PInd [9 are mapped as:0], adapting to color palette ram address PInd models Enclose, find out corresponding pseudo-colours PD further according to color palette ram address PInd and exported.Using low data, can be with Display resolution higher is obtained, but to consider overflow problem.The detection of spilling is by judging whether a high position is 1, if overflowing Then output maximum B " 1111111111 " is malfunctioned with preventing from overflowing.

Note:According to practical experience, the color burnt in visible ray is used for reference during edit palette, effect of visualization generally compares It is good.

Step 6:Design input

In Altera Quartus Prime engineerings, above-mentioned input/output signal is stated, set up color palette ram module and (use RAM resources are realized on piece), input HDL code (see step 5) completes logical design.

Step 7:Compiling engineering, according to I/O interfaces configuration setting pin after inerrancy, is then adapted to whole engineering, and most Binary stream file is obtained eventually.

Step 8:Functional simulation is carried out, " color palette ram pseudo-colours " function accuracy is verified;If delay can meet system Real-time display requirements, then reach performance indications requirement.

Step 9:Download above-mentioned binary stream file and palette data and configure chip to FPGA, system is checked after restarting Whether operation is normal.

Claims (3)

1. a kind of color palette ram pseudo-colours method for designing, it is characterised in that:Specifically include following steps:
Step 1, builds the software and hardware system of thermal infrared imager:
Build software and hardware system:IR sensors (1), signal conditioning circuit (2), video decoding circuit (3), FPGA (4), Yi Jixian Show that output block (7) is sequentially connected, processor CPU (8) is connected with FPGA (4), and hardware selects AlteraIII FPGA programmable chips;Software is provided using Altera Quartus Prime integrated design enviroments or selected FPGA manufacturers Design software;
Step 2, edit palette file:
Designer can be stored as software by image editing tools, the color card that will be obtained according to palette data form It is required that form, so as to the mapping relations of input data and display output color are stored in RAM memory;
Step 3, input/output signal is represented:
Sampled data ISig after treatment is connected to PInd to be tabled look-up as address ram index, the RAM memory for obtaining will be searched Output data D [] output is pseudo-colours output RGB;The different tune of PAL_Sel0, PAL_Sel1, PAL_Sel2 signal behavior Colour table is exported, and obtains different color mappings;There is the color that oneself is defined in each palette;Wherein content is advance user Storage is in RAM;
Step 4, color palette ram design:
The design hardware selects AlteraIII FPGA programmable chips, palette is realized using RAM on wherein piece; Software uses supporting Altera Quartus Prime integrated design enviroments, thus is realized from wherein LPM_RAM_IO modules, Being mapping through between post-sampling data and index address will be processed and be directly connected to realize that the selection signal of many palettes can be by I/ O buttons are directly selected, it is also possible to after being input into through human-computer interaction interface, be given by processor;
Step 5, writes HDL core codes:
When stepping shows, the sampled data after treatment is mapped as address ram, to adapt to color palette ram address PInd scopes, Corresponding pseudo-colours PD is found out further according to color palette ram address PInd and exported, using low data, can obtain Display resolution higher, the detection of spilling is that, by judging whether a high position is 1, if overflowing, color palette ram address PInd is assigned It is worth for complete ' 1 ' to prevent from overflowing error;
Step 6:Design input:
In Altera Quartus Prime engineerings, above-mentioned input/output signal is stated, set up the input of color palette ram module HDL code, completes logical design;
Step 7:Compiling engineering, according to I/O interfaces configuration setting pin after inerrancy, is then adapted to whole engineering, and finally obtain Obtain binary stream file;
Step 8:Functional simulation is carried out, " color palette ram pseudo-colours " function accuracy is verified;If it is real-time that delay can meet system Display requires, then reaches performance indications and require;
Step 9:Binary stream file and palette data in download step 7 configure chip to FPGA, are checked after restarting and are Whether system operation is normal.
2. a kind of color palette ram pseudo-colours method for designing, it is characterised in that:According to claim 1, color palette ram, can be with It is two or more, there is the color that oneself is defined in each palette, wherein content is that user is stored in advance in
In RAM;Its annexation is:Two or more RAM data buses correspondence position is linked together;By toning Plate selection signal PAL_Sel carries out piece choosing, the sampled data ISig after treatment is connected to PInd and is looked into as address ram index Table, will search RAM memory output data the D [] output for obtaining and is pseudo-colours output RGB.
3. a kind of color palette ram pseudo-colours method for designing, it is characterised in that:Writing according to step 5 in claim 1 HDL core codes, its specific algorithm is:For realize gear shift show the need for and improve display resolution, case statement can be used Divide multi gear display output;First gear:By the digit of color palette ram address PInd data, sampled data ISig is entered as two Data processed, the data that corresponding number is taken out from highest order are assigned to address PInd;Second gear:Two are pressed to sampled data ISig Binary data, highest order is taken out and determines whether ' 1 ', if ' 1 ' then indicates spilling, color palette ram address PInd is assigned It is complete ' 1 ' to be worth, if not ' 1 ' takes out the data of corresponding number from a secondary high position by the digit of address PInd, is assigned to address PInd;Third gear:Binary data is pressed to sampled data ISig, highest order or secondary high-order taking-up are determined whether ' 1 ', if For ' 1 ' then indicates spilling, color palette ram address PInd is entered as complete ' 1 ', otherwise by address PInd from high-order 3rd Digit take out corresponding number data, be assigned to address PInd;The like, looked into finally according to color palette ram address PInd Find out corresponding pseudo-colours PD and exported;At most can stepping gear number for sampled data ISig digit number with The difference of the digit number of color palette ram address PInd adds 1.
CN201710006770.0A 2017-01-05 2017-01-05 RAM palette pseudo color design method CN106706134A (en)

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