CN106685788B - The chip implementing method of PVLAN under stacking mode - Google Patents
The chip implementing method of PVLAN under stacking mode Download PDFInfo
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- CN106685788B CN106685788B CN201710017192.0A CN201710017192A CN106685788B CN 106685788 B CN106685788 B CN 106685788B CN 201710017192 A CN201710017192 A CN 201710017192A CN 106685788 B CN106685788 B CN 106685788B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/46—Interconnection of networks
- H04L12/4641—Virtual LANs, VLANs, e.g. virtual private networks [VPN]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/46—Interconnection of networks
- H04L12/4641—Virtual LANs, VLANs, e.g. virtual private networks [VPN]
- H04L12/4675—Dynamic sharing of VLAN information amongst network nodes
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Abstract
Present invention discloses the chip implementing methods of PVLAN under stacking mode a kind of, by the corresponding VLAN of port assignment in stacked chips, goes out the first isolation label in direction, enters the second isolation label in direction, and the forward rule of PVLAN is configured in stacked chips, after chip receives message, message is handled according to the forward rule of PVLAN, it is communicated according to the attribute of PVLAN, the information of PVLAN is transmitted across chip.The present invention greatly extends the application range of PVLAN technology so that PVLAN using more flexible and efficient.
Description
Technical field
The present invention relates to a kind of PVLAN (Private VLAN, particular virtual local area network) technologies, more particularly, to a kind of heap
The chip implementing method of PVLAN under folded mode.
Background technique
Stack Technology is the common technology of the ECP Extended Capabilities Port on Ethernet switch, can be the other stacking of switch-level,
It is also possible to the stacking of exchange chip rank.It participates in the interchanger (exchange chip) stacked and passes through ring (ring) type, tree (tree)
The Topology connections such as type, fullmesh (full mesh) type are considered as an equipment in management layer.
PVLAN is that one kind is effectively distributed for solving VLAN in carrier network (virtual LAN) resource, rationally utilized
Requirement technology, the basic principle of the technology is that VLAN is assigned to two different attributes, is Primary VLAN (main respectively
VLAN, the VLAN communicated with Operation Network) and Secondary VLAN (auxiliary vlan, the VLAN communicated with user), wherein
Primary VLAN operatable object quotient's network, and Secondary VLAN user oriented accesses network.PVLAN technology is solving to lead to
Believe safety problem, prevent broadcast storm, has stronger advantage in terms of saving IP address.
Secondary VLAN forwards isolation rule different according to L2 (data link layer), be divided into Isolated VLAN (every
From VLAN) and Community VLAN (polymerization VLAN) two classes.The port for including in Secondary VLAN is referred to as Host
Port (host port), according to the two types of Secondary VLAN be divided into again Isolated Port (isolated port) and
Community Port (aggregation port).The port of operatable object quotient network is referred to as Promiscuous in Primary VLAN
Port (Hybrid port).
It following is a brief introduction of the principle of lower PVLAN:
As shown in Figure 1, A, B indicate Isolated devices (xegregating unit), C, D, E indicate Community
Devices (polymerization unit), R indicate Router or other L4-L7device (router or other L4-L7 layers of equipment),
I1, i2 indicate Isolated ports (isolated port), and c1, c2, c3 indicate Community ports (aggregation port), p1 table
Showing Promiscuous port (Hybrid port), t1 indicates Inter-switch link port, a VLAN-aware port,
Trunk port (link exchange inner port, a kind of support vlan port, transmission port).P1 mouthfuls belong to up going port, operatable object
Quotient's network, i1, i2, c1, c2, c3 belong to down going port, and user oriented accesses network.
It should be understood that
Only one primary VLAN in 1: one private VLAN of Note, can there is multiple secondary
VLANs；
The communication authority according to sending port in Fig. 2 is broadcasted in Note 2:PVLAN to forward, Fig. 2 is above-mentioned various
Intercommunity requirement between port；Wherein, as shown in connection with fig. 3, two layers between Isolated port and Promiscuous port
Intercommunication；Two layers of not intercommunication between Isolated port；Double layer intercommunication between same group of Community port；Difference group
Two layers of not intercommunication between Community port；Double layer intercommunication between Community port and Promiscuous port.
But the technical solution of PVLAN is realized not under stacking mode at this stage.
Summary of the invention
It is an object of the invention to overcome the deficiencies of existing technologies, the chip for providing PVLAN under a kind of stacking mode is realized
Method, to solve the problems, such as to support the technology vacancy of PVLAN under chip stacking mode at this stage.
To achieve the above object, the following technical solutions are proposed by the present invention: the chip realization side of PVLAN under a kind of stacking mode
Method, comprising:
S1, to the corresponding VLAN of port assignment of stacked chips, to the port assignment outlet for participating in PVLAN in stacked chips
The first isolation label in mouth direction and the second isolation label of the direction of incoming port；
S2 configures the forward rule of PVLAN in stacked chips；
S3, message enter stacked chips port, and chip records the second isolation label of the port, and message is in chip
It inside tables look-up to obtain exit port information, message carries the chip where the second isolation label arrival exit port；
S4, the chip analytic message where exit port obtain the exit port information, and then obtain described the of exit port
One isolation label；
S5, the chip where exit port are handled message according to the forward rule of the PVLAN.
The present invention also provides another technical solutions: the chip implementing method of PVLAN under a kind of stacking mode, packet
It includes:
S1 ' participates in heap to the corresponding VLAN of port assignment of stacked chips, and to each chip distribution of stacked chips
The port of the folded port all chip PVLAN goes out the first isolation label in direction and port enters the second of direction and label is isolated；
S2 ' configures the forward rule of PVLAN in stacked chips；
S3 ', message enter stacked chips port, and chip records the second isolation label of the port, and chip is at this
Inbound port analytic message simultaneously searches forwarding table, obtains exit port, and then obtains the first isolation label of outgoing packet；
S4 ', message in inbound port judge whether directly to lose message according to the forward rule of the PVLAN in the chip
It abandons, if not abandoning, message reaches the chip where exit port according to the exit port information；
S5 ', the chip analytic message where exit port obtain the exit port information, are advised according to the forwarding of the PVLAN
Then, message is forwarded processing.
Preferably, each chip in stacking system can individually support pvlan feature.
Preferably, in step S1 and S1 ', the corresponding VLAN of port assignment to stacked chips includes:
Primary vlan is distributed to Hybrid port；
Auxiliary vlan 1 is distributed to isolated port；
2~auxiliary vlan of auxiliary vlan (N+1) is distributed to N group aggregation port, wherein N is the integer more than or equal to 1.
Preferably, it is described first isolation label and second isolation label include judge port whether be aggregation port mark
Number ID, whether be Hybrid port label ID, whether be isolated port label ID.
Preferably, the forward rule of the PVLAN includes:
If inbound port is Hybrid port, it is forwarded according to the MAC Address of message；
If inbound port is aggregation port or isolated port, according to the first of exit port the isolation label information judgement outlet
Attribute carries out respective handling to message.
Preferably, if inbound port is aggregation port, the attribute of outlet is judged according to the first of exit port the isolation label information,
Carrying out respective handling to message includes:
If exit port is isolated port, packet loss；
If exit port is Hybrid port, VLAN in message is adjusted to primary vlan, is turned according to the MAC Address of message
Hair；
If exit port is aggregation port, judge first isolation label and second isolation label in label ID whether phase
Together, respective handling is carried out to message according to estimate of situation.Specifically, if they are the same, then it is forwarded according to the MAC Address of message,
Otherwise, packet loss.
Preferably, if inbound port is isolated port, the attribute of outlet is judged according to the first of exit port the isolation label information,
Carrying out respective handling to message includes:
If exit port is isolated port, packet loss；
If exit port is Hybrid port, VLAN in message is adjusted to primary vlan, is turned according to the MAC Address of message
Hair；
If exit port is aggregation port, packet loss.
Preferably, in step S3, message and Data within the chip structure carry the second isolation label and reach exit port
The chip at place.
Preferably, message searches forwarding table, obtains outlet message in the chip according at least to the mac address information of itself
Breath.
Compared with prior art, of the invention:
1, realize that PVLAN technology, the information of PVLAN can be transmitted across chip in stacking system, so that
The application of PVLAN technology is not limited only to the application places connected at single device (single-chip), and the field used is stacked in multiple chips
The function that PVLAN can be still supported under scape, greatly extends the application range of PVLAN technology, so that the application of PVLAN is more
Add flexible and efficient.
2, use of the PVLAN in stacking system reduces number of devices, reduces customer using cost.
Detailed description of the invention
Fig. 1 is the schematic illustration of PVLAN；
Fig. 2 and Fig. 3 is the intercommunity schematic illustration between the port PVLAN；
Fig. 4 is the schematic illustration of PVLAN under stacking mode of the present invention；
Fig. 5 is the flow diagram of the chip implementing method of PVLAN under 1 stacking mode of the embodiment of the present invention.
Specific embodiment
Below in conjunction with attached drawing of the invention, clear, complete description is carried out to the technical solution of the embodiment of the present invention.
The chip implementing method of PVLANPVLAN under a kind of disclosed stacking mode, by stacking system
Chip port is configured, to realize application of the PVLAN technology in stacking system.
In conjunction with shown in Fig. 4 and Fig. 5, the chip of PVLANPVLAN under a kind of revealed stacking mode of the embodiment of the present invention 1
Implementation method, comprising the following steps:
S1, to the corresponding VLAN of port assignment of stacked chips, and to the port assignment end of stacked chips participation PVLAN
Mouth goes out the first isolation label in direction and port enters the second of direction and label is isolated.
In order to realize that stacking system can support PVLAN technology, the present invention to carry out corresponding configuration to stacking system, including
The configuration of port vlan, port go out the entering direction for the first isolation label of identification port type and port and be used for of direction
Second isolation label of identification port type.
It specifically, is primary vlan respectively by PVLAN technical principle it is found that PVLAN assigns VLAN to two different attributes
And auxiliary vlan, auxiliary vlan are divided into isolated vlan and polymerization two class of VLAN again.Wherein, operatable object quotient network in primary vlan
Port is referred to as Hybrid port, and isolated vlan corresponding with polymerization VLAN is isolated port and aggregation port.Therefore, here, give
The corresponding VLAN of the port assignment of stacked chips includes:
Primary vlan is distributed to Hybrid port；
Auxiliary vlan 1 is distributed to isolated port；
2~auxiliary vlan of auxiliary vlan (N+1) is distributed to N group aggregation port, wherein N is the integer more than or equal to 1.
Go out the first isolation label in direction, the first isolation here to the port assignment port that stacked chips participate in PVLAN
Label include message go out direction port whether be aggregation port label ID, whether be Hybrid port label ID, whether be
The label ID of isolated port.
Likewise, the port assignment port for participating in PVLAN to stacked chips enters the second isolation label in direction, here the
Two isolation labels include message go out direction port whether be aggregation port label ID, whether be Hybrid port label ID,
Whether be isolated port label ID.
S2 configures the forward rule of PVLAN in stacked chips.
In order to realize that stacking system can support PVLAN technology, the present invention also to carry out the forwarding rule of PVLAN to stacking system
The forward rule of configuration then, PVLAN is matched according to the second isolation label of the first of exit port the isolation label and inbound port
It sets, specifically, the forward rule of PVLAN includes:
If inbound port is Hybrid port, it is forwarded according to the MAC Address of message；
If inbound port is aggregation port or isolated port, according to the first of exit port the isolation label information judgement outlet
Attribute carries out respective handling to message.
I.e. the port of message entrance is if it is Hybrid port, then regardless of the attribute of its exit port, directly according to the MAC of message
Address is forwarded；If inbound port is aggregation port or isolated port, the second isolation label information in conjunction with inbound port is needed
Comprehensive descision is carried out with the first isolation label information of exit port, and then corresponding processing is made to message.
Specifically, when inbound port is aggregation port, the forward rule of the PVLAN of configuration is specifically included:
If exit port is isolated port, packet loss.
I.e. when inbound port is aggregation port, and exit port is isolated port, then dropping packets.
If exit port is Hybrid port, VLAN in message is adjusted to primary vlan, is turned according to the MAC Address of message
Hair.
I.e. when inbound port is aggregation port, and exit port is Hybrid port, the VLAN for needing to edit message is adjusted to lead
VLAN is forwarded according to the MAC Address of message.
If exit port is aggregation port, judge first isolation label and second isolation label in label ID whether phase
Together, if they are the same, then it is forwarded according to the MAC Address of message, otherwise, packet loss.
Here judge whether the label ID in the first isolation label and the second isolation label is identical, that is, judges inbound port and go out
Whether in the same aggregation group, identical is then to be forwarded according to the MAC Address of message in same aggregation group for port, otherwise,
Packet loss.
When inbound port is isolated port, the forward rule of the PVLAN of configuration is specifically included:
If exit port is isolated port, packet loss.
If exit port is Hybrid port, VLAN in message is adjusted to primary vlan, is turned according to the MAC Address of message
Hair.
If exit port is aggregation port, packet loss.
S3, message enter stacked chips port, and chip records the second isolation label of the port, and message is in chip
It inside tables look-up to obtain exit port information, message carries the chip where the second isolation label arrival exit port.
Wherein, message searches forwarding table, obtains outlet message in the chip according to information such as MAC Address in its own
Breath (because being stacking system, it will be assumed that exit port and inbound port be not in same chip), later, message and chip are included
The internal structure added carries the chip where the second isolation label arrival exit port.
S4, the chip analytic message where exit port obtain the exit port information, and then obtain described the of exit port
One isolation label.
Wherein, the chip analytic message where exit port and its internal structure, obtain exit port information.
S5, the chip where exit port are handled message according to the forward rule of the PVLAN.
Chip i.e. where exit port is according to the first obtained isolation label and the second isolation label, according to turning for PVLAN
Message is carried out discarding or forward process by hair rule.The forward rule of PVLAN, which is specifically shown in, to be described above, and which is not described herein again.
The chip implementing method of PVLANPVLAN under a kind of revealed stacking mode of the embodiment of the present invention 2, including it is following
Step:
S1 ' participates in heap to the corresponding VLAN of port assignment of stacked chips, and to each chip distribution of stacked chips
The port of the folded port all chip PVLAN goes out the first isolation label in direction and port enters the second of direction and label is isolated；
S2 ' configures the forward rule of PVLAN in stacked chips；
S3 ', message enter stacked chips port, the first isolation label of chip recorded message, and chip enters end at this
Mouth analytic message simultaneously searches forwarding table, obtains exit port, and then obtains the first isolation label of outgoing packet；
S4 ', the chip where inbound port judge whether according to the forward rule of the PVLAN directly by packet loss, if
It does not abandon, then message reaches the chip where exit port according to the exit port information in the chip；
S5 ', the chip analytic message where exit port obtain the exit port information, are advised according to the forwarding of the PVLAN
Then, message is forwarded processing.
Embodiment 2 the difference from embodiment 1 is that, using global configuration port go out direction be isolated label information, also
It is the isolation label information that each chip for participating in stacking has the port for participating in all chips stacked to go out direction.Entering in this way
Mouth chip can execute the PVLAN forward rule inspection of port isolation realization, it is known that whether dropping packets just exist if abandoned
Entrance chip executes discarding movement, executes discarding without using exit port chip, can reduce the end polymerization (stacking) in this way
The bandwidth pressure of mouth.
The configuration and above-mentioned implementation of the forward rule of the first isolation label, the second isolation label and PVLAN in the program
Identical in example 1, the processing to message is also to perform corresponding processing according to the forward rule of PVLAN, and concrete configuration content is shown in
It is described above, which is not described herein again.
The present invention is realized in the case where multiple chips stack, and enables across the chip progress of the information of PVLAN
Transmission, multiple ports of multiple chips can belong to a PVLAN simultaneously, be communicated according to the attribute of PVLAN.
Technology contents and technical characteristic of the invention have revealed that as above, however those skilled in the art still may base
Make various replacements and modification without departing substantially from spirit of that invention, therefore, the scope of the present invention in teachings of the present invention and announcement
It should be not limited to the revealed content of embodiment, and should include various without departing substantially from replacement and modification of the invention, and be this patent Shen
Please claim covered.
Claims (8)
1. the chip implementing method of PVLAN under a kind of stacking mode, which is characterized in that the described method includes:
S1, to the corresponding VLAN of port assignment of stacked chips, and the port assignment port for participating in PVLAN to stacked chips goes out
The first isolation label in direction and port enter the second isolation label in direction,
In step S1, the corresponding VLAN of port assignment to stacked chips includes:
Primary vlan is distributed to Hybrid port；
Auxiliary vlan 1 is distributed to isolated port；
2~auxiliary vlan of auxiliary vlan (N+1) is distributed to N group aggregation port, wherein N is the integer more than or equal to 1,
It is described first isolation label and second isolation label include judge port whether be aggregation port label ID, whether be
The label ID of Hybrid port, whether be isolated port label ID；
S2 configures the forward rule of PVLAN in stacked chips；
S3, message enter stacked chips port, and chip records the second isolation label of the port, and message is looked into the chip
Table obtains exit port information, and message carries the chip where the second isolation label arrival exit port；
S4, the chip analytic message where exit port obtain the exit port information, so obtain described the first of exit port every
From label；
S5, the chip where exit port are handled message according to the forward rule of the PVLAN.
2. the chip implementing method of PVLAN under stacking mode according to claim 1, which is characterized in that the PVLAN's
Forward rule includes:
If inbound port is Hybrid port, it is forwarded according to the MAC Address of message；
If inbound port is aggregation port or isolated port, according to the category of the first of exit port the isolation label information judgement outlet
Property, respective handling is carried out to message.
3. the chip implementing method of PVLAN under stacking mode according to claim 2, which is characterized in that if inbound port is
Aggregation port, according to the attribute of the first of exit port the isolation label information judgement outlet, carrying out respective handling to message includes:
If exit port is isolated port, packet loss；
If exit port is Hybrid port, VLAN in message is adjusted to primary vlan, is forwarded according to the MAC Address of message；
If exit port is aggregation port, judge whether the label ID in the first isolation label and the second isolation label is identical, if
It is identical, then it is forwarded according to the MAC Address of message, otherwise, packet loss.
4. the chip implementing method of PVLAN under stacking mode according to claim 2, which is characterized in that if inbound port is
Isolated port, according to the attribute of the first of exit port the isolation label information judgement outlet, carrying out respective handling to message includes:
If exit port is isolated port, packet loss；
If exit port is Hybrid port, VLAN in message is adjusted to primary vlan, is forwarded according to the MAC Address of message；
If exit port is aggregation port, packet loss.
5. the chip implementing method of PVLAN under a kind of stacking mode characterized by comprising
S1 ' participates in stacking to the corresponding VLAN of port assignment of stacked chips, and to each chip distribution of stacked chips
The port of the port all chip PVLAN goes out the first isolation label in direction and port enters the second of direction and label is isolated,
In step S1 ', the corresponding VLAN of port assignment to stacked chips includes:
Primary vlan is distributed to Hybrid port；
Auxiliary vlan 1 is distributed to isolated port；
2~auxiliary vlan of auxiliary vlan (N+1) is distributed to N group aggregation port, wherein N is the integer more than or equal to 1,
It is described first isolation label and second isolation label include judge port whether be aggregation port label ID, whether be
The label ID of Hybrid port, whether be isolated port label ID；
S2 ' configures the forward rule of PVLAN in stacked chips；
S3 ', message enter stacked chips port, and chip records the second isolation label of the port, and chip enters end at this
Mouth analytic message simultaneously searches forwarding table, obtains exit port, and then obtains the first isolation label of outgoing packet；
S4 ', message judge whether directly according to the forward rule of the PVLAN by packet loss in the chip where inbound port,
If not abandoning, message tables look-up to obtain exit port information and according to where exit port information arrival exit port in the chip
Chip；
S5 ', the chip analytic message where exit port obtain the exit port information, according to the forward rule of the PVLAN,
Message is forwarded processing.
6. the chip implementing method of PVLAN under stacking mode according to claim 5, which is characterized in that the PVLAN's
Forward rule includes:
If inbound port is Hybrid port, it is forwarded according to the MAC Address of message；
If inbound port is aggregation port or isolated port, according to the category of the first of exit port the isolation label information judgement outlet
Property, respective handling is carried out to message.
7. the chip implementing method of PVLAN under stacking mode according to claim 6, which is characterized in that if inbound port is
Aggregation port, according to the attribute of the first of exit port the isolation label information judgement outlet, carrying out respective handling to message includes:
If exit port is isolated port, packet loss；
If exit port is Hybrid port, VLAN in message is adjusted to primary vlan, is forwarded according to the MAC Address of message；
If exit port is aggregation port, judge whether the label ID in the first isolation label and the second isolation label is identical, if
It is identical, then it is forwarded according to the MAC Address of message, otherwise, packet loss.
8. the chip implementing method of PVLAN under stacking mode according to claim 6, which is characterized in that if inbound port is
Isolated port, according to the attribute of the first of exit port the isolation label information judgement outlet, carrying out respective handling to message includes:
If exit port is isolated port, packet loss；
If exit port is Hybrid port, VLAN in message is adjusted to primary vlan, is forwarded according to the MAC Address of message；
If exit port is aggregation port, packet loss.
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| CN114244920B (en) * | 2021-12-29 | 2024-02-09 | 苏州盛科通信股份有限公司 | New and old chip stacking head compatible method and system and chip |
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| CN1777150A (en) * | 2005-12-05 | 2006-05-24 | 杭州华为三康技术有限公司 | Method for realizing user-isolated virtual LAN and its network device |
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| CN103457862A (en) * | 2013-09-06 | 2013-12-18 | 杭州华三通信技术有限公司 | Three-layer multicast achieving method in software longitudinal stacking system and equipment |
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