CN106649004B - A kind of data acquisition device and self-diagnosing method based on PC104 bus - Google Patents
A kind of data acquisition device and self-diagnosing method based on PC104 bus Download PDFInfo
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- CN106649004B CN106649004B CN201610853408.2A CN201610853408A CN106649004B CN 106649004 B CN106649004 B CN 106649004B CN 201610853408 A CN201610853408 A CN 201610853408A CN 106649004 B CN106649004 B CN 106649004B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
Abstract
The invention discloses a kind of data acquisition device and self-diagnosing method based on PC104 bus, device includes main processing block, communication interface module and PC104 bus, the main processing block is connect by PC104 bus with communication interface module, and the main processing block includes host CPU, CPLD and the first latch；Pass through address bus, data/address bus, control bus and the connection of the first GPIO bus between the host CPU and the CPLD, first latch is connect with the address bus and data/address bus respectively, is connected between the host CPU and first latch by the 2nd GPIO bus；The CPLD is connect with the PC104 bus.The present invention has input cost small, it can be achieved that main processing block is isolated with the controllable of PC104 bus, can accurately carry out depth self-diagnosis, debugging, easy to maintain, produces, the advantages such as maintenance cost is low.
Description
Technical field
The present invention relates to data collecting fields more particularly to a kind of data based on PC104 bus based on PC104 bus
Acquisition device and self-diagnosing method.
Background technique
Data acquisition device currently based on PC104 bus is very widely used, and data collection system is generally by main
The communication interface modules for managing module and multiple peripheral expansions is constituted, as shown in Figure 1, main processing block is by PC104 bus and respectively
The communication of a peripheral expansion communication interface modules obtains data, the other end of each communication interface modules by all kinds of communication chips with
Peripheral equipment is communicated, to realize the theory of distributed data acquisition, centralized data processing.Current this equipment exists
When normal operating conditions, external interface data can be correctly acquired, and effective data analysis and state are carried out to external equipment
Diagnosis, but have a defect that, without the effective self-diagnosing method of complete set of equipment itself, when some is communicated in bus
After interface module hardware goes wrong, the host CPU in main processing block can not be identified by PC104 bus data collected
Validity, the diagnostic result of mistake may be led to due to collecting invalid data, or even maintenance personnel is given to mislead, seriously
The case where very huge economic loss may be caused due to wrong diagnosis.
Mainly there may be the problem of are as follows: 1, go wrong when the address of some communication interface modules, data latches device
When, so that data/address bus or a certain line of address bus or multi-thread level are dragged down or drawn high always by force, lead to host CPU
The bus data read is invalid data, but host CPU can not but identify the validity of data, if extended simultaneously in bus
Multiple communication interface modules then also influence the data communication of other normal communication interface modules, and can be by this bus
Problem is brought directly to inside host CPU.2, it when software, the hardware of the decoder control section of communication interface modules go wrong, leads
The data invalid read is caused, and host CPU can not identify the ineffectivity.3, since the dual port RAM device of communication interface modules goes out
Existing problem, the data invalid for causing host CPU to be accessed, and host CPU can not identify the ineffectivity.4, communication interface modules and outer
Since data invalid phenomenon occur in interference or other reasons when peripheral equipment communicates, and host CPU can not position concrete reason.
Existing apparatus self-test self diagnosis is solved, the validity of data can in time, be accurately adjudicated, find fault point in time
And handle in time, device availability and reliability are improved, device intelligent diagnostics level is improved, becomes current difficulty urgently to be solved
Topic.
Summary of the invention
The technical problem to be solved in the present invention is that, for technical problem of the existing technology, the present invention provides one
Kind of input cost is small, it can be achieved that main processing block is isolated with the controllable of PC104 bus, can accurately carry out depth self-diagnosis, tune
Examination, easy to maintain, production, the low data acquisition device and self-diagnosing method based on PC104 bus of maintenance cost.
In order to solve the above technical problems, technical solution proposed by the present invention are as follows: a kind of data acquisition based on PC104 bus
Device, including main processing block, communication interface module and PC104 bus, the main processing block pass through PC104 bus and communication
Interface module connection, the main processing block includes host CPU, CPLD(complex programmable controller) and the first latch；It is described
It is connected between host CPU and the CPLD by address bus, data/address bus, control bus and the first GPIO bus, described first
Latch is connect with the address bus and data/address bus respectively, passes through second between the host CPU and first latch
The connection of GPIO bus；The CPLD is connect with the PC104 bus.
As a further improvement of the present invention, the first driving power, the data/address bus are provided on the address bus
It is provided with the second driving power.
It as a further improvement of the present invention, further include the second latch, third latch and the 4th latch；Describedly
Location bus is also connect with second latch, and second latch is connect with PC104 bus；The data/address bus also with institute
The connection of third latch is stated, the third latch is connect with PC104 bus；The CPLD by the 4th latch with
The connection of PC104 bus；The CPLD is connect with second latch, third latch and the 4th latch respectively.
A kind of self-diagnosing method of the data acquisition device based on PC104 bus, including main processing block address bus is certainly
Inspection；Specific steps include:
S1.1 host CPU controls the conveying that the first latch allows address bus to data/address bus；
S1.2. host CPU control CPLD is in non-enabled state；
S1.3. host CPU executes data reading operation by PC104 bus, judges that the data of read data and address bus are
It is no consistent, unanimously then determine that address bus is normal, otherwise determines that address bus is abnormal；
S1.4. when the address bus exception, by the number of read data described in bit bit comparison and the address bus
According to whether consistent, determine that the corresponding address bus of inconsistent bit is abnormal.
It as a further improvement of the present invention, further include CPLD self-test；Its specific steps includes:
S2.1. host CPU reads the life signal of CPLD by the first GPIO bus, if life signal situation of change is just
Often, go to step S2.2, otherwise jumps to step S2.3；
S2.2. host CPU by PC104 bus read CPLD life signal, if life signal situation of change normally if
Determine that CPLD self-test is normal, otherwise determines that CPLD is abnormal to the connection between PC104 bus；
S2.3. host CPU by PC104 bus read CPLD life signal, if life signal situation of change normally if
Determining that CPLD software is normal, and CPLD is normal to the connection between PC104 bus, PC104 bus can be accessed normally, but the
One GPIO bus connect exception with CPLD, otherwise determines that CPLD self-test is abnormal.
It as a further improvement of the present invention, further include the PC104 bus self-test of main processing block side；Its specific steps packet
It includes:
S3.1. preset first self-inspection data is written to CPLD by PC104 bus in host CPU, then reads, judges institute
Whether write-in and the data read are consistent, and unanimously then go to step S3.2, otherwise determine that main processing block side PC104 bus is different
Often；
S3.2. preset second self-inspection data is written to CPLD by PC104 bus in host CPU, then reads, judges institute
Whether write-in and the data read are consistent, unanimously then determine that main processing block side PC104 bus is normal, otherwise determine main process task mould
Block side PC104 bus is abnormal.
As a further improvement of the present invention, first self-inspection data is 0x5A, and second self-inspection data is 0xA5.
It as a further improvement of the present invention, further include communication interface modules self-test；Its specific steps includes:
S4.1. the life signal that host CPU reads communication interface modules jumps to step if the life signal is normal
Otherwise rapid S4.2 judges that the communication interface modules self-test is abnormal；
S4.2. self-test mark is written to the command register of the communication interface modules in host CPU；
S4.3. host CPU reads the value of the response register of the communication interface modules, when described value is to respond mark then
Go to step S4.4, otherwise judges that communication interface modules self-test is abnormal；
S4.4. successively preset self-inspection data is written to each data storage area of the communication interface modules in host CPU, and
Data are read from each data storage area of the communication interface modules, when the reading data and the preset self-checking number being written
According to consistent, then judge that communication interface modules is normal, otherwise determines that the data storage area is abnormal.
As a further improvement of the present invention, the preset self-inspection data includes 0x00,0x5A, 0xA5.
Compared with the prior art, the advantages of the present invention are as follows:
1, the present invention only needs to improve the hardware circuit of main processing block, does not need whole redesign, input cost
It is small.
2, present invention design data bus, address bus, control bus and second between host CPU and communication interface modules
Latch, third latch and the 4th latch；By the enabled and direction of CPLD control latch, can be realized host CPU side from
Communication interface modules acquires data, and can realize that the side bus between host CPU and communication interface modules is controllably isolated.
3, the present invention is connected between host CPU and CPLD by the first GPIO bus, and host CPU is enabled to pass through binary channels
The state of real-time monitoring CPLD；It is capable of the degree whether software of Accurate Diagnosis to CPLD are write with a brush dipped in Chinese ink, especially to production, debugging, dimension
It repairs personnel to provide conveniently, saves production, the maintenance cost of product.
4, the present invention designs the first latch between the data/address bus and address bus of host CPU side, by the GPIO of host CPU
Its enabled and transmission direction is directly controlled, the self-test to address bus may be implemented.
5, the present invention passes through CPLD programming Control, it can be achieved that management to PC104 control bus.
6, for the present invention by arranging self-detection mechanism in the Software Interface Design of host CPU and communication interface modules, host CPU can
Intelligent measurement and diagnosis are carried out to communication interface modules at any time by software protocol interface, can accomplish the software of communication interface modules
The diagnostic routine whether write with a brush dipped in Chinese ink, the also detectable bad block situation of storage unit.
Detailed description of the invention
Fig. 1 is available data acquisition device PC104 bus structures schematic diagram.
Fig. 2 is data acquisition device structural schematic diagram one of the present invention.
Fig. 3 is data acquisition device structural schematic diagram two of the present invention.
Fig. 4 is main processing block address bus self-test flow diagram of the present invention.
Fig. 5 is CPLD self-test self-test flow diagram of the present invention.
Fig. 6 is PC104 bus self-test flow diagram in main processing block side of the present invention.
Fig. 7 is communication interface modules self-test flow diagram of the present invention.
Specific embodiment
Below in conjunction with Figure of description and specific preferred embodiment, the invention will be further described, but not therefore and
It limits the scope of the invention.
Embodiment one:
As shown in Fig. 2, the data acquisition device based on PC104 bus of the present embodiment, including main processing block, communication connect
Mouth mold block and PC104 bus, main processing block are connect by PC104 bus with communication interface module, and main processing block includes master
CPU, CPLD and the first latch；Pass through address bus, data/address bus, control bus and the first GPIO between host CPU and CPLD
Bus connection, the first latch are connect with address bus and data/address bus respectively, pass through second between host CPU and the first latch
The connection of GPIO bus；CPLD is connect with PC104 bus.The first driving power is provided on address bus, data/address bus is provided with
Second driving power.First driving power and the second driving power are 5V.
As shown in figure 4, the self-diagnosing method of the data acquisition device based on PC104 bus of the present embodiment, including main place
Manage the self-test of module's address bus；Specific steps include: that S1.1 host CPU the first latch of control allows address bus total to data
The conveying of line；S1.2. host CPU control CPLD is in non-enabled state；It is not responding to PC104 bus operation at this time；S1.3. it leads
CPU executes data reading operation by PC104 bus, judges whether the data of read data and address bus are consistent, unanimously then sentence
It is normal to determine address bus, otherwise determines that address bus is abnormal；S1.4. it when address bus exception, is determined not by bit bit comparison
The corresponding address bus of consistent bit, records the exception information of detection, can guide staff in time, quickly, targetedly
Maintenance.
As shown in figure 5, the present embodiment further includes CPLD self-test；Its specific steps includes: S2.1. host CPU by first
GPIO bus reads the life signal of CPLD, if life signal situation of change is normal, go to step S2.2, otherwise jumps to
Step S2.3；S2.2. host CPU reads the life signal of CPLD by PC104 bus, if life signal situation of change is normal
Then determine that CPLD self-test is normal, otherwise determines that CPLD is abnormal to the connection between PC104 bus；S2.3. host CPU passes through PC104
Bus reads the life signal of CPLD, if life signal situation of change normally if determine that CPLD software is normal, and CPLD is extremely
Connection between PC104 bus is normal, and PC104 bus can be accessed normally, but the first GPIO bus connect exception with CPLD,
Otherwise determine that CPLD self-test is abnormal.In the present embodiment, the life signal of CPLD is read by different buses, and life is believed
Number judged, so that whether analyze CPLD bus whether different between normal and host CPU and CPLD normal.Host CPU is logical
Cross the life signal that the first GPIO bus reads CPLD, obtain first life signal of the CPLD, host CPU by data/address bus,
PC104 bus reads the life signal of CPLD, second life signal of the CPLD is obtained, respectively to first life signal and second
A life signal is judged that if, all normal, CPLD self-test is normal, while also illustrating the first GPIO bus, data/address bus
It is all normal with the state of PC104 bus.If first life signal is normal, second life signal exception then illustrates CPLD
Normally, but between CPLD and PC104 bus there is exception, need to check CPLD and PC104 bus with the presence or absence of virtual connection.If the
One life signal exception, second life signal is normal, illustrates that CPLD is normal, and PC104 bus is normal, but host CPU with
The first GPIO bus between GPLD is abnormal, needs to check the first GPIO bus with the presence or absence of virtual connection.If first life letter
Number and second life signal it is abnormal, then illustrate CPLD exception, need to check whether the software of CPLD is write with a brush dipped in Chinese ink, or check
Whether the hardware circuit of CPLD is abnormal.
As shown in fig. 6, the present embodiment further includes the PC104 bus self-test of main processing block side；Its specific steps includes:
S3.1. preset first self-inspection data is written to CPLD by PC104 bus in host CPU, then reads, and judges to be written and read
Whether data out are consistent, and unanimously then go to step S3.2, otherwise determine that main processing block side PC104 bus is abnormal；S3.2.
Preset second self-inspection data is written to CPLD by PC104 bus in host CPU, then reads, and judges to be written the number with reading
According to whether unanimously, unanimously then determines that main processing block side PC104 bus is normal, otherwise determine main processing block side PC104 bus
It is abnormal.In the present embodiment, the first self-inspection data is 0x5A, and the second self-inspection data is 0xA5.
As shown in fig. 7, the present embodiment further includes communication interface modules self-test；Its specific steps includes: that S4.1. host CPU is read
The life signal of communication interface modules is taken, if life signal is normal, go to step S4.2, otherwise judges communication interface mould
Block self-test is abnormal；S4.2. self-test mark is written to the command register of communication interface modules in host CPU；S4.3. host CPU is read
Otherwise the value of the response register of communication interface modules judges communication interface when value is that response mark then gos to step S4.4
Module self-test is abnormal；S4.4. successively preset self-inspection data is written to each data storage area of communication interface modules in host CPU, and
Data are read from each data storage area of communication interface modules, when reading, data are consistent with the preset self-inspection data being written,
Then judge that communication interface modules is normal, otherwise determines that data storage area is abnormal.Preset self-inspection data include 0x00,0x5A,
0xA5.In the present embodiment, host CPU is by the different data storage write-in self-inspection data into communication interface modules, and reads
The data being written illustrate the block data storage area of communication interface modules when the data of reading and the data of write-in are inconsistent
It is abnormal, there are bad block phenomenon, need to replace in time.
In this example, all testing results can be shown by man-machine interface, with remind staff and
The corresponding inspection operation of Shi Jinhang.
Embodiment two:
As shown in figure 3, the present embodiment is basically the same as the first embodiment, and the difference is that: the data based on PC104 bus
Acquisition device further includes the second latch, third latch and the 4th latch；Address bus is also connect with the second latch, the
Two latch are connect with PC104 bus；Data/address bus is also connect with third latch, and third latch is connect with PC104 bus；
CPLD is connect by the 4th latch with PC104 bus；CPLD respectively with the second latch, third latch and the 4th latch
Connection, CPLD is only hung in PC104 bus, not directly to communication interface modules output address, data/address bus.This example pair
The functional requirement of CPLD is high not as good as embodiment one.The self-diagnosing method of the present embodiment is the same as example 1.
Above-mentioned only presently preferred embodiments of the present invention, is not intended to limit the present invention in any form.Although of the invention
It has been disclosed in a preferred embodiment above, however, it is not intended to limit the invention.Therefore, all without departing from technical solution of the present invention
Content, technical spirit any simple modifications, equivalents, and modifications made to the above embodiment, should all fall according to the present invention
In the range of technical solution of the present invention protection.
Claims (8)
1. a kind of data acquisition device based on PC104 bus, including main processing block, communication interface module and PC104 bus,
The main processing block is connect by PC104 bus with communication interface module, it is characterised in that: the main processing block includes master
CPU, CPLD and the first latch；Between the host CPU and the CPLD by address bus, data/address bus, control bus and
The connection of first GPIO bus, first latch are connect with the address bus and data/address bus respectively, the host CPU and institute
It states and is connected between the first latch by the 2nd GPIO bus；The CPLD is connect with the PC104 bus；
The first driving power is provided on the address bus, the data/address bus is provided with the second driving power.
2. the data acquisition device according to claim 1 based on PC104 bus, it is characterised in that: further include the second lock
Storage, third latch and the 4th latch；The address bus is also connect with second latch, second latch
It is connect with PC104 bus；The data/address bus is also connect with the third latch, the third latch and PC104 bus
Connection；The CPLD is connect by the 4th latch with PC104 bus；The CPLD respectively with second latch,
Third latch and the connection of the 4th latch.
3. a kind of self-diagnosing method of the data acquisition device based on PC104 bus, it is characterised in that: including main processing block
Location bus self-test；Specific steps include:
S1.1 host CPU controls the conveying that the first latch allows address bus to data/address bus；
S1.2. host CPU control CPLD is in non-enabled state；
S1.3. host CPU executes data reading operation by PC104 bus, judge read data and address bus data whether one
It causes, unanimously then determines that address bus is normal, otherwise determine that address bus is abnormal；
S1.4. when the address bus exception, it is by read data described in bit bit comparison and the data of the address bus
It is no consistent, determine that the corresponding address bus of inconsistent bit is abnormal.
4. the self-diagnosing method of the data acquisition device according to claim 3 based on PC104 bus, it is characterised in that:
It further include CPLD self-test；Its specific steps includes:
S2.1. host CPU reads the life signal of CPLD by the first GPIO bus, if life signal situation of change is normal, jumps
Step S2.2 is gone to, step S2.3 is otherwise jumped to；
S2.2. host CPU by PC104 bus read CPLD life signal, if life signal situation of change normally if determine
CPLD self-test is normal, otherwise determines that the connection between CPLD and PC104 bus is abnormal；
S2.3. host CPU by PC104 bus read CPLD life signal, if life signal situation of change normally if determine
CPLD software is normal, and CPLD is normal to the connection between PC104 bus, and PC104 bus can be accessed normally, but first
GPIO bus connect exception with CPLD, otherwise determines that CPLD self-test is abnormal.
5. the self-diagnosing method of the data acquisition device according to claim 3 based on PC104 bus, it is characterised in that:
It further include the PC104 bus self-test of main processing block side；Its specific steps includes:
S3.1. preset first self-inspection data is written to CPLD by PC104 bus in host CPU, then reads, judges to be written
Whether consistent with the data of reading, unanimously then go to step S3.2, otherwise determines that main processing block side PC104 bus is abnormal；
S3.2. preset second self-inspection data is written to CPLD by PC104 bus in host CPU, then reads, judges to be written
It is whether consistent with the data of reading, unanimously then determine that main processing block side PC104 bus is normal, otherwise determines main processing block side
PC104 bus is abnormal.
6. the self-diagnosing method of the data acquisition device according to claim 5 based on PC104 bus, it is characterised in that:
First self-inspection data is 0x5A, and second self-inspection data is 0xA5.
7. the self-diagnosing method of the data acquisition device according to claim 3 based on PC104 bus, it is characterised in that:
It further include communication interface modules self-test；Its specific steps includes:
S4.1. the life signal that host CPU reads communication interface modules gos to step if the life signal is normal
Otherwise S4.2 judges that the communication interface modules self-test is abnormal；
S4.2. self-test mark is written to the command register of the communication interface modules in host CPU；
S4.3. host CPU reads the value of the response register of the communication interface modules, when described value is that response mark then jumps
To step S4.4, otherwise judge that communication interface modules self-test is abnormal；
S4.4. successively preset self-inspection data is written to each data storage area of the communication interface modules in host CPU, and from institute
Each data storage area for stating communication interface modules reads data, when the reading data and the preset self-inspection data one being written
It causes, then judges that communication interface modules is normal, otherwise determine that the data storage area is abnormal.
8. the self-diagnosing method of the data acquisition device according to claim 7 based on PC104 bus, it is characterised in that:
The preset self-inspection data includes 0x00,0x5A, 0xA5.
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| CN102489874A (en) * | 2011-11-25 | 2012-06-13 | 江苏大学 | Laser pulse control card of laser micro-processing equipment and control method |
| CN203643813U (en) * | 2013-11-28 | 2014-06-11 | 北车大连电力牵引研发中心有限公司 | CANOPEN main control device based on PC104 bus |
| CN104678918A (en) * | 2013-11-28 | 2015-06-03 | 北车大连电力牵引研发中心有限公司 | CANOPEN main control equipment based on PC104 bus and control method of CANOPEN main control equipment |
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| JP2005049993A (en) * | 2003-07-30 | 2005-02-24 | Canon Inc | Conference system and its control method |
| US20100092615A1 (en) * | 2008-10-14 | 2010-04-15 | Jose Angel Olalde Rangel | Thermoregulating herbal blend formulation for carbonated and non-carbonated beverages, and juices |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102489874A (en) * | 2011-11-25 | 2012-06-13 | 江苏大学 | Laser pulse control card of laser micro-processing equipment and control method |
| CN203643813U (en) * | 2013-11-28 | 2014-06-11 | 北车大连电力牵引研发中心有限公司 | CANOPEN main control device based on PC104 bus |
| CN104678918A (en) * | 2013-11-28 | 2015-06-03 | 北车大连电力牵引研发中心有限公司 | CANOPEN main control equipment based on PC104 bus and control method of CANOPEN main control equipment |
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