CN106601720A - Testing structure and testing method of semiconductor - Google Patents
Testing structure and testing method of semiconductor Download PDFInfo
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- CN106601720A CN106601720A CN201510666862.2A CN201510666862A CN106601720A CN 106601720 A CN106601720 A CN 106601720A CN 201510666862 A CN201510666862 A CN 201510666862A CN 106601720 A CN106601720 A CN 106601720A
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Abstract
The invention provides a testing structure of a semiconductor, The testing structure comprises a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes at least two ground metal wires arranged in parallel; and at least two oblong first metal blocks having the arrangement direction identical with that of the ground metal wires are formed between the two adjacent ground metal wires. The second metal layer includes a plurality of metal conductive posts that correspond to the first metal blocks and are connected to the tops of the first metal blocks. And the third metal layer consists of a plurality of oblong second metal blocks corresponding to the metal conductive posts; the second metal bocks are connected to the tops of the metal conductive posts and the arrangement direction of the second metal blocks is perpendicular to that of the ground metal wires. The testing structure has a simple structure; and the interlamination through-hole metal layer process can be reflected effectively. With a plurality of blocks with different testing distances, the on-line process window size can be fed back in real time and the process improvement can be promoted; and with the testing method, a defect can be localized rapidly; and the operation improvement effect can be fed back timely.
Description
Technical field
The invention belongs to field of semiconductor manufacture, is related to a kind of semi-conductor test structure and method of testing.
Background technology
With the progress of semiconductor technology, the integrated level more and more higher of integrated circuit, the size of semiconductor device is less and less, because
Technologic trickle error in this manufacturing process, will produce serious influence to yield rate, device performance, device reliability etc..
Prepare smaller szie, the device of higher performance is always target and the direction that semi-conductor industry develops, with 28nm techniques
The propulsion of node, in order to further realize volume production, there are problems that in metal postchannel process it is many need solve.Wherein, rear road is carved
In etching technique, larger porosity characteristics size is a key factor for causing current yield relatively low.This larger through hole is caused
Metal-metal spacing reduces, and so as to easily cause underlying metal short circuit, and produces signal interference.Its reason is primarily due to 28nm
In technique, metal-metal spacing very little, and process window also very little.
Therefore need to control through hole critical size by adjusting process menu (recipe tuning).But current problems faced
Mainly cannot real time on-line monitoring defect because defect hiding is below metal wire, and random distribution.
Current solution is mainly by taking offline defect analysiss (Outline FA), and it passes through first chip testing (CP
Test defect) is found out, then the circuit-line that fails is gone out by DFT (Design For Testability) test badge, further along line
In layer find defect in road.The existing improvement cycle significantly extends, and has delayed volume production schedule.
Therefore, a kind of semi-conductor test structure knot method of testing how is provided, with monitor in real time metallic conduction post defect, and quickly
Positioning defective locations, are greatly decreased the improvement cycle, obtain true and reliable defect information, become those skilled in the art and urgently solve
An important technological problems certainly.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of semi-conductor test structure and method of testing,
Monitor in real time via metal conductive pole defect, and too long of problem of existing improvement cycle are unable in for solving prior art.
For achieving the above object and other related purposes, the present invention provides a kind of semi-conductor test structure, including：
The first metal layer；The first metal layer includes at least two grounded metal lines arranged in parallel, adjacent two grounded metals
At least two the first metal derbies of rectangle are formed between line；The orientation phase of first metal derby and the grounded metal line
Together；
Second metal layer；The second metal layer includes some metallic conduction posts corresponding with first metal derby, the gold
Category conductive pole is connected to the first metal derby top；
3rd metal level；3rd metal level includes some rectangle second metal derbies corresponding with the metallic conduction post,
Second metal derby is connected to the metallic conduction post top, and the orientation of second metal derby perpendicular to the ground connection
Metal wire.
Alternatively, first metal derby is equal with the distance between the grounded metal line of its both sides.
Alternatively, the semi-conductor test structure include at least two blocks, each block by the first metal layer, second
Metal level and the 3rd metal level are constituted；The distance between the grounded metal line on first metal derby and its left side or right side is test
Distance, and the measuring distance of each block is unequal.
Alternatively, a grounded metal line is shared between two neighboring block.
Alternatively, the semi-conductor test structure includes 5 blocks, and the initial value of the measuring distance is 20nm, is increased every time
Plus 5nm, until 40nm.
Alternatively, the material of the metallic conduction post is copper, copper alloy, tungsten or tungsten alloy.
Alternatively, the test structure is located at the Cutting Road region of wafer.
The present invention also provides a kind of method that test structure using described in above-mentioned any one carries out semiconductor test, including following
Step：
S1：Using test structure described in electron beam scanning, and observe the bright-dark degree of second metal derby；
S2：If wherein one or more second metal derbies are brighter relative to other metal derbies, it is determined that the second brighter metal derby
For defect place.
Alternatively, in step S1, the bright-dark degree of second metal derby is observed by scanning electron microscope.
Alternatively, in step S2, core is determined according to the projected direction of the metallic conduction post under the second brighter metal derby
The offset direction of panel region metallic conduction post.
As described above, the semi-conductor test structure and method of testing of the present invention, have the advantages that：(1) survey of the invention
The characteristics of examination structure has simple structure, and can effectively reflect inter-level vias metal layer process；(2) test structure of the invention can
Differed with the measuring distance including multiple blocks, each block, be technique such that it is able to feed back online process window size
Improvement provides help；(3) test structure of the invention can apply to the defects detection per via layer between from level to level, and supervise in real time
The performance of inter-level vias layer is surveyed, 28nm process nodes or the Resolving probiems of other process nodes can be helped；(4) it is of the invention
Method of testing by test structure described in online electron beam scanning, and observe the bright-dark degree of second metal derby i.e. can be quick
Positioning defect, according to the projected direction of metallic conduction post in test structure the offset direction of chip area metallic conduction post is determined,
Can feed back in time improves the effect of operation.
Description of the drawings
Fig. 1 is shown as structure sectional view of the semi-conductor test structure of the present invention in embodiment one.
Fig. 2 is shown as the top view of structure shown in Fig. 1.
Fig. 3 is shown as the flow chart of the method for testing of the present invention.
Fig. 4 is shown as in the test structure of the present invention schematic diagram with defect area.
Fig. 5 is shown as the structure sectional view in region shown in Fig. 4 dotted line frames.
Fig. 6 is shown as the structural representation observed when testing.
Fig. 7 is shown as structure top view of the semi-conductor test structure of invention in embodiment two.
Component label instructions
100 the first metal layers
101 grounded metal lines
102 first metal derbies
200 second metal layers
201 metallic conduction posts
300 the 3rd metal levels
301 second metal derbies
400 defect areas
S1～S2 steps
The blocks of I first
The blocks of II second
The blocks of III the 3rd
Specific embodiment
Embodiments of the present invention are illustrated below by way of specific instantiation, those skilled in the art can be by disclosed by this specification
Content understand easily the present invention other advantages and effect.The present invention can also be added by specific embodiments different in addition
To implement or apply, the every details in this specification can also be based on different viewpoints and application, in the essence without departing from the present invention
Various modifications and changes are carried out under god.
Refer to Fig. 1 to Fig. 7.It should be noted that the diagram provided in the present embodiment only illustrates in a schematic way the present invention
Basic conception, only show in schema then with relevant component in the present invention rather than according to component count, shape during actual enforcement
And size is drawn, it is actual when the implementing kenel of each component, quantity and ratio can be a kind of random change, and its assembly layout
Kenel is likely to increasingly complex.
Embodiment one
The present invention provides a kind of semi-conductor test structure, refers to Fig. 1, is shown as the sectional view of the semi-conductor test structure, wraps
Include：
The first metal layer 100；The first metal layer 100 include at least two grounded metal lines 101 arranged in parallel, adjacent two
At least two the first metal derbies of rectangle 102 are formed between bar grounded metal line 101；First metal derby 102 with it is described
The orientation of grounded metal line 101 is identical；
Second metal layer 200；The second metal layer 200 is led including some metals corresponding with first metal derby 102
Electric post 201, the metallic conduction post 201 is connected to the top of first metal derby 102；
3rd metal level 300；3rd metal level 300 includes some rectangles second corresponding with the metallic conduction post
Metal derby 301, second metal derby 301 is connected to the top of the metallic conduction post 201, and second metal derby 301
Orientation perpendicular to the grounded metal line 101.
Fig. 2 is referred to, the top view of structure shown in Fig. 1 is shown as.As an example, grounded metal line shown in Fig. 1 and Fig. 2
101 number is 7, and in other embodiments, the number of the grounded metal line 101 can be increased and decreased as needed,
Should not too limit the scope of the invention herein.
The test structure of the present invention may be disposed at the Cutting Road region of wafer, be applied to the online defects detection of inter-level vias layer.It is right
In per via layer between from level to level, the test structure corresponding thereto can be respectively made.The test structure can be with chip area
Respective metal layers and via layer synchronously make.
It should be noted that first metal derby 102 it is identical with the orientation of the grounded metal line 101 refer to it is rectangular
The long side direction of the first metal derby of shape is parallel with the grounded metal line, and short side direction is vertical with the grounded metal line.
Specifically, first metal derby 102 is preferably equal with the distance between the grounded metal line 101 of its both sides, so as to
The degree that metallic conduction post offsets to the left or to the right can under equal conditions be judged.
The material phase of the metallic conduction post in the material of the metallic conduction post 102 and the inter-level vias layer of chip area on wafer
Together, including but not limited to copper, copper alloy, tungsten or tungsten alloy.
Fig. 3 is referred to, the method flow diagram that the test structure of the present invention is tested is shown with, is comprised the following steps：
S1：Using test structure described in electron beam scanning, and observe the bright-dark degree of second metal derby；
S2：If wherein one or more second metal derbies are brighter relative to other metal derbies, it is determined that the second brighter metal derby
For defect place.
Specifically, in step S1, the bright-dark degree of second metal derby 301 is observed by scanning electron microscope.
The method of testing of the present invention is carried out according to voltage-contrast (Voltage contrast) principle of scanning electron microscope, i.e.,
Under low electron accelerating voltage (typically smaller than 3kV), ground connection and earth-free metal can reflect different bright dark degree.
Specifically, ground connection is different from earth-free metal surface potential, final anti-so as to how much different the electron beam of metallic reflection is
Reflect the bright dark difference for metal.When metal derby is unearthed, then under electronic scanner microscope, the electron beam of its reflection is less,
Color is dark；When metal derby is grounded, then under electronic scanner microscope, the electron beam of its reflection is more, and color is brighter.
During test, it is assumed that there is a larger defective hole in the test structure, as an example, Fig. 4 and Fig. 5 is referred to,
Defect area 400 is shown in wherein Fig. 4, Fig. 5 is shown as the structure sectional view in region shown in Fig. 4 dotted line frames.It can be seen that, compared with
Big through hole causes conducting metal post 201 to overflow first metal derby 102, and connects with the side of the first metal derby 102
Ground metal wire 101 connects, so that second metal derby 301 is in ground state.As shown in fig. 6, sweeping in electron beam
When retouching, second metal derby (such as arrow indication in Fig. 6) of defect area will seem more relative to other second metal derbies 301
It is bright, such that it is able to quick positioning defect areas.
As shown in figure 5, in step S2, according to the prominent of the metallic conduction post 201 under the second brighter metal derby 301
Outgoing direction determines the offset direction of chip area metallic conduction post.
The characteristics of test structure of the present invention has simple structure, and can effectively reflect inter-level vias metal layer process.The present invention's
Test structure can apply to the defects detection per via layer between from level to level, and the performance of real-time monitoring inter-level vias layer, Neng Goubang
Help 28nm process nodes or the Resolving probiems of other process nodes.The method of testing of the present invention is by described in online electron beam scanning
Test structure, and observe the bright-dark degree of second metal derby and can quickly position defect, led according to metal in test structure
The projected direction of electric post determines the offset direction of chip area metallic conduction post, and can feed back in time improves the effect of operation, from
And greatly shorten the process improving cycle.
Embodiment two
The present embodiment and embodiment one adopt the essentially identical technical scheme, difference to be, the semiconductor test of embodiment one
Only include a block in structure, and the semi-conductor test structure of the present embodiment includes at least two blocks.
Fig. 4 is referred to, the top view of semi-conductor test structure described in the present embodiment is shown as, as illustrated, the quasiconductor
Test structure includes at least two blocks, such as the first block I, the second block II, the 3rd block III ....Each block is equal
It is made up of such as the first metal layer 100 described in embodiment one, the metal level 300 of second metal layer 200 and the 3rd, i.e., described first
Metal level 100 includes at least two grounded metal lines 101 arranged in parallel, is formed between adjacent two grounded metal lines 101
At least two the first metal derbies of rectangle 102；The orientation phase of first metal derby 102 and the grounded metal line 101
Together；The second metal layer 200 includes some metallic conduction posts 201 corresponding with first metal derby 102, the gold
Category conductive pole 201 is connected to the top of first metal derby 102；3rd metal level 300 is led including some with the metal
The corresponding metal derby of rectangle second of electric post, second metal derby is connected to the metallic conduction post top, and described second
The orientation of metal derby is perpendicular to the grounded metal line.
Specifically, as shown in fig. 7, a grounded metal line 101 can be shared between two neighboring block.In other embodiments,
Also can be separate between each block, and not necessarily arrange in a row, it is also possible to it is arranged in multiple lines and multiple rows.
Specifically, the distance between the grounded metal line 101 on first metal derby 102 and its left side or right side is measuring distance,
And the measuring distance of each block is unequal.As an example, the semi-conductor test structure include 5 blocks, the test away from
From initial value be 20nm, 5nm is increased every time, until 40nm.For ease of illustration, 3 are illustrate only in Fig. 7
Block, wherein the measuring distance of the first block I is 20nm, the measuring distance of the second block II is 25nm, the survey of the 3rd block
Examination distance is 30nm.Certainly, in other embodiments, the quantity of the block can be increased and decreased as needed, be increased every time
Plus measuring distance can also according to test fine degree be adjusted, should not too limit the scope of the invention herein.
Because the test structure of the present embodiment includes multiple blocks, and the measuring distance of each block is differed, therefore can be real
When feed back online process window size, provide help for process improving.
In sum, semi-conductor test structure of the invention and method of testing, have the advantages that：(1) survey of the invention
The characteristics of examination structure has simple structure, and can effectively reflect inter-level vias metal layer process；(2) test structure of the invention can
Differed with the measuring distance including multiple blocks, each block, be technique such that it is able to feed back online process window size
Improvement provides help；(3) test structure of the invention can apply to the defects detection per via layer between from level to level, and supervise in real time
The performance of inter-level vias layer is surveyed, 28nm process nodes or the Resolving probiems of other process nodes can be helped；(4) it is of the invention
Method of testing by test structure described in online electron beam scanning, and observe the bright-dark degree of second metal derby i.e. can be quick
Positioning defect, according to the projected direction of metallic conduction post in test structure the offset direction of chip area metallic conduction post is determined,
Can feed back in time improves the effect of operation.So, the present invention effectively overcomes various shortcoming of the prior art and has height and produce
Industry value.
The principle and its effect of above-described embodiment only illustrative present invention, it is of the invention not for limiting.It is any to be familiar with this skill
The personage of art all can carry out modifications and changes under the spirit and the scope without prejudice to the present invention to above-described embodiment.Therefore, such as
Those of ordinary skill in the art completed under without departing from disclosed spirit and technological thought all etc.
Effect modifications and changes, should be covered by the claim of the present invention.
Claims (10)
1. a kind of semi-conductor test structure, it is characterised in that include：
The first metal layer；The first metal layer includes at least two grounded metal lines arranged in parallel, adjacent two ground connection gold
At least two the first metal derbies of rectangle are formed between category line；The arrangement side of first metal derby and the grounded metal line
To identical；
Second metal layer；The second metal layer includes some metallic conduction posts corresponding with first metal derby, described
Metallic conduction post is connected to the first metal derby top；
3rd metal level；3rd metal level includes some rectangle second metals corresponding with the metallic conduction post
Block, second metal derby is connected to the metallic conduction post top, and the orientation of second metal derby perpendicular to institute
State grounded metal line.
2. semi-conductor test structure according to claim 1, it is characterised in that：First metal derby is golden with the ground connection of its both sides
The distance between category line is equal.
3. semi-conductor test structure according to claim 2, it is characterised in that：The semi-conductor test structure includes at least two
Block, each block is constituted by the first metal layer, second metal layer and the 3rd metal level；First metal derby with
The distance between the grounded metal line on its left side or right side is measuring distance, and the measuring distance of each block is unequal.
4. semi-conductor test structure according to claim 3, it is characterised in that：A ground connection gold is shared between two neighboring block
Category line.
5. semi-conductor test structure according to claim 3, it is characterised in that：The semi-conductor test structure includes 5 blocks,
The initial value of the measuring distance is 20nm, 5nm is increased every time, until 40nm.
6. semi-conductor test structure according to claim 1, it is characterised in that：The material of the metallic conduction post is copper, copper conjunction
Gold, tungsten or tungsten alloy.
7. semi-conductor test structure according to claim 1, it is characterised in that：The test structure is located at the Cutting Road area of wafer
Domain.
8. a kind of method that test structure using as described in claim 1～7 any one carries out semiconductor test, it is characterised in that
Comprise the following steps：
S1：Using test structure described in electron beam scanning, and observe the bright-dark degree of second metal derby；
S2：If wherein one or more second metal derbies are brighter relative to other metal derbies, it is determined that the second brighter metal
Block is defect place.
9. the method for semiconductor test according to claim 8, it is characterised in that：In step S1, by scanning electricity
The bright-dark degree of the second metal derby described in the micro- sem observation of son.
10. the method for semiconductor test according to claim 8, it is characterised in that：It is brighter according to this in step S2
The second metal derby under the projected direction of metallic conduction post determine the offset direction of chip area metallic conduction post.
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| CN201510666862.2A CN106601720B (en) | 2015-10-15 | 2015-10-15 | A kind of semi-conductor test structure and test method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510666862.2A CN106601720B (en) | 2015-10-15 | 2015-10-15 | A kind of semi-conductor test structure and test method |
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| Publication Number | Publication Date |
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| CN106601720A true CN106601720A (en) | 2017-04-26 |
| CN106601720B CN106601720B (en) | 2019-03-29 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6949765B2 (en) * | 2002-11-05 | 2005-09-27 | Chartered Semiconductor Manufacturing Ltd. | Padless structure design for easy identification of bridging defects in lines by passive voltage contrast |
| US20060220240A1 (en) * | 2005-03-14 | 2006-10-05 | Samsung Electronics Co., Ltd. | Analytic structure for failure analysis of semiconductor device |
| US7772590B2 (en) * | 2007-03-05 | 2010-08-10 | Systems On Silicon Manufacturing Co. Pte. Ltd. | Metal comb structures, methods for their fabrication and failure analysis |
| CN102446901A (en) * | 2010-10-14 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Failure analysis structure, formation method of failure analysis structure and failure analysis method |
| CN103594453A (en) * | 2012-08-15 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | Test structure for dielectric breakdown reliability analysis in integrated circuit and test method thereof |
-
2015
- 2015-10-15 CN CN201510666862.2A patent/CN106601720B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6949765B2 (en) * | 2002-11-05 | 2005-09-27 | Chartered Semiconductor Manufacturing Ltd. | Padless structure design for easy identification of bridging defects in lines by passive voltage contrast |
| US20060220240A1 (en) * | 2005-03-14 | 2006-10-05 | Samsung Electronics Co., Ltd. | Analytic structure for failure analysis of semiconductor device |
| US7772590B2 (en) * | 2007-03-05 | 2010-08-10 | Systems On Silicon Manufacturing Co. Pte. Ltd. | Metal comb structures, methods for their fabrication and failure analysis |
| CN102446901A (en) * | 2010-10-14 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Failure analysis structure, formation method of failure analysis structure and failure analysis method |
| CN103594453A (en) * | 2012-08-15 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | Test structure for dielectric breakdown reliability analysis in integrated circuit and test method thereof |
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| CN106601720B (en) | 2019-03-29 |
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