CN106576087A - Orthogonal differential vector signaling codes with embedded clock - Google Patents

Orthogonal differential vector signaling codes with embedded clock Download PDF

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CN106576087A
CN106576087A CN201580041726.2A CN201580041726A CN106576087A CN 106576087 A CN106576087 A CN 106576087A CN 201580041726 A CN201580041726 A CN 201580041726A CN 106576087 A CN106576087 A CN 106576087A
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input
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set
signal
vector
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布赖恩·霍尔登
阿明·肖克罗拉
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康杜实验室公司
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Priority to PCT/US2015/043463 priority patent/WO2016019384A1/en
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/26Systems using multi-frequency codes
    • H04L27/2601Multicarrier modulation systems
    • H04L27/2626Arrangements specific to the transmitter
    • H04L27/2627Modulators
    • H04L27/2637Modulators with direct modulation of individual subcarriers
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4247Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
    • G06F13/426Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076Timing circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4093Input/output [I/O] data interface arrangements, e.g. data buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066Output synchronization
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093Input synchronization
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222Clock generating, synchronizing or distributing circuits within memory device
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/38Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40Transmitting circuits; Receiving circuits
    • H04L25/49Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H04L25/4919Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using balanced multilevel codes
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing
    • Y02D10/10Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply
    • Y02D10/14Interconnection, or transfer of information or other signals between, memories, peripherals or central processing units
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing
    • Y02D10/10Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply
    • Y02D10/15Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply acting upon peripherals
    • Y02D10/151Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply acting upon peripherals the peripheral being a bus

Abstract

Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.

Description

带内嵌时钟的正交差分向量信令码 With embedded clock difference vector orthogonal signaling code

[0001] 相关申请的交叉引用 CROSS [0001] REFERENCE TO RELATED APPLICATIONS

[0002] 本申请要求申请号为62,032,175,申请日为2014年8月1日,发明人为布赖恩"霍尔登(Brian Holden)和阿明〃肖克罗拉(Amin Shokrollahi),名称为"带内嵌时钟的正交差分向量信令码"的美国临时专利申请的优先权,并通过引用将其内容整体并入本文,以供所有目的之用。 [0002] This application claims Application No. 62,032,175, filed August 1, 2014, inventor Bryan "Holden (Brian Holden) and Amin 〃 Shocker roller (Amin Shokrollahi), entitled U.S. provisional Patent "with embedded clock difference vector orthogonal signaling code" priority application, and incorporated by its entirety herein for all purposes by reference.

[0003] 参考文献 [0003] Reference

[0004] 以下参考文献通过引用整体并入本文,以供所有目的之用: [0004] The following references are incorporated herein by reference in its entirety, for all purposes of use:

[0005] 公开号为2011/0268225,申请号为12/784,414,申请日为2010年5月20日,发明人为Harm Cronie和Amin Shokrollahi,名称为"正交差分向量信令"的美国专利申请,下称〈〈Cronie 1〉〉; [0005] Publication No. 2011/0268225, Application No. 12 / 784,414, filed May 20, 2010, inventor Harm Cronie and Amin Shokrollahi, entitled "Orthogonal differential vector signaling" U.S. Patent Application, hereinafter referred to as << Cronie 1 >>;

[0006] 申请号为13/030,027,申请日为2011年2月17日,发明人为Harm Cronie、Amin ShokrolIahi和Armin Tajalli,名称为"利用稀疏信令码进行抗噪声干扰、高引脚利用率、 低功耗通讯的方法和系统"的美国专利申请,下称《Cronie 2》; [0006] Application No. 13 / 030,027, filed February 17, 2011, by inventors Harm Cronie, Amin ShokrolIahi and Armin Tajalli, entitled "sparse signaling code for anti-noise, high efficiency pin, low-power communication method and system, "US patent application, hereinafter referred to as" Cronie 2 ";

[0007] 申请号为14/158,452,申请日为2014年1月17日,发明人为John Fox、Brian HolderuPeter Hunt、John D Keay、Amin Shokrollahi、Richard SimpsoruAnant Singh、 Andrew Kevin John Stewart和Giuseppe Surace,名称为"低同步开关噪声芯片间的通信" 的美国专利申请,下称《Fox 1》; [0007] Application No. 14 / 158,452, filed on January 17, 2014, inventor John Fox, Brian HolderuPeter Hunt, John D Keay, Amin Shokrollahi, Richard SimpsoruAnant Singh, Andrew Kevin John Stewart and Giuseppe Surace, name "synchronous communication between the low switching noise chip" U.S. Patent application, hereinafter referred to as "Fox 1";

[0008] 申请号为13/842,740,申请日为2013年3月15日,发明人为Brian Holden、Amin ShokroI Iahi和Anant Singh,名称为"芯片间通信的向量信令码中的偏斜耐受方法以及用于芯片间通信的向量信令码的高级检测器"的美国专利申请,下称《Holden 1》; [0008] Application No. 13 / 842,740, filed March 15, 2013, inventors Brian Holden, Amin ShokroI Iahi and Anant Singh, entitled "signaling code vector in the inter-chip communication method of skew tolerance and a detector for advanced inter-chip communication signaling code vector "U.S. Patent application, hereinafter referred to as" Holden 1 ";

[0009] 申请号为61/934,804,申请日为2014年2月2日,发明人为Ali Hormati和Amin Shokrollahi,名称为"利用ISI比进行代码评价的方法"的美国临时专利申请,下称《Hormati 1》; [0009] Application No. 61 / 934,804, filed Feb. 2, 2014, inventor Ali Hormati and Amin Shokrollahi, entitled "using the ISI method than the code evaluation of" U.S. Provisional Patent Application, hereinafter referred to as "Hormati 1";

[0010] 申请号为61/934,807,申请日为2014年2月2日,发明人为Amin Shokrollahi,名称为"高引脚利用率向量信令码及其在芯片间通信及存储中的应用",下称《Shokrollahi 1》; [0010] Application No. 61 / 934,807, filed Feb. 2, 2014, inventors Amin Shokrollahi, entitled "High efficiency pins signaling code vector and its application in inter-chip communication and store" hereinafter referred to as "Shokrollahi 1";

[0011] 申请号为61/839,360,申请日为2013年6月23日,发明人为Amin Shokrollahi,名称为"低接收器复杂度的向量信令码"的美国临时专利申请,下称《Shokrollahi 2》; [0011] Application No. 61 / 839,360, filed June 23, 2013, by inventors Amin Shokrollahi, entitled "Low complexity receptor signaling code vector" U.S. Provisional Patent Application, hereinafter referred to as "Shokrollahi 2 ";

[0012] 申请号为61/946,574,申请日为2014年2月28日,发明人为AminShokrollahi, Br i anHo I den和Ri chardS imp son,名称为"内嵌时钟的向量信令码"的美国临时专利申请,下称《Shokrollahi 3》; [0012] Application No. 61 / 946,574, filed February 28, 2014, by inventors AminShokrollahi, Br i anHo I den and Ri chardS imp son, entitled "Embedded signaling code vector clock" U.S. Provisional patent application, hereinafter referred to as "Shokrollahi 3";

[0013] 申请号为62/015,172,申请日为2014年7月10日,发明人为Amin Shokrollahi和R 〇ger UI rich,名称为"高信噪比特性向量信令码"的美国临时专利申请,下称((Shokrollahi 4〉〉; [0013] Application No. 62 / 015,172, filed July 10, 2014, inventors Amin Shokrollahi and R 〇ger UI rich, entitled "High SNR characteristic vector signaling code" U.S. Provisional Patent Application, hereinafter referred to as ((Shokrollahi 4 >>;

[0014] 申请号为13/895,206,申请日为2013年3月15日,发明人为Roger Ulrich和Peter Hunt,名称为"用于通过差和高效检测芯片间通信用的向量信令码的电路"的美国专利申请,下称《Ulrich 1》; [0014] Application No. 13 / 895,206, filed March 15, 2013, by inventors Roger Ulrich and Peter Hunt, entitled "Circuit and efficient detection by a difference between the communication chip for signaling code vector" US Patent application, hereinafter referred to as "Ulrich 1";

[0015] 申请号为62/026,860,申请日为2014年7月21日,发明人为Roger Ulrich和Amin Shokrollahi,名称为"总线可逆正交差分向量信令码"的美国临时专利申请,下称《Ulrich 2》; [0015] Application No. 62 / 026,860, filed July 21, 2014, by inventors Roger Ulrich and Amin Shokrollahi, entitled "Bus reversible difference vector orthogonal signaling code" U.S. Provisional Patent Application, hereinafter " Ulrich 2 ";

[0016] 此外,本申请中还引用了以下现有技术参考文献: [0016] Further, the present application also refers to the following prior art references:

[0017] 专利号为7,053,802,申请日为2004年4月22日,授权公告日为2006年5月30日,发明人为William Cornelius,名称为"带内嵌定时功能的单端平衡编码型接口"的美国专利, 下称《Cornel ius》; [0017] Patent No. 7,053,802, filed April 22, 2004, authorized announcement of May 30, 2006, inventor William Cornelius, entitled "Embedded timing function with single-ended balanced coding Interface" US Patent, hereinafter referred to as "Cornel ius";

[0018] 专利号为8,064,535,申请日为2007年3月2日,授权公告日为2011年11月22日,发明人为George Wi Iey,名称为"三相三极编码型串行接口"的美国专利,下称《Wi Iey》; [0018] Patent No. 8,064,535, filed March 2, 2007, authorized announcement for the November 22, 2011, inventor George Wi Iey, the name "three-pole three-phase encoded serial interface" of the United States patents, hereinafter referred to as "Wi Iey";

[0019] 专利号为8,649,460,申请日为2010年3月11日,授权公告日为2014年2月11日,发明人为Frederick Ware和Jade Kizer,名称为"利用嵌入式时钟进行多线路编码的技术"的美国专利,下称《Ware》。 [0019] Patent No. 8,649,460, filed March 11, 2010, authorized announcement is February 11, 2014, inventor Frederick Ware and Jade Kizer, the name "technology with an embedded clock multi-line coding "US Patent, hereinafter referred to as" Ware ".

背景技术 Background technique

[0020] 通信系统中的一个目的在于将信息从一个物理位置传输至另一物理位置。 [0020] The object of a communication systems is the information transmitted from one physical location to another physical location. 一般而言,此类信息传输的目标在于,可靠、快速且消耗最少的资源。 In general, such information transfer aims, reliable, fast and consumes minimal resources. 一种常见的信息传输媒介为串行通信链路,此种链路可以以将地面或其他常用基准作为比较对象的单个有线电路或将地面或其他常用基准作为比较对象的多个此类有线电路为基础。 A common information transmission medium is a serial communication link, such a link may be the ground or other common wired circuit compares the reference as a single object or the ground or other objects commonly used as a comparison reference of a plurality of such wired circuit basis. 常见的一例为使用单端信令(SES)。 A common example is the use of single-ended signaling (SES). 单端信令的工作原理为,在一条线路中发送信号,然后在接收器端以固定基准值为比较对象测定所述信号。 Works for single-ended signaling, the transmission signal in one line, and then to fix the reference value for comparison of the measured signal at the receiver. 串行通信链路也可以以相互间作为比较对象的多个电路为基础。 Serial communications link may be a plurality of circuits to each other as a comparison basis. 此方面的常见的一例为使用差分信令(DS)。 Common example of this aspect is the use of differential signaling (DS). 差分信令的工作原理在于,在一条线路中发送信号,并在配对线路中发送所述信号的相反信号。 Working principle of differential signaling is that the transmission signal in one line, and sends the opposite signal of the signal line pairing. 所述信号的信息由上述两线路之间的差值,而非其相对于地面或其他固定基准值的绝对值表示。 Said information signal by a difference between the two lines, rather than relative to the ground or other fixed reference value represents an absolute value.

[0021] 与差分信令相比,有多种信令方法可在增加引脚利用率的同时,保持相同的有益特性。 [0021] Compared with differential signaling, a variety of signaling method can increase the utilization of the pins while maintaining the same beneficial characteristics. 向量信令为一种信令方法。 Vector signaling as a signaling method. 通过向量信令,多条线路中的多个信号在保持每个信号的独立性的同时可视为一个整体。 Signaling by a vector, the plurality of the plurality of signal lines while maintaining the independence of each signal may be considered as a whole. 该信号整体中的每个信号均称为向量分量,而所述多条线路的数目称为向量"维数"。 Each entire signal in the signal vector components are referred to, and the number of the plurality of lines is called a vector "dimension." 在一些实施方式中,与差分信令对的情况相同,一条线路中的信号完全取决于另一线路中的信号。 In some embodiments, as in the case of differential signaling, the signal line is completely dependent on a signal of the other lines. 因此,在某些情况下,向量维数可指多条线路内的信号的自由度数,而非该多条线路的数目。 Thus, in some cases, vector dimension may refer to the number of degrees of freedom in a plurality of signal lines, rather than the number of said plurality of lines.

[0022] 向量信令码的任何合适子集均为该码的"子码"。 [0022] Any suitable vector signaling code a subset of the code are "sub-code." 此类子码可本身为一种向量信令码。 Such subcode may itself as a signaling code vector. 在二元向量信令中,每个向量分量(或称"符号")的取值为两个可能取值当中的一值。 Signaling binary vectors, each vector component (or "symbol") is a value of two possible values ​​among values. 在非二元向量信令中,每个符号的取值为从由两个以上可能取值所组成的集合中选出的一值。 In the non-binary vector signaling, the value of each symbol is a value selected from a set of two or more possible values ​​consisting of. 当作为物理信号在通信介质中传输时,符号可由适合于该介质的具体物理值表示。 When the transmitted signal as a physical communications medium, the symbol value may be adapted to the particular physical representation of the medium. 例如,在一种实施方式中,可由150mV的电压表不符号"+1",50mV的电压表不符号"_1" ;而在另一实施方式中,"+1"可由800mV表不,"_1"可由_800mV表不。 For example, in one embodiment, the voltage may be 150mV symbol table is not the "+1", 50mV voltmeter The symbol "_1"; and in another embodiment, the "+ 1" may be 800mV table is not "1 _ "_800mV table may not.

[0023] 在本文中,向量信令码为由具有相同长度N的向量(称作码字)组成的集合C。 [0023] As used herein, by the signaling code vector having the same collection of vector length N (referred to as a codeword) C. 集合C 大小的二进制对数与长度N之间的比值称为该向量信令码的引脚利用率。 C to set the size of the binary number and the ratio between the length N of the vector is called pin utilization signaling code. 向量信令码的示例见《Cronie l》、《Cronie 2》、《Fox l》、《Shokrollahi l》、《Shokrollahi 2》及《Shokrollahi 3》中的正交差分向量信令码,该码在本文中用于描述目的。 See example signaling code vector "Cronie l", "Cronie 2", "Fox l", "Shokrollahi l", the "Shokrollahi 2" and "Shokrollahi 3" difference vector orthogonal signaling code, which herein They are used for descriptive purposes.

[0024] 图1所示为采用向量信令码的通信系统。 It shows a communication system using the signaling code vector [0024] FIG. 比特S0,S1,S2从分块100进入编码器112。 Bits S0, S1, S2 from encoder 112 enters block 100. 该分块的大小可变且取决于所述向量信令码的参数。 The variable size of the block depends on the parameters of the vector and the signaling code. 所述编码器生成该向量信令码的码字,而且所述系统为针对该向量信令码而设计的系统。 The encoder generates a code word signaling code vector, and the vector for the system is a signaling system designed code. 运行时,所述编码器可生成信息,该信息用于控制驱动器118内的PMOS和匪OS晶体管,从而在N条通信线路125上生成电压或电流,且该N条通信线路包括通信信道120。 Operation, the encoder may generate information which is used to control the drive PMOS and bandit OS transistors 118, thereby generating a voltage or current on the N communication lines 125, and the N communication lines include a communication channel 120. 接收器132读取所述线路中的电压或电流,此过程有可能涉及放大、频率补偿和共模信号消除。 The receiver circuit 132 reads the voltage or current, this process might involve amplification, frequency compensation and common mode canceled. 接收器132将其结果提供于解码器138,该解码器重新在140处生成上述输入比特,此处表示为接收比特RO,Rl,R2。 The receiver 132 provides the result to the decoder 138, the decoder 140 re-generated at the input bits, here denoted as receiving a bit RO, Rl, R2.

[0025] 根据所使用向量信令码的不同,可不设置解码器,或不设置编码器,或既不设置解码器也不设置编码器。 [0025] Depending on the vector used in the signaling code, the decoder may not be provided, or not provided an encoder, a decoder is not provided, or neither is provided an encoder. 举例而言,对于《Cronie 2》中公开的8b8w码,既设置了编码器112,也同时设置了解码器138。 For example, for "Cronie 2" disclosed in 8b8w code, both encoder 112 is provided, also the decoder 138 is provided. 另一方面,对于《Cronie 1》中公开的阿达玛码,可无需明确设置解码器,这是因为该系统可设置为使得接收器132直接生成输出比特。 On the other hand, for "Cronie 1" disclosed in the Hadamard codes, the decoder may not need to explicitly set, this is because the system may be arranged such that the receiver 132 directly to generate the output bits.

[0026] 为了保证所述通信系统的正确运行,必须使发送装置110的操作(包括输入数据100和元件112和118)与接收装置130的操作(包括元件132,可选元件138以及输出数据140) 完全同步化。 [0026] To ensure correct operation of the communication system, the transmission operation of the device 110 must be operating and the receiving device 130 (including the elements (including the elements 112 and input data 100 and 118) 132, optional element 138 and the output data 140 ) completely synchronized. 在一些实施方式中,该同步化由所述发送器和接收器共享的外部时钟实现。 In some embodiments, the synchronization is shared by the transmitter and receiver to achieve the external clock. 在其他实施方式中,与众所周知的用于串行通信的双相编码的情况相同,所述时钟功能可与一条或多条数据信道相结合。 In other embodiments, the well-known case of biphase coding for the same serial communication, the clock function may be combined with one or more data channels.

[0027] 此方面的重要一例为存储接口,在该接口中,在控制器内生成时钟,并与存储器共享。 [0027] The important aspect is one case this memory interface, in the interface, generating a clock within the controller, and shared memory. 该存储器既可将所述时钟信息用于其内部存储操作,也可将其用于输入/输出。 This memory can be the storing clock information for its internal operation, it may be used for input / output. 由于存储操作的突发性和非同步性,所述输入/输出功能并不随时处于可用状态。 Due to the bursty and asynchronous nature, the storage operation input / output function is not always available when needed. 此外,主时钟和数据线路可能因偏斜而互不对齐。 In addition, the master clock and data lines may not be aligned due to the mutually skewed. 在这些情形下,须使用额外的选通信号对何时进行数据读写进行指示。 In these cases, to use an additional strobe signal when data is read for an instruction.

发明内容 SUMMARY

[0028] 公开一种可实现数据与时钟信号传输的正交差分向量信令码,该代码既适合在常规高速CMOS工艺中实施,也适合在DRAM集成电路工艺中实施。 [0028] discloses a method for performing quadrature differential signaling code vector transmitted data and clock signal, the code in the embodiment suitable both for conventional high speed CMOS processes are also suitable embodiments the integrated circuit in a DRAM process. 以下描述了从现有低功率DDR4接口实践中获得的例示信道,以及具有更快速度及更大信号完整性的适度信道改进。 The following describes the embodiment shown the channel obtained from conventional low power interfaces DDR4 practice, with moderate and higher speed and larger channel signal integrity is improved.

附图说明 BRIEF DESCRIPTION

[0029]图1显示了采用向量信令码的通信系统。 [0029] Figure 1 shows a communication system using code vector signaling.

[0030]图2显示了ODVS通信系统的一种实施方式,其中,无需分立的解码功能。 [0030] FIG. 2 shows an embodiment of a communication system ODVS embodiment, wherein no separate decoding.

[0031]图3为一种实施方式的框图,该实施方式利用ODVS码发送数据及时钟信号,并含有可促进接收器与现有DRAM实践的集成的元件。 [0031] FIG. 3 is a block diagram of an embodiment, this embodiment utilizes ODVS code transmission data and a clock signal, and an integrated element comprising a receiver and may facilitate the practice of the conventional DRAM.

[0032]图4为采用5b6w码(也称透翅码)在所提出LPDDR5信道上实施传输的实施方式框图。 [0032] FIG. 4 is employed 5b6w code (also called code tabaniformis) LPDDR5 block diagram of an embodiment of the proposed transmission channel in embodiment.

[0033]图5为采用8b9w码在所提出LPDDR5信道上实施传输的实施方式框图。 [0033] FIG. 5 is a block diagram of an embodiment using code LPDDR5 8b9w transmission channel proposed in the embodiment.

[0034]图6为采用ENRZ码在所提出LPDDR5信道上实施传输的实施方式框图。 [0034] FIG. 6 is a block diagram of an embodiment using ENRZ LPDDR5 channel code transmission proposed in the embodiment.

[0035]图7A,7B和7C所示分别为在6.4G波特和8.4G波特的信令速率下工作的透翅码, ENRZ码和8b9w码实施方式的比较接收眼图。 [0035] Figures 7A, respectively tabaniformis code operating at a signaling rate of 6.4G and 8.4G baud Potter, comparing the received code and eye ENRZ code 8b9w embodiment shown 7B and 7C.

[0036]图8所示为根据至少一个实施例的方法。 The method of at least one embodiment of the [0036] As shown in FIG. 8 according to.

具体实施方式 Detailed ways

[0037] 图1所示为采用向量信令码的通信系统。 [0037] Figure a communication system employing a code vector signaling. 发射器110的输入源数据(图示为S0,S1, S2)通过分块100进入编码器112。 The transmitter data input source 110 (shown as S0, S1, S2) by the block 100 enters the encoder 112. 该分块的大小可变且取决于所述向量信令码的参数。 The variable size of the block depends on the parameters of the vector and the signaling code. 编码器112生成该向量信令码的码字,而且所述系统为针对该向量信令码所设计的系统。 The encoder 112 generates a code word signaling code vector, and the vector system is a system for the design of signaling codes. 运行时,由编码器112生成的所述码字用于控制驱动器118内的PMOS和NMOS晶体管,从而能够在通信信道120的N条通信线路125当中的每条线路上产生两个,三个或更多个不同的电压或电流,以表示所述码字的N个符号。 Running, by the encoder 112 generates the codeword for the PMOS and NMOS transistors 118 controls the drive, it is possible to produce two or three lines on each of the N communication lines 125 of the communication channel 120 among more different voltage or current to represent the N of the codeword symbols. 在通信接收器130内,接收器132读取所述N条线路125中的电压或电流(此过程有可能涉及放大、频率补偿和共模信号消除),并将其结果提供于解码器138,该解码器将所述输入比特重新生成为接收结果140 (图示为R0,R1,R2)。 Within the communication receiver 130, the receiver reads 132 lines N in voltage or current 125 (this process might involve amplification, frequency compensation and common mode canceled), and results are provided in the decoder 138, the decoder input bits reproduced as the reception result 140 (shown as R0, R1, R2). 容易理解的是,不同代码可与不同分块大小和不同码字大小相关联;为了描述的方便性,图1示例为采用ODVS码的系统,但这并不构成任何限制,该代码可编码在四条线路上传输的三个二进制比特值,即所谓的3b4w码。 Readily understood that different code can be different sizes and different block sizes associated codeword; for convenience of description, the example of FIG. 1 is a system employing code ODVS, this does not constitute any limitation, the code may be encoded in three transmission lines on the four binary bit value, i.e., a so-called 3b4w code.

[0038] 根据所使用向量信令码的不同,可不设置解码器,或不设置编码器,或既不设置解码器也不设置编码器。 [0038] Depending on the vector used in the signaling code, the decoder may not be provided, or not provided an encoder, a decoder is not provided, or neither is provided an encoder. 举例而言,对于《Cronie 2》中公开的8b8w码,既设置了编码器112,也同时设置了解码器138。 For example, for "Cronie 2" disclosed in 8b8w code, both encoder 112 is provided, also the decoder 138 is provided. 另一方面,对于《Cronie 1》中公开的H4码(本文中也称为ENRZ码), 可无需明确设置解码器,这是因为该系统可设置为使得接收器132直接生成接收结果140。 On the other hand, for "Cronie 1" in the code disclosed H4 (also referred to herein ENRZ code), the decoder may not need to explicitly set, this is because the system may be arranged such that the receiver receives the results directly generated 140,132. [0039] 为了保证所述通信系统的正确运行,必须使通信发射器110的操作与通信接收器130的操作完全同步化。 [0039] To ensure correct operation of the communication system, the communication transmitter must be operated with the operation of the communication receiver 110 synchronized 130, completely. 在一些实施方式中,该同步化由所述发送器和接收器共享的外部时钟实现。 In some embodiments, the synchronization is shared by the transmitter and receiver to achieve the external clock. 在其他实施方式中,与众所周知的用于串行通信的双相编码的情况相同,所述时钟功能可与所述数据信道中的一条或多条相结合。 In other embodiments, the well-known case of biphase coding for the same serial communication, the clock function may be combined with one or more of the data channels.

[0040] 此方面的重要一例为存储接口,在该接口中,在控制器内生成时钟,并与存储器共享。 [0040] The important aspect is one case this memory interface, in the interface, generating a clock within the controller, and shared memory. 该存储器既可将所述时钟信息用于其内部存储操作,也可将其用于输入/输出。 This memory can be the storing clock information for its internal operation, it may be used for input / output. 由于存储操作的突发性和非同步性,所述输入/输出功能并不随时处于可用状态。 Due to the bursty and asynchronous nature, the storage operation input / output function is not always available when needed. 此外,主时钟和数据线路可能因偏斜而互不对齐。 In addition, the master clock and data lines may not be aligned due to the mutually skewed. 在这些情形下,须使用额外的选通信号对何时进行数据读写进行指示。 In these cases, to use an additional strobe signal when data is read for an instruction.

[0041] 历经数代设计,系统存储控制器与多个动态RAM器件之间的接口在传输速度和低功耗方面已获得极大优化。 [0041] After designing the interface between generations, the system memory controller and the plurality of dynamic RAM devices has been optimized for maximum transmission speed and low power consumption. 现有技术的DRAM接口LPDDR4包括8条数据线,1条DMI信号线,2条选通线,以及其他相关非数据传输线。 LPDDR4 prior art DRAM interface comprises eight data lines, a DMI signal lines, two gate lines, and other related non-data transmission lines.

[0042] 人们对于将LPDDR4扩展至以相同或更少的功耗支持更高性能具有极大兴趣,然而仅对现有技术的性能进行改进似乎存在着问题。 [0042] It will be extended for the same or less LPDDR4 to support higher-performance power of great interest, but only to improve the performance of the prior art appears problematic. 在使用现有单端互连的情况下,如果单单提高数据传输速率,将使得信号完整性降低,从而使得此方式不可行。 In the case of using the conventional single-ended interconnects, only if the higher data rates, such that the signal integrity decreases, so that this method is not feasible. 此外,众所周知,即使在当前的时钟速度下,接收的DRAM数据与其选通信号之间的不能对准仍然是一个问题。 Further, it is known, even in the current clock speed, a DRAM can not be selected from the received data its alignment between the signal remains a problem. 然而,新技术的引入又受到如下限制:人们极其希望尽可能多地保留总线布局、信号分布、时钟设置等方面的现有实践;所述新技术需要满足既可在用于存储控制器的高速CMOS工艺中实施,又可在用于制造具有相对较慢数字和接口逻辑的极小型、高电容、低泄漏存储器单元的高度专用DRAM制造工艺中实施。 However, the introduction of new technology and limited as follows: it is highly desirable to retain as much bus topology, the conventional practice of distribution of signals, the clock setting and the like; the need to meet both new technologies for high-speed memory controller CMOS process embodiments, but also in highly specialized for manufacturing DRAM manufacturing process of very small, high capacitance, low leakage of the memory cell having a relatively slow and interface logic of a digital embodiment.

[0043] 由于此逻辑速度较慢,因此现有的DRAM设计中采用两个或更多处理逻辑阶段处理现有LPDDR4数据传输速率,例如,一个处理逻辑阶段用于捕获数据传输选通信号的上升沿数据,另一处理逻辑阶段用于捕获选通信号的下降沿数据。 [0043] Since this logic is slower, so the conventional DRAM designs employ two or more processing stages prior LPDDR4 processing logic data transmission rate, for example, the processing logic stage for a increase in the captured data strobe signal transfer edge data, processing logic further phase for capturing the falling edge of the data strobe signal. 此类多阶段处理实施方式的一个潜在限制在于其难于从连续接收单元间隔提取差分类信息,这是因为连续单元间隔仅为不同处理阶段下的一个概念。 Such a multi-stage process to limit potential embodiments in that it is difficult from a continuous reception unit extracts a difference interval classification information, because only a concept of continuous cell gap at different processing stages. 因此,对于分别使用依赖于对连续单元间隔内接收的数据值进行比较的跃迀编码数据方案及内嵌时钟式或自时钟式数据方案的两种代码而言,多阶段处理存在问题。 Thus, for each use depends on the data value received consecutive hop comparing unit interval Gan both tags embedded coded data and the program clock from the clock of formula or of formula program data, the multi-stage process problems.

[0044] 在所述通信接收器实施方式中,上述时钟提取及跃迀或变化检测问题最难解决, 因此本文中示例集中于,在所述实施方式中所述相对较慢的DRAM器件为上述接收器。 [0044] In the communication receiver embodiments, the clock extraction and detection of a change or hop Gan most difficult to solve the problem, thus herein focuses on an example, in the embodiment of the device is relatively slow DRAM above receiver. 但是, 这不构成限制,因为熟悉本领域的人员容易理解的是,以DRAM器件实施双向数据通信易于理解,且适于实施DRAM接收的例示实施方式同样也可满足更为简单的发送要求。 However, this does not constitute a limitation, because those skilled in the art readily appreciate that the embodiment of a DRAM device to be readily understood bidirectional data communication, and is adapted to receive a DRAM embodiment shown embodiment also easier to meet the requirements of transmission.

[0045] 使用多输入比较器的接收器 [0045] The use of multiple receiver input of the comparator

[0046] 如《Holden 1》中所述,系数为ao,ai,…,am-1的多输入比较器为一种电路,该电路接收输入向量(XQ,Xl,…,Xm-I),并输出: [0046] The "Holden 1" in the coefficient of ao, ai, ..., the multi-input comparator am-1 there is provided a circuit which receives the input vector (XQ, Xl, ..., Xm-I), and output:

[0047] 结果=(a〇Xxo+H.+am-lXxm-1)试I) [0047] Results = (a〇Xxo + H. + am-lXxm-1) Test I)

[0048] 由于多种实施方式需要输出为二进制值,因此使用模拟比较器对该结果值进行分害J,以生成二进制判定输出。 [0048] Since the various embodiments need to output a binary value, and therefore for the use of analog comparator result value J damage points, to generate a binary decision outputs. 由于用法较为常见,因此所述电路的通俗名称中包括"比较器" 一词,但其他实施方式也可能使用PAM-3或PAM-4分割器获得三进制或四进制输出,或可实际上保留式1的模拟输出,以用于进一步计算。 Since the use of more common, the common name of the circuit thus includes the term "comparator", but other embodiments may also be used or PAM-3 PAM-4 divider obtain output ternary or quaternary, or actual It is left on the analog output 1, for further calculations. 在至少一种实施方式中,根据与用于生成所述ODVS码的非简单正交矩阵或单位矩阵的行对应的子信道向量,选择上述系数。 In at least one embodiment, the vector according to the row corresponding to a subchannel with non-simple orthogonal matrix or a unit for generating the code ODVS matrix, selecting the coefficient.

[0049] 作为一例,根据《Ulrichl》的教示内容,可使用相同四位输入的多输入比较器的三个实例对所述ODVS码(本文称为ENRZ码)进行检测,以执行以下运算: [0049] As an example, according to "Ulrichl" the teachings, examples of using multiple three-input comparator of the same four input ODVS code (referred to herein as ENRZ code) is detected, to perform the following operations:

[0050] RO= (A+C)-(B+D)(式2) [0050] RO = (A + C) - (B + D) (Formula 2)

[0051] Rl = (C+D) - (A+B)(式3) [0051] Rl = (C + D) - (A + B) (Formula 3)

[0052] R2=(C+B)_(D+A)(式4) [0052] R2 = (C + B) _ (D + A) (Formula 4)

[0053]可易于通过系数为[+1,+1,-1,_1]的多输入比较器的三个完全相同的实例以及所述四个输入值的不同排列组合形式执行如式2~4所描述的运算。 [0053] can be readily prepared by coefficient [+ 1, + 1, -1, _1] multi-input comparator and examples of different arrangements of three identical combinations of the four input values ​​to perform the formulas 2 to 4 He described operation.

[0054] ODVS 子信道 [0054] ODVS subchannels

[0055] 通常,将图1编码器112的数据输入视为待原子式地编码为码字的数据向量(即数据字),该码字经信道120传输,然后被接收器132检测,并最终被138解码,从而生成所发送向量或数据字的接收重构形式。 [0055] Generally, the data enter an encoder 112 is considered to be atomically encoded codeword data vector (i.e., the data word), transmitting the codeword via a channel 120, and then 132 detects the receiver, and eventually 138 is decoded, thereby generating a reconstructed form of a vector or receiving the transmitted data word.

[0056] 然而,所述通信系统可以稍微不同的方式但以同等的准确性进行建模。 [0056] However, the communication system may be slightly different but equivalent ways to model accuracy. 由于此替代模型可在无需其他解码器的系统中得到最好的理解,为了描述目的,采用基于图2所示的ENRZ码的具体实施方式,但这不构成限制。 Since this alternative model may best be understood in the decoder without additional systems, for descriptive purposes, based DETAILED DESCRIPTION ENRZ code shown in FIG. 2, but this is not limiting. 图2中,与图1元件功能相同的元件采用相同编号,但图2在下文中还展示了其他内部结构以及图1中泛述的组成特征。 In FIG. 2, the same functional elements in FIG. 1 with the same element number, but also in FIG. 2 below shows the composition of the features described in the pan, and other internal structures FIGS.

[0057]图2中,进入通信发射器110的输入数据向量100明确示为扩展为其各个比特S^S1, S2并进入编码器112。 In [0057] FIG 2, the transmitter enters the communication data vector input 110 of extension 100 is explicitly shown for each bit S ^ S1, S2 and into the encoder 112. 表示编码器112的输出码字符号的各个信号示为对各个线路驱动器118进行控制,以使其向包括通信信道120的线路125发射信号。 Indicates the respective signal output codeword symbols of the encoder 112 is shown for the respective line driver 118 is controlled so as to transmit a signal line 125 includes a communication channel 120. 由于任何一条传输所述ENRZ 码的线路均可取四个不同信号值当中的一个值,因此每条线路的线路驱动器均示为由两个控制信号控制。 Since any one of the transmission lines can take ENRZ a code value from among the four different signal values, and therefore each line driver circuit are shown by the two control signal.

[0058]如上所述,在此实施方式中,通信接收器130无需明确设置解码器。 [0058] As described above, in this embodiment, the communication receiver decoder 130 need not explicitly set. 接收器132的内部结构图示为包括从线路125接收信号的四个接收前端(如131),而且根据通信信道120的特性的要求,可选包括放大和均衡功能。 Illustrating an internal configuration of the receiver 132 comprises a receiver front-end from four (e.g., 131) the received signal line 125, and according to required characteristics of a communication channel 120, optionally including amplification and equalization. 如图所示,三个多输入比较器的输入端连接于式2, 式3和式4所述的四个接收线路信号。 As shown, more than three-input comparator is connected to the input terminal 2, and a signal receiving line four Formula 4 Formula 3 Formula. 为了避免混淆,所述多输入比较器如图所示为包括计算功能133以及其后的分割功能134,该分割功能自所述输入值的运算组合中产生数字输出RO,R1,R2〇 To avoid confusion, the multi-input comparator 134 shown in FIG arithmetic combining function from the input value of the segmentation to generate a digital output RO comprises calculating function 133 and the subsequent division function, Rl, R2〇

[0059] 熟悉本领域的技术人员可注意到的是,所述ODVS编码器接收一组输入数据并在每个发送单元间隔内输出一个码字。 [0059] Those skilled in the art can be noted that the ODVS encoder receives a set of input data and outputs a codeword in each unit transmission interval. 如果与上述多种实施方式中的情形一样,所述编码器包括组合数字逻辑(即无额外内部状态),则此周期性码字输出可易于视作在编码变换、后续传输等之前向所述输入数据实施的采样功能。 If as in the above embodiment is the case in various embodiments, the encoder comprises a combination of digital logic (i.e., no additional internal state), this periodic output codeword deemed to be easily transformed prior to encoding said subsequent transmission, input data sampling function implemented. 类似地,如果与此处所述由多输入比较器执行检测的情形一样,所述接收器内的检测运算同样为组合运算,则给定输出元素的状态仅由一定数量的信道线路上的接收信号电平确定。 Similarly, if the multi-input case where the detection is performed by the comparator as the detection operation of the receiver in the same state as the combination calculation, then the given output element received only by a certain number of channels on the line signal level determination. 因此,每个独立信号输入(例如So)及其等效独立信号输出(如Ro)均可视为虚拟通信信道,本文称其为所述ODVS编码系统的"子信道"。 Thus, each individual input signal (e.g., So) output independent signals and their equivalents (e.g., Ro) can be considered as a virtual communication channel, herein referred to as the encoding system ODVS "subchannels." 给定子信道既可以为二进制信道(即传送双状态值),也可表示更高阶的值。 Given that both binary channel subchannel (i.e., dual status value transfer), may represent the value of a higher order. 实际上,正如《Shokrollahi4》中所述,给定ODVS码的子信道的独立性足以使其采用不同码集(及码集大小)描述其所传送的值。 In fact, as "Shokrollahi4" said, given the independence of a subchannel codes ODVS value sufficient to set a different code (and a code set size) it transmits described.

[0060] ODVS系统内包括子信道内的状态变化在内的所有数据通信均以码字形式在整个信道内发送。 [0060] All the data communication system comprises ODVS state changes within a subchannel including the codewords are transmitted in the form of the whole channel. 在一种实施方式中,如《Holden 1》和《Ulrich 1》中所述,可将输入值的特定映射与码字相关联,并将这些映射与特定检测器结果相关联,但此类关联不应与通信介质本身的分区、子分区或子信道相混淆。 In one embodiment, such as "Holden 1" and "Ulrich 1" particular mapping associated with said codeword, the input values ​​and maps them with a particular detector associated results, but such an association the communication medium itself should not partition, or sub-sub-partitions confused.

[0061] ODVS子信道的概念并不因上述例示实施方式而限制于特定ODVS代码、发射器实施方式或接收器实施方式。 [0061] ODVS subchannel concept is not due to the above illustrated embodiments but limited to the specific embodiment ODVS code transmitter implementation or receiver implementation. 保持内部状态的编码器和/或解码器也可为实施方式的部件。 Maintaining the internal state of the encoder and / or decoder may also be part of the embodiment. 子信道既可由各个信号表示,也可由多个信号传送的状态表示。 Each subchannel is represented by a signal can also be represented by the state of the plurality of signal transmission.

[0062] 子信道内的定时信息 [0062] The timing information within a subchannel

[0063] 由于ODVS通信系统必须将数据输入的每种组合以编码传输的形式进行发送,而且此类编码传输的速率必然受通信介质的容量限制,因此待传输数据的变化速率必须处于奈奎斯特极限之内,其中,码字的传输速率表示采样间隔。 [0063] Since the communication system must ODVS each combination of input data is transmitted in the form of coded transmission, and such coded transmission rate inevitably restricted by the capacity of the communications medium, thus to be the rate of change in transmitted data must Nyquist Laid limits within which the transmission rate code word represents the sampling interval. 举例而言,如果二进制时钟或选通信号在每个码字传输时的时钟边沿数不超过一个,则其可在ODVS子信道内传输。 For example, if the number of clock edges of a clock or strobe binary each codeword transmission at no more than one, it can be transmitted in a subchannel ODVS.

[0064] 在ODVS编码器和关联线路驱动器的一种实施方式中,其可在数据输入中发生任何变化时以非同步方式工作。 It operates in an asynchronous manner [0064] that any change in the data can be input in one embodiment ODVS and associated encoder when the line driver. 在其他实施方式中,可例如通过内部定时时钟将多个数据处理阶段相结合,以生成单个高速输出流。 In other embodiments, for example, by an internal timing clock to the plurality of data processing stages are combined to generate a single high-speed output stream. 在此类实施方式中,码字所有元素的输出均以内在同步的方式进行,因此所述代码子信道内传送的选通或时钟信号在所述接收器处表现为数据对准式时钟(例如,其跃迀边沿与该代码其他子信道内的数据边沿同步)。 , The elements of the output codeword are all carried out in such a manner inherent synchronization embodiment, the strobe or clock signal is therefore transmitted in the subchannel codes in performance at the receiver clock with the alignment data (e.g. , which is synchronized with the edge jump Gan data edge in the other subchannel codes). 在无时钟或非同步实施方式中也通常设定类似的定时关系。 In the non-synchronized clock or embodiment is also generally similar to the set timing relationship.

[0065] 图3为ODVS通信系统的框图,在该系统内,子信道内承载数据对准式选通信号(类似于与已知LPDDR4信道相关联的选通信号),而该代码的其他子信道承载N个比特的数据。 [0065] FIG. 3 is a block diagram of a communication system ODVS, within the system, carries the data strobe signal is aligned Formula (similar strobe associated with known LPDDR4 channel) within the sub, the sub-codes other channel carries the N-bit data. 在接收器内,一系列多输入比较器132对所接收信息进行检测,并输出数据345及所接收的数据对准式选通信号346。 In the receiver, a series of multi-input comparator 132 detects the received information, and outputs the data 345 and data-aligning the received strobe signal 346. 此外,通过引入半个单元间隔的延时350,使所接收的选通信号发生偏移,以生成眼图对准式选通信号356,该信号的跃迀边沿处于最佳采样时间,从而实现数据345的锁存。 Further, by introducing a delay of half a cell gap 350, so that the received strobe shifted to produce eye-aligning strobe 356, Yue Gan edge of the signal at the optimum sampling time, in order to achieve a data latch 345. 作为多种DRAM实施方式中的一种通常做法,图示中为用于数据采样的两个处理阶段:处理阶段360对眼图对准式选通信号356负边沿上的数据345进行采样,而处理阶段370对眼图对准式选通信号356正边沿上的数据345进行采样。 As various embodiments of DRAM common practice, illustrated in two processing stages for data sampling: the processing stage 360 ​​eye view of the alignment of formula negative data strobe signal 356 is sampled on the rim 345, and 356 on the positive edge of the data processing stage 370 eye view of the alignment of formula strobe signal 345 is sampled. 通过LPDDR接口实现延时350的方法及其可能所需的任何关联调整或校准手段均为本领域所熟知。 It means any association adjustment or calibration method 350 LPDDR interface that may be needed by the time delay and are known in the art.

[0066] LPDDR通信至ODVS系统的映射 [0066] mapped to LPDDR communication system ODVS

[0067] 现有的LPDDR4规范规定了8条数据线路,1条DMI线路以及2条选通线路,共11条线路。 [0067] LPDDR4 existing specification data of eight lines, a DMI lines and strobe lines 2, a total of 11 lines. 利用ODVS编码,可通过数种方式将这些现有连接映射至一种新的协议模式,本文称为LH)DR5。 ODVS using code that may be mapped to an existing connection, a new protocol model several ways, herein referred to as LH) DR5.

[0068] 根据《Holdenl》的教示内容,多输入比较器的噪声特性取决于其输入端尺寸及配置。 [0068] The "Holdenl" the teachings, the multi-input comparator noise characteristic depending on its size and configuration input. 根据《Shokrollahi 4》的教示内容,式1中各种运算所产生的信号幅度可表示不同接收眼图特性。 The "Shokrollahi 4" of the teachings, the signal amplitude of Formula 1 in various calculations generated eye diagram may represent different characteristics. 因此,在优选实施方式中,当可用子信道的特性可变时,将指定质量较高(如眼开度较大)的子信道承载时钟、选通或其它定时信息。 Thus, in a preferred embodiment, when the variable characteristics of available sub-channels, the higher the quality specified (e.g., larger eye opening) subchannel carries clock, strobe, or other timing information.

[0069] 透翅码 [0069] Code tabaniformis

[0070] 第一实施方式在本文中称为透翅Oilasswing)码并示于图4的框图中,该实施方式新增1条线路,从而共提供12条线路,这些线路以逻辑方式分为两个六线组。 [0070] In a first embodiment, referred to herein as tabaniformis Oilasswing) code and a block diagram shown in FIG. 4, a new route to this embodiment, providing a total of 12 lines that are logically divided into two six-line groups. 每个六线组用于承载ODVS码的一个实例,以在6条线路上传输5个比特(以下称为5b6w码),从而共提供10 条子信道。 Each six-line group for example a bearer ODVS code, for transmission over line 5 6 bits (hereinafter referred 5b6w code), providing a total of 10 subchannels. 其中,8条子信道用于承载8个数据比特,1条子信道用于承载掩码比特(通常在DRAM写操作期间用于防止单独字节写入),还有1条子信道用于承载数据对准式选通信号。 Wherein eight subchannels used to carry eight data bits, a sub-channel for carrying a mask bit (usually written in the DRAM during an operation for preventing the individual byte write), there is a sub-channel for carrying the data alignment formula strobe signal. 该5b6w码为平衡码,任何给定码字内的所有符号的和为零,而且其构造使得每个码字恰好包含一个+1和一个-1,而其余码字符号包括符号+1/3和-1/3。 The balanced code is a code 5b6w, all symbols within any given codeword is zero, and configured such that each codeword contains exactly a +1 and a -1, and the remaining codeword symbols including symbols + 1/3 and -1/3. 对于本领域的技术人员而言容易理解的是,实施方式中可使用合适码字集合的多种排列组合形式以及相应的比较器检测系数。 For those skilled in the art will readily be appreciated that the embodiment using a suitable set of codewords corresponding to various permutations and combinations of the comparator detects coefficients.

[0071] 透翅码中,每个5b6w接收器包括五个多输入比较器。 [0071] tabaniformis code, each 5b6w receiver comprises more than five-input comparator. 在一种优选实施方式中,5b6w 码的每个实例的码字如表1所示,而且所述一组比较器为: In one preferred embodiment, 5b6w code word of each code shown in Table 1 as example, the comparator and the set of:

Figure CN106576087AD00101

[0072] [0072]

[0073] [0073]

[0074] [0074]

[0075] [0075]

[0076] [0076]

[0077] [0077]

[0078] [0078]

[0079] 表1 [0079] TABLE 1

[0080] 5b6w码的其他信息可参见《Ulrich 2》。 Other Information [0080] 5b6w code can be found in "Ulrich 2".

[0081] 8b9w 码 [0081] 8b9w code

[0082] 第二实施方式在本文中称为"8b9w"码并示于图5的框图中,该实施方式保留现有LPDDR4的11条数据传输线路。 [0082] In the second embodiment referred to herein as "8b9w" code and is shown in block diagram in FIG. 5, this embodiment retains the LPDDR4 conventional data transmission line 11. 其中,9条线路用于承载8b9w码,该码本身包含本文称为4.5b5w码的五线码,以及本文称为3.5b4w码的四线码,此两种代码合并提供288个不同码字组合,编码器使用其中的257个。 Wherein 8b9w nine lines for carrying a code, the code itself is referred to herein as comprising five lines of code 4.5b5w code, and herein referred to as four-wire code 3.5b4w code, merge these two codes to provide 288 different combinations of code words , wherein the encoder uses 257. 在这257个码字当中,256个码字用于在掩码输入为假时编码8个比特数据,而另1个码字用于在掩码输入为真时标记"不写入"这一条件。 In this 257 yards words among 256 code words for encoding the input mask is false 8-bit data, and the other one code word for the input mask is true flag "is not written," the condition. 数据对准式选通信号利用现有手段发送,即使用上述两条现有的LPDDR4选通线路。 Data strobe signal is aligned using the conventional type transmission means, i.e., using the conventional two LPDDR4 strobe lines.

[0083] 在至少一种实施方式中,每个4.5b5w接收器包括七个多输入比较器,其使用如表2 所示的4.5b5w码的码字以及以下一组比较器: [0083] In at least one embodiment, each receiver comprises more than seven 4.5b5w input comparator, using a code word table as the code shown in FIG. 2 4.5b5w a set of comparators and the following:

Figure CN106576087AD00111

[0084] [0084]

[0085] [0085]

[0086] [0086]

[0087] [0087]

[0088] [0088]

[0089] [0089]

[0090] [0090]

[0091] [0091]

[0092] [0092]

[0093] 表2 [0093] TABLE 2

[0094] 前6个比较器的符号间干扰比为2,而最后一个比较器的符号间干扰比为1 (见《Hormati 1》)。 [0094] The first six inter-symbol interference ratio of the comparator 2, and the last inter-symbol interference is a comparator (see "Hormati 1") ratio.

[0095] 在该实施方式中,所述3.5b4w码的码字如表3所示。 [0095] In this embodiment, the codeword 3.5b4w code shown in Table 3.

[0096] [0096]

Figure CN106576087AD00112

[0097] 表3 [0097] TABLE 3

[0098] 每个3.5b4w接收器包括六个多输入比较器。 [0098] Each receiver comprises more than six 3.5b4w input comparator. 如果每个四线组的线路表示为xO, xl... χ3,则所述比较器为: If each line is represented as a four-line group xO, xl ... χ3, then the comparator is:

[0099] χΟ-χΙ [0099] χΟ-χΙ

[0100] χ〇-χ2 [0100] χ〇-χ2

[0101] χ〇-χ3 [0101] χ〇-χ3

[0102] χ1-χ2 [0102] χ1-χ2

[0103] χ1-χ3 [0103] χ1-χ3

[0104] χ2-χ3 [0104] χ2-χ3

[0105] 所有上述比较器的符号间干扰比为2(见《Hormati 1》)。 [0105] All the above-described intersymbol interference ratio comparator 2 (see "Hormati 1").

[0106] ENRZ 码 [0106] ENRZ code

[0107] 第三实施方式在本文中称为"ENRZ"码并示于如图6所示的框图中,该实施方式在现有LPDDR4方案中新增1条线路,从而共提供12条线路,这些线路以逻辑方式分为三个四线组。 [0107] In the third embodiment referred to herein as "ENRZ" code and is shown in the block diagram shown in FIG. 6, this embodiment is a new line in the prior LPDDR4 embodiment, providing a total of 12 lines, these lines are logically divided into three quads. 每个四线组用于承载ENRZ码的一个实例,因此每个实例具有八个唯一码字。 Each for carrying a four-line group code ENRZ example, each instance has a unique eight codewords. 在至少一种实施方式中,每个实例的一个码字保留为重复码,而每个实例的7个剩余码字由编码器组合,以提供7X7X7 = 343个唯一组合形式,从而足以编码上例所述的8个数据比特及一个掩码条件。 In at least one embodiment, one instance of each codeword repetition code is reserved, while the seven remaining codewords in each instance by the encoder combined to provide 7X7X7 = 343 unique combinations, sufficient to encode the embodiment the eight data bits and a mask condition. 在另一实施方式中,不指定重复码字。 In another embodiment, the repeated codeword is not specified. 相反的,如《Shokrollahi3》中所述,发射器可将最后发送的码字保存,并为下一单位间隔(UI)生成与所发送码字不同的码字。 In contrast, as "Shokrollahi3" in the transmitter may be transmitted to save the last codeword, and generates different codewords transmitted for the next unit interval (UI). 所述数据对准式选通信号用于为发射器的码字发射定时,而且每当当前待发送码字与前一单元间隔所发送的码字相同时,则发送每个实例的重复码。 The data strobe signal is aligned formula codeword for transmission timing for the transmitter, and the current code word to be transmitted every time the code word from the previous cell transmission intervals are the same, the repetition code is sent to each instance. 在接收机器中,使用本领域已知的时钟恢复电路从所接收码字的边沿提取定时信息,并由一个数据值历史缓冲器在检测到所接收重复码字时重新生成所复制的数据值。 In the receiving machine, known in the art clock recovery circuit extracts the timing information from a received codeword rim by a value of the history buffer data is detected in the received data value is repeatedly regenerated duplicated codeword.

[0108] 此实施方式的进一步描述可参见《Shokrollahi3》。 [0108] Further description of this embodiment can be found in "Shokrollahi3".

[0109] 图7A,7B和7C所示为各种实施方式的比较,其中所示透翅码,ENRZ码和8b9w实施方式的接收眼图分别得自6.4G波特和8.4G波特的信令速率。 [0109] Figures 7A, is a comparison of the various embodiments, wherein the receiving eye lens shown in FIG wings code, ENRZ code and 8b9w embodiment illustrated embodiment are available from Potter and 6.4G 8.4G Potter letters 7B and 7C order rates.

[0110] 本文实施例描述了向量信令码在点对点线路通信中的使用。 [0110] Example embodiments described herein vector signaling point codes used in the communication line. 然而,这不应视为对所描述实施方式的范围进行了任何限制。 However, this should not be seen as the embodiment described any limiting scope. 本申请中所公开的方法同样适用于包括光学和无线通信在内的其他通信介质。 The method disclosed in this application are equally applicable to other media including optical communication and wireless communication, including. 因此,"电压"和"信号电平"等描述性词语应视为包括其在其他度量系统中的同等概念,如"光强"、"射频调制"等。 Accordingly, "voltage" and the "signal level" and the like are words of description should be considered include its metric equivalent systems in other concepts, such as "light intensity", "RF modulator" and the like. 本文所使用的"物理信号"一词包括可传送信息的物理现象的任何适用形态和/或属性。 The term "physical signals" as used herein includes any suitable form of physical phenomena may transmit information and / or attributes. 此外,此类物理信号可以为有形的非暂时性信息。 Further, such physical signal may be a non-transitory tangible information.

[0111] 实施方式 [0111] Embodiment

[0112] 在至少一种实施方式中,一种方法800包括:在步骤802中,在多个多输入比较器(MIC)处接收向量信令码的码字的一个符号集,所述符号集表示以非简单正交矩阵或单位矩阵对输入向量所做的变换,所述输入向量包括多条子信道,其中,至少一条子信道对应于输入数据信号,而且至少一条子信道对应于数据对准式选通信号;在步骤804中,根据所述码字的多个符号子集之间的多个比较,形成一组多输入比较器输出信号,其中,对于每个比较,每个符号子集具有由相应多输入比较器决定且施加于该符号子集的一组输入系数,所述一组多输入比较器输出信号包括至少一个数据输出信号以及至少一个所接收的数据对准式选通信号;以及在步骤806中,根据所述至少一个所接收的数据对准式选通信号对所述至少一个数据输出信号进行采样。 [0112] In at least one embodiment, a method 800 comprises: In step 802, a received codeword symbol set vector signaling code (MIC) at a plurality of multi-input comparator, said set of symbols represents a non-simple orthogonal transform matrix or matrix made of the input vector, the input vector comprising a plurality of subchannels, wherein the subchannels corresponding to the at least one data signal input, and at least one sub-channel corresponding to the data alignment formula strobe; in step 804, a plurality of subsets of symbols among the plurality of the codeword comparison, form a set of multi-input comparator output signal, wherein, for each comparison, each symbol subset having determined by a respective plurality of comparator inputs and a set of input coefficients is applied to the set of sub-symbols, the set of multi-input comparator output signal comprises at least one data output signal and at least one type of the received data strobe signal is aligned; and in step 806, the data received by the at least one strobe-aligning the at least one data output signal is sampled.

[0113] 在至少一种实施方式中,在所述至少一个所接收的数据对准式选通信号的上升沿采样所述至少一个数据输出信号。 [0113] In at least one embodiment, at least one of the rising edge of the received data strobe signal-aligning samples of the at least one data output signal. 在另一实施例中,在所述至少一个所接收的数据对准式选通信号的下降沿采样所述至少一个输出数据信号。 In another embodiment, the at least a falling edge of the sampling of the received data alignment in the formula at least one strobe output data signal.

[0114] 在至少一种实施方式中,所述输入向量包括对应于输入数据信号的4条子信道以及对应于数据对准式选通信号的1条子信道。 [0114] In at least one embodiment, the input vector data corresponding to the input signal comprises four subchannels of a subchannel and data corresponding to the alignment of formula strobe signal. 在至少一种实施方式中,所述符号集中的每个符号具有选自由至少两个值组成的集合中的值。 In at least one embodiment, each symbol of the symbol set having at least two values ​​selected from the group consisting of a free set. 在另一实施方式中,所述符号集中的每个符号具有选自值集{+1,+1/3,-1/3,-1}的值。 In another embodiment, the concentration of each of the symbols has a value selected from the set {1/3 + 1 + -1 / 3, -1} values.

[0115] 在至少一种实施方式中,每个多输入比较器的所述一组输入系数均由所述非简单正交矩阵或单位矩阵决定。 [0115] In at least one embodiment, each multi-input of the comparator input coefficients by a set of orthogonal matrices or the non-simple decision matrix.

[0116] 在至少一种实施方式中,所述码字为均衡码字。 [0116] In at least one embodiment, the codeword is balanced codeword.

[0117] 在至少一种实施方式中,该方法还包括通过分割所述一组多输入比较器输出信号形成一组输出比特。 [0117] In at least one embodiment, the method further comprises dividing the set of multi-input comparator output signal to form a set of output bits.

[0118] 在至少一种实施方式中,该方法还包括:从多条线路上接收所述输入向量;使用编码器生成所述码字的符号集,该符号集表示子信道向量的加权和,所述子信道向量对应于所述非简单正交矩阵或单位矩阵的行,其中,每个子信道向量的加权值由相应的输入向量子信道决定;以及将所述码字的符号提供于多线路总线。 [0118] In at least one embodiment, the method further comprising: receiving the input vector from the plurality of lines; symbol set using the encoder generates the codeword, which represents the weighted set of symbols and subchannels vector, the sub-vectors corresponding to the non-simple orthogonal matrix or a unit matrix rows, wherein a weight value of each sub-vector is determined by the respective subchannel input vector; and the symbols of the codeword is provided to a multi-line bus.

[0119] 在至少一种实施方式中,一种装置包括:多线路总线,用于接收向量信令码的码字的一个符号集,所述符号集表示以非简单正交矩阵或单位矩阵对输入向量所做的变换,所述输入向量包括多条子信道,其中,至少一个条所述信道对应于输入数据信号,而且至少一条所述子信道对应于数据对准式选通信号;多个多输入比较器(MIC),用于根据所述码字的多个符号子集之间的多个比较,形成一组多输入比较器输出信号,其中,对于每个比较,每个所述符号子集具有由相应的多输入比较器决定且施加于该符号子集的一组输入系数,所述一组多输入比较器输出信号包括至少一个数据输出信号以及至少一个所接收的数据对准式选通信号;以及多个采样电路,用于根据所述至少一个所接收的数据对准式选通信号对所述至少一个数据输出信号进行采样。 [0119] In at least one embodiment, an apparatus comprising: a multi-line bus, a symbol set for the received codeword vector signaling code, the symbol set represents a non-orthogonal matrix or simply matrix units input transform vector made, the input vector comprising a plurality of subchannels, wherein at least one strip of said channel corresponding to the input data signal, and at least one of the subchannels corresponding to the data strobe signal-aligning; a plurality of multi- input of the comparator (the MIC), for comparison, to form a set of multi-input comparator output signals, wherein, for each comparison, each of the plurality of symbols between the plurality of sub-symbols according to a subset of the code word set having a set of input coefficients is determined by the corresponding multi-input comparator and applied to the subset of symbols, the set of multi-input comparator output signal comprises at least one data output signal and the at least one received data alignment formula selected from signal; and a plurality of sampling circuits, according to the at least one data-aligning the received strobe signal to the at least one data output signal is sampled.

[0120] 在至少一种实施方式中,至少一个采样电路用于在所述至少一个所接收的数据对准式选通信号的上升沿采样所述至少一个数据输出信号。 [0120] In at least one embodiment, the at least one sampling circuit for sampling the rising edge of the data strobe signal-aligning the at least one received at least one data output signal. 在另一实施方式,至少一个采样电路用于在所述至少一个所接收的数据对准式选通信号的下降沿采样所述至少一个输出数据信号。 In another embodiment, at least one sampling circuit for sampling the falling edge of the data strobe signal-aligning at least one of said at least one output of the received data signal.

[0121] 在至少一种实施方式中,所述输入向量包括对应于输入数据信号的4条子信道以及对应于数据对准式选通信号的1条子信道。 [0121] In at least one embodiment, the input vector data corresponding to the input signal comprises four subchannels of a subchannel and data corresponding to the alignment of formula strobe signal. 在至少一种实施方式中,所述符号集中的每个符号具有选自由至少两个值组成的集合中的值。 In at least one embodiment, each symbol of the symbol set having at least two values ​​selected from the group consisting of a free set. 在另一实施方式中,所述符号集中的每个符号具有选自值集{+1,+1/3,-1/3,-1}的值。 In another embodiment, the concentration of each of the symbols has a value selected from the set {1/3 + 1 + -1 / 3, -1} values.

[0122] 在至少一种实施方式中,每个多输入比较器的所述一组输入系数均由所述非简单正交矩阵或单位矩阵决定。 [0122] In at least one embodiment, each multi-input of the comparator input coefficients by a set of orthogonal matrices or the non-simple decision matrix.

[0123] 在至少一种实施方式中,所述码字为均衡码字。 [0123] In at least one embodiment, the codeword is balanced codeword.

[0124] 在至少一种实施方式中,该装置还包括多个分割器,用于通过分割所述一组多输入比较器输出信号形成一组输出比特。 [0124] In at least one embodiment, the apparatus further comprises a plurality of divider for dividing by the set of multi-input comparator output signals form a set of output bits.

[0125] 在至少一种实施方式中,一种装置包括:多条线路,用于接收所述输入向量,该输入向量包括多条子信道,其中至少一条所述子信道对应于数据信号,且至少一条所述子信道对应于数据对准式选通信号;编码器,用于生成所述码字的符号集,该符号集表示子信道向量的加权和,所述子信道向量对应于所述非简单正交矩阵或单位矩阵的行,其中,每个所述子信道向量的加权值由相应的输入向量子信道决定;以及多个线路驱动器,用于向多线路总线发送所述码字的所述符号。 [0125] In at least one embodiment, an apparatus comprising: a plurality of lines for receiving the input vector, the input vector comprising a plurality of subchannels, wherein the subchannels corresponding to the at least one data signal, and at least the data corresponding to a sub-aligning strobe signal; an encoder for generating a codeword symbol sets, which represents a weighted set of symbols and subchannels vector, the vector corresponding to the non subchannels simple orthogonal matrix row or a matrix, wherein the weighting value for each vector of said subchannel by subchannel corresponding decision input vector; and a plurality of line drivers, to a multi-line bus for the transmission of the codeword said symbol.

Claims (15)

1. 一种方法,其特征在于,包括: 在多个多输入比较器处接收向量信令码的码字的一个符号集,所述符号集表示以非简单正交矩阵或单位矩阵对输入向量所做的变换,所述输入向量包括多条子信道,其中,至少一条所述子信道对应于输入数据信号,而且至少一条所述子信道对应于数据对准式选通信号; 根据所述码字的多个符号子集之间的多个比较,形成一组多输入比较器输出信号,其中,对于每个比较,每个所述符号子集具有由相应的多输入比较器决定且施加于该符号子集的一组输入系数,所述一组多输入比较器输出信号包括至少一个数据输出信号以及至少一个所接收的数据对准式选通信号;以及根据所述至少一个所接收的数据对准式选通信号对所述至少一个数据输出信号进行米样。 1. A method, comprising: receiving a codeword vector symbol set of signaling codes in a plurality of multi-input comparator, the set of symbols represented in the non-simple orthogonal matrix or matrix of the input vector conversion done, the input vector comprising a plurality of subchannels, wherein the subchannels corresponding to the at least one data signal input, and at least one of the subchannels corresponding to the data strobe signal is aligned formula; according to the codeword comparison between a plurality of subsets of the plurality of symbols to form a set of multi-input comparator output signals, wherein, for each comparison, each of the symbol subsets having a respective plurality is determined by the input applied to the comparator and a set of input coefficients subset of symbols, the set of multi-input comparator output signal comprises at least one data output signal and the at least one received data-aligning the strobe signal; and data according to the received at least one of quasi formula strobe signal to the at least one data output signal rice samples.
2. 如权利要求1所述的方法,其特征在于,在所述至少一个所接收的数据对准式选通信号的上升沿采样所述至少一个数据输出信号。 2. The method according to claim 1, wherein the at least one rising edge of the sampling in the received data strobe signal-aligning the at least one data output signal.
3. 如权利要求1所述的方法,其特征在于,在所述至少一个所接收的数据对准式选通信号的下降沿采样所述至少一个输出数据信号。 The method according to claim 1, wherein the at least a falling edge of the sampling of the received data alignment in the formula at least one strobe output data signal.
4. 如权利要求1所述的方法,其特征在于,所述输入向量包括对应于输入数据信号的4 条子信道以及对应于所述数据对准式选通信号的1条子信道。 4. The method according to claim 1, wherein said input vector comprises four sub-channels corresponding to the input data signal, and a subchannel corresponding to the data strobe signal-aligning.
5. 如权利要求4所述的方法,其特征在于,所述符号集中的每个符号具有选自值集{+1, +1/3,-1/3,-1}的值。 5. The method as claimed in claim 4, wherein values, wherein each of the symbols selected from set value set {+ 1/3 - 1/3, -1, +1}.
6. 如权利要求1所述的方法,其特征在于,每个多输入比较器的所述一组输入系数均由所述非简单正交矩阵或单位矩阵决定。 6. The method according to claim 1, characterized in that each of said multi-input comparator input coefficients by a set of orthogonal matrices or the non-simple decision matrix.
7. 如权利要求1所述的方法,其特征在于,还包括通过分割所述一组多输入比较器输出信号形成一组输出比特。 7. The method according to claim 1, characterized by further comprising dividing the set of multi-input comparator output signal to form a set of output bits.
8. 如权利要求1的所述方法,其特征在于,还包括: 从多条线路上接收所述输入向量; 使用编码器生成所述码字的符号集,所述符号集表示子信道向量的加权和,所述子信道向量对应于所述非简单正交矩阵或单位矩阵的行,其中,每个所述子信道向量的加权值由相应的输入向量子信道决定;以及将所述码字的所述符号提供于多线路总线。 8. The method as claimed in claim 1, characterized in that, further comprising: receiving the input vector from the plurality of lines; using an encoder to generate said codeword symbol set, the set of symbols represented subchannel vectors and weighting the sub-vector corresponds to a row of said matrix or non-simple orthogonal matrix, wherein the weighting value for each of the subchannels determined by the subchannel vector corresponding to input vector; and the codeword the symbols provided in a multi-line bus.
9. 一种装置,其特征在于,包括: 多线路总线,用于接收向量信令码的码字的一个符号集,所述符号集表示以非简单正交矩阵或单位矩阵对输入向量所做的变换,所述输入向量包括多条子信道,其中,至少一条所述子信道对应于输入数据信号,而且至少一条所述子信道对应于数据对准式选通信号; 多个多输入比较器,用于根据所述码字的多个符号子集之间的多个比较,形成一组多输入比较器输出信号,其中,对于每个比较,每个所述符号子集具有由相应的多输入比较器决定且施加于该符号子集的一组输入系数,所述一组多输入比较器输出信号包括至少一个数据输出信号以及至少一个所接收的数据对准式选通信号;以及多个采样电路,用于根据所述至少一个所接收的数据对准式选通信号对所述至少一个数据输出信号进行采样。 9. An apparatus, characterized by comprising: a multi-line bus, a symbol set for the received codeword vector signaling code, the symbol set represents a non-orthogonal matrix or simply matrix made on an input vector transform, the input vector comprising a plurality of subchannels, wherein the subchannels corresponding to the at least one data signal input, and at least one of the subchannels corresponding to the data strobe signal-aligning; a plurality of multi-input comparator, for comparison, forming a set of multi-input comparator output signals, wherein, for each comparison, each of the subset of symbols having a plurality of symbols among the plurality of subsets of the code word by the respective plurality of input and applied to the comparator determines a set of input coefficients of the subset of symbols, the set of multi-input comparator output signal comprises at least one data output signal and the at least one received data strobe signal is aligned formula; and a plurality of sampling circuit for the at least one data-aligning the received strobe signal to the at least one data output signal is sampled.
10. 如权利要求9所述的装置,其特征在于,至少一个采样电路用于在所述至少一个所接的收数据对准式选通信号的上升沿采样所述至少一个数据输出信号。 10. The apparatus according to claim 9, characterized in that at least one sampling circuit for sampling the rising edge at the at least one contact-aligning received data strobe signal to at least one data output signal.
11. 如权利要求9所述的装置,其特征在于,至少一个采样电路用于在所述至少一个所接收的数据对准式选通信号的下降沿采样所述至少一个输出数据信号。 11. The apparatus according to claim 9, characterized in that at least one sampling circuit for sampling the falling edge of the data strobe signal-aligning at least one of said at least one output of the received data signal.
12. 如权利要求9所述的装置,其特征在于,所述输入向量包括对应于输入数据信号的4 条子信道以及对应于数据对准式选通信号的1条子信道。 12. The apparatus according to claim 9, wherein said input vector comprises four sub-channels corresponding to the input data signal, and a subchannel corresponding to the data strobe signal-aligning.
13. 如权利要求9所述的装置,其特征在于,所述符号集中的每个符号具有选自值集{+ 1,+1/3,-1/3,-1}的值。 13. The apparatus according to claim 9, wherein each of the symbols selected from set value set {+ 1, + 1/3 - 1/3, -1} values.
14. 如权利要求9所述的装置,其特征在于,每个多输入比较器的所述一组输入系数均由所述非简单正交矩阵或单位矩阵决定。 14. The apparatus according to claim 9, characterized in that each of said multi-input comparator input coefficients by a set of orthogonal matrices or the non-simple decision matrix.
15. 如权利要求9所述的装置,其特征在于,还包括多个分割器,用于通过分割所述一组多输入比较器输出信号形成一组输出比特。 15. The apparatus according to claim 9, characterized in that, further comprising a plurality of divider for dividing by the set of multi-input comparator output signals form a set of output bits.
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