The content of the invention
In view of the foregoing, it is necessary to a kind of reduction is provided or arc discharge is reduced to power supply and the hurtful power supply switch controller of relay and method.
A kind of power supply switch controller, including:
One switching device, including first and second input, first and second switch element being connected corresponding with first and second input and an outfan, the outfan is to receive one first input voltage by first input end and first switch unit, or to receive one second input voltage by the second input and second switch unit, each switch element includes some relays;
One control device, including:
One detecting unit, is connected with first and second input, to receive the first or second input voltage, and to detect the zero-crossing signal of the first or second input voltage;
One processor, with detecting unit, first and second switch element is connected, to receive the first or second input voltage and the zero-crossing signal, and to detect the cycle of the described first or second input voltage, and judge whether first or second input voltage is abnormal, when processor detects the first input voltage exception from first input end, then according to the discharge time of the relay in the cycle and first switch unit of first input voltage calculating a delay time, and according to the zero-crossing signal of the delay time and the first input voltage for detecting judging opportunity that the relay for controlling first switch unit disconnects.
A kind of power supply switch controller, including:
One switching device, including first and second input, first and second switch element being connected corresponding with first and second input and an outfan, the outfan is to receive one first input voltage by first input end and first switch unit, or to receive one second input voltage by the second input and second switch unit, each switch element includes some relays;
One control device, including:
One detecting unit, is connected with first and second input, to receive the first or second input voltage, and to detect the crest signal of the first or second input voltage;
One processor, with detecting unit, first and second switch element is connected, to receive the first or second input voltage and the crest signal, and to detect the cycle of the described first or second input voltage, and judge whether first or second input voltage is abnormal, when processor detects the first input voltage exception from first input end, then according to the discharge time of the relay in the cycle and first switch unit of first input voltage calculating a delay time, and according to the crest signal of the delay time and the first input voltage for detecting judging opportunity that the relay for controlling first switch unit disconnects, after first switch unit disconnects, the relay conducting of the second switch unit that processor control is connected with the second input, so that the second input provides the second input voltage to outfan.
A kind of power supply switch controlling method, the method step include as follows:
The first or second input voltage exported by the first or second input is received by a voltage sensing unit;
The zero-crossing or crest signal of first or second input voltage are detected by a signal sensing unit;
The first or second input voltage that processor is provided by voltage sensing unit is detecting the cycle of the input voltage, and judge whether the described first or second input voltage is abnormal, if, first input voltage is abnormal, then the discharge time of the relay that processor is connected according to the cycle of the input voltage for being detected and with first input end to be calculating a delay time, and opens the opportunity of the relay of first switch unit judging end according to the zero-crossing or crest of the delay time and the input voltage of the first input end for detecting.
Compared to prior art, power supply switch controller of the present invention and method, can make processor that cycle of the input voltage of the first or second input and whether abnormal is detected by detecting unit, if the input voltage that the input for detecting work at present is provided is abnormal, a delay time is calculated according to the cycle of the input voltage for detecting and the discharge time of relay, and the delay time calculated by the zero-crossing signal of the input voltage for detecting or crest signal lag come judge export be connected with the input of work at present relay disconnection opportunity.It is thus possible to when greatly reducing or reducing relay disconnection, arc discharge causes damage to power supply and relay.
Description of the drawings
Fig. 1 is the schematic diagram that power supply switch controller of the present invention is connected with the first power supply, second source and an electronic equipment.
Fig. 2 is the block diagram of first preferred embodiment of power supply switch controller of the present invention.
Fig. 3 is the structural representation of first preferred embodiment of power supply switch controller of the present invention.
Fig. 4 is the zero-crossing signal according to input voltage of first preferred embodiment of power supply switch controller of the present invention judging the first waveform schematic diagram of delay time.
Fig. 5 is the zero-crossing signal according to input voltage of first preferred embodiment of power supply switch controller of the present invention judging the second waveform diagram of delay time.
Fig. 6 is the zero-crossing signal according to input voltage of first preferred embodiment of power supply switch controller of the present invention judging the 3rd waveform diagram of delay time.
Fig. 7 is the schematic diagram of second preferred embodiment of power supply switch controller of the present invention.
Fig. 8 is the crest signal according to input voltage of second preferred embodiment of power supply switch controller of the present invention judging the first waveform schematic diagram of delay time.
Fig. 9 is the crest signal according to input voltage of second good embodiment of power supply switch controller of the present invention judging the second waveform diagram of delay time.
Figure 10 is the crest signal according to input voltage of second good embodiment of power supply switch controller of the present invention judging the 3rd waveform diagram of delay time.
Figure 11 is the flow chart of power supply switch controlling method of the present invention.
Main element symbol description
Power supply switch controller 100
First power supply 300
Second source 400
Electronic equipment 200
Switching device 10
Control device 20
First input end 11
Second input 12
First switch unit 13
Second switch unit 14
Outfan 15
Detecting unit 23
Processor 25
Voltage sensing unit 230
Zero-crossing signal sensing unit 231
First voltage sensor 2301
Secondary signal detector 2302
First zero-crossing signal sensor 2310
Second zero-crossing signal sensor 2311
Primary peak signal sensing device 2330
Secondary peak signal sensing device 2331
Relay R1-R8
Thyristor S1-S4
Control chip 250
Relay driver 251
Thyristor driver 252
Following specific embodiment will further illustrate the present invention with reference to above-mentioned accompanying drawing.
Specific embodiment
With reference to shown in Fig. 1, power supply switch controller 100 is connected with one first power supply 300, a second source 400 and an electronic equipment 200, for switching between the first power supply 300 and second source 400 so that the voltage of the voltage or second source of the first power supply is supplied to electronic equipment 200, to maintain the normal power supply of electronic equipment 200.
Fig. 2 is referred to, is the schematic diagram of the first preferred embodiment of the invention.In the present embodiment, described power supply switch controller 100 includes a switching device 10 and a control device 20, and the switching device 10 is automatic change-over (Automatic
Transfer Switch, referred to as:ATS), the switching device 10 includes a first input end 11, one second input 12, a first switch unit 13, a second switch unit 14 and an outfan 15, the first input end 11 and the second input 12 are connected with the first power supply 300 and second source 400 respectively, the outfan 13 is to the first input voltage by first input end 11 and the reception output of the first power supply 300 of first switch unit 13, or receives the second input voltage of the output of second source 400 to pass through the second input 12 and second switch unit 14.The control device 20 includes a detecting unit 23 and a processor 25,The detecting unit 23 includes a voltage sensing unit 230 and a zero-crossing signal sensing unit 231,The voltage sensing unit 230 includes a first voltage sensor 2301 and a second voltage sensor 2302,The zero-crossing signal sensing unit 231 includes one first zero-crossing signal sensor 2310 and one second zero-crossing signal sensor 2311,The first voltage sensor 2301 and the first zero-crossing signal sensor 2310 are connected with the first input end 11 and processor 25,The second voltage sensor 2302 and the second zero-crossing signal sensor 2311 are connected with the second input 12 and processor 25,Processor 25 is also connected with the first switch unit 13 and second switch unit 14.
As shown in figure 3, for the structural representation of the first preferred embodiment of the invention.The first input end 11 and the second input 12 are all connected with civil power.The first switch unit 13 includes four relay R1-R4 and two thyristors S1 and S2, and the second switch unit 14 includes four relay R5-R8 and four thyristors S3 and S4.The relay R1 and relay R2 are serially connected between the live wire L1 and outfan 15 of the first input end 11, and the relay R3 and relay R4 is serially connected between the zero line N1 and outfan 15 of the first input end 11.Each thyristor is composed in parallel by two single thyristors.Node between the first end of the thyristor S1 and relay R1 and R2 is connected, and second end of the thyristor S1 is connected with outfan 15.Node between the first end of the thyristor S2 and relay R3 and R4 is connected, and second end of the thyristor S2 is connected with outfan 15.The relay R5 and relay R6 are serially connected between the live wire L2 and outfan 15 of second input 12, and the relay R7 and relay R8 is serially connected between the zero line N2 and outfan 15 of second input 12.Node between the first end of the thyristor S3 and relay R5 and R6 is connected, and second end of the thyristor S3 is connected with outfan 15.Node between the first end of the thyristor S4 and relay R7 and R8 is connected, and second end of the thyristor S4 is connected with outfan 15.
The processor 25 includes control chip 250, a relay driver 251 and a thyristor driver 252, the relay R1-R8 is connected to the processor 25 by relay driver 251, and the control end of the thyristor S1-S4 is connected to the processor 25 by thyristor driver 252.The relay driver 251 and thyristor driver 252 play regulating relay R1-R8 and thyristor S1-S4 is connected into the voltage of control chip 250 by civil power, to reach the effect of voltage matches.
In the present embodiment, thyristor S1 and S2 can play the signal transmission time for accelerating first input end to outfan, thyristor S3 and S4 can play the signal transmission time for accelerating the second input to outfan, each thyristor advantageously reduces the pressure drop of corresponding relay connected in parallel, then beneficial to further reducing arc discharge.
During work, the voltage being currently received when outfan 15 is from the first input end 11 and the first power supply 300, the first input voltage that the detecting of first voltage sensor 2301 first input end 11 is received, and the voltage for receiving is supplied to into processor 25, the first zero-crossing signal sensor 2310 detects the zero-crossing signal of the first input voltage, and the zero-crossing signal for detecting is supplied to the processor 25.The processor 25 detects the cycle T of the first input voltage by first voltage sensor 2301, and judge whether first input voltage is abnormal, if current first input voltage is abnormal, discharge time T of the processor 25 according to the relay of the cycle T and first switch unit 13 of the first input voltageReleaseTo calculate a delay time TDelay, and according to delay time TDelayAnd the zero-crossing signal of the first input voltage for detecting is judging to export the opportunity for disconnecting four relay R1-R4 signals, to avoid stronger arc discharge, arc discharge is reduced to relay and the adverse effect of power supply.In the present embodiment, the power-on time T of relayReleaseIt is relay coil from starting to obtain the release time that the control signal of power-off is fully disconnected to relay contacts point.
With reference to Fig. 4 to Fig. 6, when to be the first input voltage be sine wave, processor 25 detects the zero-crossing signal of the first input voltage with the first zero-crossing signal sensor 2310(ZCD)Three kinds of state waveforms on the basis of, determine send disconnection four relays(Represented with Delay in Fig. 4 to Fig. 6)The opportunity of signal, wherein, TDelayMeet following relational expression:
T/4-TRelease <TDelay< T/2-TRelease ;Or 3T/4-TRelease <TDelay< T-TRelease
。
I.e. processor 25 is detecting the zero-crossing signal of the first input voltage(ZCD)And Jing delay time TDelayAfterwards, output disconnects four relay R1-R4 signals immediately.After four relay R1-R4 being connected with first input end 11 are disconnected, processor 25 controls the relay R5-R8 closures being connected with the second input 12, so that the voltage of second source 400 is exported to outfan 15 by the second input 12 by relay R5-R8.In the present embodiment, the zero-crossing signal of the input voltage for input voltage sine wave when transverse axis is close to signal.
As shown in Figure 7, for the schematic diagram of the second preferred embodiment of the invention, from unlike the first preferred embodiment, the detecting unit 23 includes voltage sensing unit 230 and a crest signal sensing unit 233, shown crest signal sensing unit 233 includes primary peak signal sensing device 2330 and a secondary peak signal sensing device 2331, the primary peak signal sensing device 2330 and a secondary peak signal sensing device 2331 respectively with receive the first input voltage and the second input voltage, and detect the crest signal of the first input voltage and the second input voltage, and the crest signal for detecting is supplied to into processor 25.
Second preferred embodiment is similar with the operation principle of the first preferred embodiment, the voltage being currently received when outfan 15 is from the first input end 11 and the first power supply 300, the first input voltage that the detecting of first voltage sensor 2301 first input end 11 is received, and the voltage for receiving is supplied to into processor 25, the primary peak signal sensing device 2330 detects the crest signal of the first input voltage, and the crest signal for detecting is supplied to the processor 25.The processor 25 detects the cycle T of the first input voltage by first voltage sensor 2301, and judge whether first input voltage is abnormal, if current first input voltage is abnormal, discharge time T of the processor 25 according to the relay of the cycle T and first switch unit 13 of the first input voltageReleaseTo calculate a delay time TDelay, and according to delay time TDelayAnd the crest signal of the first input voltage for detecting judge export disconnect four relay R1-R4 signals opportunity.
With reference to Fig. 8 to Figure 10, when to be the first input voltage be sine wave, processor 25 detects the crest signal of the first input voltage with primary peak signal sensing device 2310(PKD)Three kinds of state waveforms on the basis of, calculate send disconnection four relays(Represented with Delay in Fig. 4 to Fig. 6)The opportunity of signal, wherein, TDelayMeet following relational expression:
0<TDelay< T/4-TRelease Or T/2-TRelease <TDelay< 3T/4-TRelease
。
I.e. processor 25 is detecting the crest signal of the first input voltage(PKD)And Jing delay time TDelayAfterwards, output disconnects four relay R1-R4 signals immediately.After four relay R1-R4 being connected with first input end 11 are disconnected, processor 25 controls the relay R5-R8 closures being connected with the second input 12, so that the voltage of second source 400 is exported to outfan 15 by the second input 12 by relay R5-R8.In the present embodiment, the crest signal of the input voltage for input voltage sine wave in crest signal.
With reference to shown in Figure 11, it is the flow chart of power supply automatic switching method preferred embodiment of the present invention.In the present embodiment, the method can be by being applied to power supply switch controller as above, and the step includes as follows:
Step S801, receives the first input voltage exported by first input end by voltage sensing unit 230.
Step S802, detects the zero-crossing or crest signal of first input voltage by signal sensing unit 231/233.
Step S803, the first input voltage that 25 receiving voltage sensing unit of processor 230 is provided, and detect the cycle T of first input voltage.
Step S804, processor 25 judge whether first input voltage is abnormal, if there is exception, carries out step S805, return to step S801 if it there is no exception.
Step S805, the discharge time T of the relay R1-R4 that processor is connected according to the cycle T of the first input voltage for being detected and with first input endReleaseTo calculate a delay time tDelay。
Step S806, processor is according to delay time tDelayAnd the zero-crossing signal or crest signal of the input voltage of the first input end for detecting judge export disconnect first switch unit relay signal opportunity.
Step S807, after the relay of first switch unit disconnects, processor 25 controls the relay R5-R8 conductings of the second switch unit being connected with the second input 12, so that the second input 12 provides the voltage of second source 400 to outfan 15.
When second source 400 is supplied to outfan 15 by second switch unit 14 by the second input 12, and when second voltage sensor 2302 and the work of the second zero-crossing signal sensor 2311, first power supply 300 is supplied to outfan 15 by first switch unit 13 with first input end 11 by its principle, and the principle of first voltage sensor 2301 and the work of the first zero-crossing signal sensor 2310 is identical, will not be described here.
To sum up, the processor 25 of the present invention passes through the zero-crossing or crest signal for detecting input voltage, and the delay time calculated by the zero-crossing signal of input voltage or crest signal lag to judge to export the opportunity that the relay being connected with the input of work at present is disconnected.It is thus possible to when greatly reducing or reducing relay disconnection, arc discharge causes damage to power supply and relay.
Above example is only to illustrate technical scheme and unrestricted, although being described in detail to the present invention with reference to above preferred embodiment, it will be understood by those within the art that, technical scheme can be modified or equivalent should not all depart from the spirit and scope of technical solution of the present invention.