CN106547232B - A kind of hard switching circuit - Google Patents

A kind of hard switching circuit Download PDF

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Publication number
CN106547232B
CN106547232B CN201510607462.4A CN201510607462A CN106547232B CN 106547232 B CN106547232 B CN 106547232B CN 201510607462 A CN201510607462 A CN 201510607462A CN 106547232 B CN106547232 B CN 106547232B
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China
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triode
connect
pin
capacitor
resistance
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CN201510607462.4A
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Chinese (zh)
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CN106547232A (en
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傅强
李云
但汉波
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万众科技有限公司
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    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00Programme-control systems
    • G05B19/02Programme-control systems electric
    • G05B19/04Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors

Abstract

The embodiment of the invention discloses a kind of hard switching circuits, solving present products most on the market is all that come the on-off mode of control switch machine, there is no fully powered-off for system after shut down by Sofe Switch, only part of functions is powered off, CUP will also keep minimum working condition, to which shutdown truly be not achieved, also power consumption more cannot thoroughly be reduced, Sofe Switch has to write startup and shutdown code simultaneously, caused by design become increasingly complex, the higher technical problem of use cost.

Description

A kind of hard switching circuit

Technical field

The present invention relates to electronic circuit technology field more particularly to a kind of hard switching circuits.

Background technique

Existing long press-type switch majority is controlled with software, and booting, shut down main operational principle are as follows: opens Machine: it presses power button → power-on instruction and is sent to power supply IC module → power supply IC control foot and obtain signal and transmit starting-up signal To CPU → CPU bring into operation CPU after boot program → boot program normal operation issue power-on instruction signal to power supply IC block → Each road operating voltage opening of output → mobile phone is completed boot action by power supply IC.Shutdown: it presses closing key → shutdown command and send It obtains off signal to power supply IC module → power supply IC control foot and signal is passed to CPU → CPU to bring into operation journey of shutting down It is to power supply IC block → power supply IC that each road work of output is electric to issue shutdown command signal by CPU after sequence → shutdown programm normal operation Pressure closing → mobile phone terminates shutdown movement.

Most products are all by Sofe Switch come control switch machine on the market now, and this on-off mode is after shut down System only powers off part of functions there is no fully powered-off, and CPU will also keep minimum working condition, thus Shutdown truly is not achieved, also more cannot thoroughly reduce power consumption, at the same Sofe Switch have to write booting and Shut down code, becomes increasingly complex so as to cause design, the higher technical problem of use cost.

Summary of the invention

The embodiment of the invention provides a kind of hard switching circuit, solves present products most on the market and all pass through Sofe Switch carrys out the on-off mode of control switch machine, and system only breaks part of functions there is no fully powered-off after shut down Electricity, CPU will also keep minimum working condition, so that shutdown truly is not achieved, it also cannot be more thorough Reduce power consumption, while Sofe Switch has to write startup and shutdown code, caused by design become increasingly complex, use cost Higher technical problem.

A kind of hard switching circuit provided in an embodiment of the present invention, comprising:

CPU, key switch SW1, triode Q3;

The emitter of the triode Q3 is connect with the ON/OFF pin of the CPU;

The base stage of the triode Q3 is connect with one end of the key switch SW1, and is connected with the collector of triode Q4 It connects;

The emitter of the triode Q4 is connect with the other end of the key switch SW1;

The base stage of the triode Q4 is connect with the PWR_CTL pin of the CPU;

The PWR_CTL pin of the CPU is connect with the enabled foot EN of voltage stabilizing chip U1.

Optionally, the hard switching circuit further includes the first RC charge-discharge circuit.

Optionally, first RC charge-discharge circuit is made of the resistance R7 and capacitor C4 being connected in series.

Optionally, the intermediate point of the resistance R7 and the capacitor C4 are connect with the collector of triode Q6, the centre Point is also connect with one end of diode D4;

The base stage of the triode Q6 is connected with one end of resistance R6, the other end of the resistance R6 and the triode Q4 Base stage connection.

Optionally, one end of the emitter of the triode Q6 is connected to the key switch SW1 and the triode Q4 Collector between, the capacitor C4 and the disconnected of the resistance R7 terminate at the key switch SW1 and the triode Between the collector of Q4;

The emitter of triode Q5 is also connected between the key switch SW1 and the collector of the triode Q4.

Optionally, the base stage of the triode Q5 is connect with the other end of the diode D4;

The collector of the triode Q5 is connect with one end of resistance R3.

Optionally, the other end of the resistance R3 is connect with the grid of PMOS tube Q1, the source electrode and electricity of the PMOS pipe Q1 Pond feeder ear VBAT connection, the drain electrode of the PMOS tube Q1 are connect with one end of rectifier D2, the other end of the rectifier D2 For being connect with VBUS pin.

Optionally, the hard switching circuit further includes the 2nd RC charge-discharge circuit being made of resistance R8 and capacitor C3;

The capacitor C3 is connect with the front of motor of the resistance R8 with the grid of PMOS tube Q2, the drain electrode of the PMOS tube It is connect with the PWR_CTL pin of the CPU, the source electrode of the PMOS tube is connect with one end of diode D3, the diode D3 The other end for being connect with VBUS pin;

The resistance R8 is connect with the front of motor of the capacitor C3 with the other end of the diode D3.

Optionally, the resistance R8 and the capacitor C3 intermediate point are connected with one end of diode D5;

The other end of the diode D5 is connect with the base stage of triode Q7, the collector and the electricity of the triode Q7 Resistance R8 is connect with the front of motor of the capacitor C3, and the emitter of the triode Q7 is with the capacitor C3's and resistance R8 Front of motor connection.

Optionally, the VIN pin of the voltage stabilizing chip U1 is connected by the VBUS pin of diode D1 and MICROUSB;

The GND pin of the voltage stabilizing chip U1 and the GND pin of MICROUSB connect;

One end of capacitor C2, the capacitor are connected between the VIN pin of the voltage stabilizing chip U1 and the diode D1 It is connected between the GND pin of the GND pin and the MICROUSB of the other end of C2 and the voltage stabilizing chip U1;

The GND pin of the MICROUSB is connected with one end of capacitor C1, the other end of the capacitor C1 and the pressure stabilizing The VOUT pin of chip U1 connects, the VOUT pin of the other end of the capacitor C1 and the voltage stabilizing chip U1 with power supply VCC Connection.

As can be seen from the above technical solutions, the embodiment of the present invention has the advantage that

A kind of hard switching circuit provided in the present embodiment, comprising: CPU, key switch SW1, triode Q3;Three pole The emitter of pipe Q3 is connect with the ON/OFF pin of the CPU;The one of the base stage of the triode Q3 and the key switch SW1 End connection, and connect with the collector of triode Q4;The other end of the emitter of the triode Q4 and the key switch SW1 Connection;The base stage of the triode Q4 is connect with the PWR_CTL pin of the CPU;The PWR_CTL pin of the CPU and pressure stabilizing The enabled foot EN connection of chip U1.In the present embodiment, whether the ON/OFF pin by detecting CPU is set low to shut down Operation, normal operating conditions ON/OFF pin export high level, and SW1 is not closed before being shut down, PNP triode Q3 Base stage have voltage, Q3 is in off state, and the ON/OFF functional pin of CPU is constantly in output high level state, works as key SW1 is pressed, and the base stage of Q3 is connected to ground, and Q3 conducting, ON/OFF is pulled low, and CPU is detecting ON/OFF within the T3 time After low level, CPU issues shutdown command to PWR_CTL, gives mono- low level of PWR_CTL, the enabled foot EN of U1 is set to Low, so U1 can not work normally, rear portion down circuitry, shutdown is completed, and solving present products most on the market is all By Sofe Switch come the on-off mode of control switch machine after shut down system there is no fully powered-off, only by part of functions into Row power-off, CPU will also keep minimum working condition, so that shutdown truly is not achieved, it also cannot be more thorough The reduction power consumption at bottom, while Sofe Switch has to write startup and shutdown code, caused by design become increasingly complex, use The higher technical problem of cost.

Detailed description of the invention

In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this Some embodiments of invention without any creative labor, may be used also for those of ordinary skill in the art To obtain other attached drawings according to these attached drawings.

Fig. 1 is a kind of circuit diagram of the hard switching circuit provided in the present embodiment.

Specific embodiment

The embodiment of the invention provides a kind of hard switching circuit, solves present products most on the market and all pass through Sofe Switch carrys out the on-off mode of control switch machine, and system only breaks part of functions there is no fully powered-off after shut down Electricity, CPU will also keep minimum working condition, so that shutdown truly is not achieved, it also cannot be more thorough Reduce power consumption, while Sofe Switch has to write startup and shutdown code, caused by design become increasingly complex, use cost Higher technical problem.

In order to make the invention's purpose, features and advantages of the invention more obvious and easy to understand, below in conjunction with the present invention Attached drawing in embodiment, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that disclosed below Embodiment be only a part of the embodiment of the present invention, and not all embodiment.Based on the embodiments of the present invention, this field Those of ordinary skill's all other embodiment obtained without making creative work, belongs to protection of the present invention Range.

Referring to Fig. 1, a kind of one embodiment of the hard switching circuit provided in the present embodiment includes:

CPU, key switch SW1, triode Q3;

The emitter of the triode Q3 is connect with the ON/OFF pin of the CPU;

The base stage of the triode Q3 is connect with one end of the key switch SW1, and is connected with the collector of triode Q4 It connects;

The emitter of the triode Q4 is connect with the other end of the key switch SW1;

The base stage of the triode Q4 is connect with the PWR_CTL pin of the CPU;

The PWR_CTL pin of the CPU is connect with the enabled foot EN of voltage stabilizing chip U1.

Optionally, the hard switching circuit further includes the first RC charge-discharge circuit.

Optionally, first RC charge-discharge circuit is made of the resistance R7 and capacitor C4 being connected in series.

Optionally, the intermediate point of the resistance R7 and the capacitor C4 are connect with the collector of triode Q6, the centre Point is also connect with one end of diode D4;

The base stage of the triode Q6 is connected with one end of resistance R6, the other end of the resistance R6 and the triode Q4 Base stage connection.

Optionally, one end of the emitter of the triode Q6 is connected to the key switch SW1 and the triode Q4 Collector between, the capacitor C4 and the disconnected of the resistance R7 terminate at the key switch SW1 and the triode Between the collector of Q4;

The emitter of triode Q5 is also connected between the key switch SW1 and the collector of the triode Q4.

Optionally, the base stage of the triode Q5 is connect with the other end of the diode D4;

The collector of the triode Q5 connect with one end of resistance R3,

Optionally, the other end of the resistance R3 is connect with the grid of PMOS tube Q1, the source electrode and electricity of the PMOS pipe Q1 Pond feeder ear VBAT connection, the drain electrode of the PMOS tube Q1 are connect with one end of rectifier D2, the other end of the rectifier D2 For being connect with VBUS pin.

Optionally, the hard switching circuit further includes the 2nd RC charge-discharge circuit being made of resistance R8 and capacitor C3;

The capacitor C3 is connect with the front of motor of the resistance R8 with the grid of PMOS tube Q2, the drain electrode of the PMOS tube It is connect with the PWR_CTL pin of the CPU, the source electrode of the PMOS tube is connect with one end of diode D3, the diode D3 The other end for being connect with VBUS pin;

The resistance R8 is connect with the front of motor of the capacitor C3 with the other end of the diode D3.

Optionally, the resistance R8 and the capacitor C3 intermediate point are connected with one end of diode D5;

The other end of the diode D5 is connect with the base stage of triode Q7, the collector and the electricity of the triode Q7 Resistance R8 is connect with the front of motor of the capacitor C3, and the emitter of the triode Q7 is with the capacitor C3's and resistance R8 Front of motor connection.

Optionally, the VIN pin of the voltage stabilizing chip U1 is connected by the VBUS pin of diode D1 and MICROUSB;

The GND pin of the voltage stabilizing chip U1 and the GND pin of MICROUSB connect;

One end of capacitor C2, the capacitor are connected between the VIN pin of the voltage stabilizing chip U1 and the diode D1 It is connected between the GND pin of the GND pin and the MICROUSB of the other end of C2 and the voltage stabilizing chip U1;

The GND pin of the MICROUSB is connected with one end of capacitor C1, the other end of the capacitor C1 and the pressure stabilizing The VOUT pin of chip U1 connects, the VOUT pin of the other end of the capacitor C1 and the voltage stabilizing chip U1 with power supply VCC Connection.

In order to make it easy to understand, the switching on and shutting down process to embodiment shown in FIG. 1 is described in detail below.

Application examples one:

Start process when being powered by battery: when being battery powered, since SW1 is not pressed at this time, NPN triode There is voltage in the base stage of Q6, so as to cause triode Q6 conducting, the RC charge-discharge circuit of R7 and C4 composition can not charge, Voltage is suppressed in 0V always, makes NPN triode Q5 base stage no-voltage, and the pole G of PMOS tube Q1 is in high level always, and Q1 can not Conducting, so that the rear portion Q1 VBUS be made not have voltage, U1LDO chip can not output voltage to system power supply;After pressing SW1, Since the base voltage of Q6 becomes 0V, Q6 can not be connected, and the RC charge-discharge circuit of R7 and C4 composition starts to work normally, as R7 and When the voltage of C4 intermediate point reaches 1.4V by the charged voltage of T1 times, SW1 is disconnected, the base voltage of Q5 reaches 0.7V, Q5 are switched on, and the voltage at the both ends R3 is made to become 0V, and the pole G of PMOS tube Q1 becomes low level, Q1 conducting, the normal band of VBUS Electricity, in VBUS there are no when normal voltage, the charge-discharge circuit of R8 and C3 composition does not carry out charging work, voltage 0V, NPN Triode Q7 is not connected, and the pole the G no-voltage of PMOS tube Q2, Q2 is on state, and after VBUS has voltage, what R8 and C3 was formed fills Discharge circuit charges, and being charged to this period that 1.4V can allow NPN triode Q7 to be connected in voltage, Q2 is normally to lead in T2 Leading to state, there is voltage on PWR_CTL, the EN of U1 enables foot and is in high level, and so far the EN foot of U1 and Vin foot have voltage, U1 is worked normally, thus make below whole system start to work normally, after system worked well, allow system within the T2 time CPU gives PWR_CTL (i.e. EN foot) a lasting high level, maintains the conducting of NPN triode Q4, and R3 both end voltage is 0V, Q1 On state cell voltage VBAT i.e. sustainable supply can be constantly in VBUS, under entire boot-strap circuit works normally always It goes.After the T2 time, Q7 conducting, Q2 cut-off, the high level of PWR_CTL is provided by CPU at this time.

The time of T1 and T2 above-mentioned calculate as follows:

The calculation formula of T1, T2 charge and discharge time: T1 is the time of long-pressing booting, T1=-R7*C4*ln [(E-V)/E];

The unit of R7 is ohm, and the unit of C4 is F;Voltage (i.e. VBAT) of the E between series resistance and capacitor, V are electricity Voltage (i.e. 1.4V) to be achieved between appearance.Ln is natural logrithm.

According to formula: T1=-100*1000*47/1000000*ln [(5-1.4)/5]=- 4.7*ln0.72 ≈ 1.54s;

T2 is CPU response time, T2=-R8*C3*ln [(E-V)/E];

The unit of R8 is ohm, and the unit of C3 is F;E between series resistance and capacitor voltage (i.e. VBAT-VD2, Middle VD2 is the pressure drop 0.3V of D2 zener diode), V voltage (i.e. 1.4V) to be achieved between capacitor.Ln is natural logrithm.

T2=-50*1000*22/1000000*ln [(4.7-1.4)/4.7]=- 1.1*ln0.72 ≈ 0.4s.

Application examples two:

Start process when being powered by USB: after access USB, VCC5V has voltage, and VBUS has voltage, the power supply of U1LDO Input pin VIN has voltage, at this point, since the R8 and C3 RC charge-discharge circuit formed is carrying out filling for 0~1.4V voltage range Electricity, so NPN triode Q7 is not turned on, the pole G of Q2 is in low level, Q2 can normally, have electricity on PWR_CTL pin It presses, also has normal high level on the enabled foot EN of U1, so U1 is worked normally, the rear portion U1 circuit can be worked normally, meanwhile, After RC circuit voltage is filled to 1.4V, Q7 conducting, Q2 cut-off, PWR_CTL level is lower, so CPU is necessary after working normally It is filled in 1.4V T2 this period in the RC circuit voltage of R8 and C3 composition and gives mono- high level of PWR_CTL, to maintain electricity Road continues working.

Application examples three:

Shutdown process: entire shutdown process is controlled by CPU, the ON/OFF pin by detecting CPU whether set low come into Row power-off operation, normal operating conditions ON/OFF pin export high level, and SW1 is not closed before being shut down, PNP tri- The base stage of pole pipe Q3 has voltage, and Q3 is in off state, and the ON/OFF functional pin of CPU is constantly in output high level state, When key SW1 is pressed, the base stage of Q3 is connected to ground, and Q3 conducting, ON/OFF is pulled low, and CPU is detecting ON/OFF in T3 In time all in low level after, CPU issues shutdown command to PWR_CTL, gives mono- low level of PWR_CTL, the enabled foot of U1 EN is set low, so U1 can not work normally, rear portion down circuitry, shutdown is completed.

A kind of hard switching circuit provided in the present embodiment, comprising: CPU, key switch SW1, triode Q3;Three pole The emitter of pipe Q3 is connect with the ON/OFF pin of the CPU;The one of the base stage of the triode Q3 and the key switch SW1 End connection, and connect with the collector of triode Q4;The other end of the emitter of the triode Q4 and the key switch SW1 Connection;The base stage of the triode Q4 is connect with the PWR_CTL pin of the CPU;The PWR_CTL pin of the CPU and pressure stabilizing The enabled foot EN connection of chip U1.In the present embodiment, whether the ON/OFF pin by detecting CPU is set low to shut down Operation, normal operating conditions ON/OFF pin export high level, and SW1 is not closed before being shut down, PNP triode Q3 Base stage have voltage, Q3 is in off state, and the ON/OFF functional pin of CPU is constantly in output high level state, works as key SW1 is pressed, and the base stage of Q3 is connected to ground, and Q3 conducting, ON/OFF is pulled low, and CPU is detecting ON/OFF within the T3 time After low level, CPU issues shutdown command to PWR_CTL, gives mono- low level of PWR_CTL, the enabled foot EN of U1 is set to Low, so U1 can not work normally, rear portion down circuitry, shutdown is completed, and solving present products most on the market is all By Sofe Switch come the on-off mode of control switch machine after shut down system there is no fully powered-off, only by part of functions into Row power-off, CPU will also keep minimum working condition, so that shutdown truly is not achieved, it also cannot be more thorough The reduction power consumption at bottom, while Sofe Switch has to write startup and shutdown code, caused by design become increasingly complex, use The higher technical problem of cost, and by Sofe Switch cannot fully powered-off mode be changed to can be fully powered-off, reduce power consumption, it is complete Electric current is less than 10uA under complete closedown state.

It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description, The specific work process of device and unit, can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.

In several embodiments provided herein, it should be understood that disclosed system, device and method can be with It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit It divides, only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple units or components It can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, it is shown or The mutual coupling, direct-coupling or communication connection discussed can be through some interfaces, the indirect coupling of device or unit It closes or communicates to connect, can be electrical property, mechanical or other forms.

The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme 's.

It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit It is that each unit physically exists alone, can also be integrated in one unit with two or more units.Above-mentioned integrated list Member both can take the form of hardware realization, can also realize in the form of software functional units.

If the integrated unit is realized in the form of SFU software functional unit and sells or use as independent product When, it can store in a computer readable storage medium.Based on this understanding, technical solution of the present invention is substantially The all or part of the part that contributes to existing technology or the technical solution can be in the form of software products in other words It embodies, which is stored in a storage medium, including some instructions are used so that a computer Equipment (can be personal computer, server or the network equipment etc.) executes the complete of each embodiment the method for the present invention Portion or part steps.And storage medium above-mentioned includes: USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic or disk etc. are various can store journey The medium of sequence code.

The above, the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations;Although referring to before Stating embodiment, invention is explained in detail, those skilled in the art should understand that: it still can be to preceding Technical solution documented by each embodiment is stated to modify or equivalent replacement of some of the technical features;And these It modifies or replaces, the spirit and scope for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution.

Claims (10)

1. a kind of hard switching circuit characterized by comprising
CPU, key switch SW1, triode Q3;
The emitter of the triode Q3 is connect with the ON/OFF pin of the CPU;
The base stage of the triode Q3 is connect with one end of the key switch SW1, and is connect with the collector of triode Q4;
The emitter of the triode Q4 is connect with the other end of the key switch SW1;
The base stage of the triode Q4 is connect with the PWR_CTL pin of the CPU;
The PWR_CTL pin of the CPU is connect with the enabled foot EN of voltage stabilizing chip U1;
After detecting that the ON/OFF pin is in low level within a preset time, the CPU sends a low level extremely The PWR_CTL pin of the CPU, so that the rear portion down circuitry of the voltage stabilizing chip U1.
2. hard switching circuit according to claim 1, which is characterized in that the hard switching circuit further includes the first RC charge and discharge Circuit.
3. hard switching circuit according to claim 2, which is characterized in that first RC charge-discharge circuit is by being connected in series Resistance R7 and capacitor C4 composition.
4. hard switching circuit according to claim 3, which is characterized in that the intermediate point of the resistance R7 and the capacitor C4 It is connect with the collector of triode Q6, the intermediate point is also connect with one end of diode D4;
The base stage of the triode Q6 is connected with one end of resistance R6, the base of the other end of the resistance R6 and the triode Q3 Pole connection.
5. hard switching circuit according to claim 4, which is characterized in that
One end of the emitter of the triode Q6 be connected to the key switch SW1 and the triode Q4 emitter it Between, the disconnected emitter for terminating at the key switch SW1 Yu the triode Q4 of the capacitor C4 and the resistance R7 Between;
The emitter of triode Q5 is also connected between the key switch SW1 and the emitter of the triode Q4.
6. hard switching circuit according to claim 5, which is characterized in that the base stage of the triode Q5 and the diode The other end of D4 connects;
The collector of the triode Q5 is connect with one end of resistance R3.
7. hard switching circuit according to claim 6, which is characterized in that the other end of the resistance R3 is with PMOS tube Q1's Grid connection, the source electrode of the PMOS tube Q1 are connect with battery feeder ear VBAT, the drain electrode of the PMOS tube Q1 and rectifier D2 One end connection, the other end of the rectifier D2 with the VBUS pin of the voltage stabilizing chip U1 for connecting.
8. hard switching circuit according to claim 7, which is characterized in that the hard switching circuit further includes, by resistance R8 With the second RC charge-discharge circuit of capacitor C3 composition;
The capacitor C3 is connect with the front of motor of the resistance R8 with the grid of PMOS tube Q2, the drain electrode of the PMOS tube and institute The PWR_CTL pin connection of CPU is stated, the source electrode of the PMOS tube is connect with one end of diode D3, and the diode D3's is another One end with the VBUS pin of the voltage stabilizing chip U1 for connecting;
The resistance R8 is connect with the front of motor of the capacitor C3 with the other end of the diode D3.
9. hard switching circuit according to claim 8, which is characterized in that the resistance R8 and the capacitor C3 intermediate point connect It is connected to one end of diode D5;
The other end of the diode D5 is connect with the base stage of triode Q7, the collector of the triode Q7 and the resistance R8 It is connect with the front of motor of the capacitor C3, the non-company of the emitter of the triode Q7 and the capacitor C3 and the resistance R8 Connect end connection.
10. hard switching circuit according to claim 9, which is characterized in that the VIN pin of the voltage stabilizing chip U1 passes through two The VUSB pin of pole pipe D1 and MICROUSB connect;
The GND pin of the voltage stabilizing chip U1 and the GND pin of MICROUSB connect;
One end of capacitor C2 is connected between the VIN pin of the voltage stabilizing chip U1 and the diode D1, the capacitor C2's It is connected between the GND pin of the GND pin and the MICROUSB of the other end and the voltage stabilizing chip U1;
The GND pin of the MICROUSB is connected with one end of capacitor C1, the other end of the capacitor C1 and the voltage stabilizing chip The VOUT pin of U1 connects, and the other end of the capacitor C1 is connect with power supply VCC with the VOUT pin of the voltage stabilizing chip U1.
CN201510607462.4A 2015-09-22 2015-09-22 A kind of hard switching circuit CN106547232B (en)

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