CN106449555A - Chip packaging process and chip packaging structure - Google Patents

Chip packaging process and chip packaging structure Download PDF

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Publication number
CN106449555A
CN106449555A CN201611129948.2A CN201611129948A CN106449555A CN 106449555 A CN106449555 A CN 106449555A CN 201611129948 A CN201611129948 A CN 201611129948A CN 106449555 A CN106449555 A CN 106449555A
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chip
substrate
protective layer
cavity
formed
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CN201611129948.2A
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Chinese (zh)
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林挺宇
陈�峰
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华进半导体封装先导技术研发中心有限公司
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Priority to CN201611129948.2A priority Critical patent/CN106449555A/en
Publication of CN106449555A publication Critical patent/CN106449555A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52Mounting semiconductor bodies in containers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device

Abstract

The invention provides a chip packaging process and a chip packaging structure, and relates to the field of chip packaging. The chip packaging process comprises providing a substrate, forming a cavity in the substrate, arranging at least one chip with a boss on the bottom face of the cavity, and enabling the upper surface of the substrate to be higher than the upper surface of an electrode of each chip, wherein the bosses are positioned on the electrodes of the chips; forming a protection layer in the cavity, and forming a plurality of guide lines, which are electrically connected with the upper surfaces of the bosses, on the protection layer and the substrate; forming an insulating layer on the guide lines and the protection layer, and forming at least one window in the insulating layer to arrange welding balls electrically connected with the guide lines. The chip packaging process and the chip packaging structure have the advantages that the chips are sealed through the cavity and the protection layer, thereby not being damaged easily; the guide lines and the bosses guide the electrodes of the chips to the welding balls, and accordingly, data transmission to the chips is achieved through the welding balls.

Description

一种芯片的封装工艺和封装结构 A chip package structure of the packaging process and

技术领域 FIELD

[0001] 本发明实施例涉及芯片封装领域,尤其涉及一种芯片的封装工艺和封装结构。 FIELD The embodiment relates to a chip package [0001] The present invention particularly relates to a package structure and a packaging process of the chip.

背景技术 Background technique

[0002]芯片封装就是把生产出来的集成电路裸片放在一块起到承载作用的基板上,把电极引出来,然后固定包装成为一个整体。 [0002] The chip package is produced by an integrated circuit die on the substrate plays the role of carrier, the electrode lead out, and then packaged as a whole is fixed. 在芯片的封装过程中,一般是将裸片放置在封装基板上并对准放置位点,使得焊球对准基板上的预焊料。 Chip during packaging, the die is typically placed on the package substrate and aligned to the placement site, such that the pre-solder balls are aligned on the substrate. 基板通常由有机材料或层压材料组成,后续再利用加热回焊,形成芯片与封装基板之间的电连接。 Substrate is typically an organic material or a laminate material, then the subsequent reflowed by heating, an electrical connection between the chip and the package substrate. 芯片封装是半导体行业极其重要的一个组成部分,现有的封装结构不能对芯片进行针对性和有效地保护。 The chip package is a very important part of the semiconductor industry, the conventional chip package structure can not be targeted and effective protection.

发明内容 SUMMARY

[0003] 本发明提供一种芯片的封装工艺和封装结构,以实现对芯片进行更完善的保护。 [0003] The present invention provides a package structure and a packaging process of the chip, the chip in order to achieve better protection.

[0004] 第一方面,本发明实施例提供了一种芯片的封装工艺,包括: [0004] In a first aspect, the present invention provides a process for packaging chip, comprising:

[0005] 提供衬底; [0005] providing a substrate;

[0006] 在所述衬底中形成腔体,将至少一个设置有凸台的芯片设置在所述腔体的底面,并使所述衬底的上表面高于所述芯片的电极上表面,其中所述凸台位于所述芯片的电极上; [0006] a cavity formed in the substrate, at least a bottom surface of the chip is provided with a boss provided in said cavity, and an upper surface of the substrate is higher than the upper electrode of the chip surface, wherein said boss is located on the electrode of the chip;

[0007] 在所述腔体中形成保护层,并在所述保护层和所述衬底上形成与各所述凸台上表面电连接的多条导线; [0007] forming a protective layer in the cavity, and the protective layer formed on the substrate and a plurality of wires electrically connected to the stage with the surface of each salient;

[0008] 在所述多条导线和所述保护层上形成绝缘层,并在所述绝缘层上形成至少一个窗口,以设置与各所述导线电连接的焊球。 [0008] The insulating layer is formed on the plurality of wires and the protective layer, and at least one window is formed on the insulating layer, is provided with a solder ball to each of the conductors electrically connected.

[0009]可选的,在上述封装工艺中,所述在所述腔体中形成保护层包括: [0009] Optionally, in the packaging process, the protective layer is formed in the cavity comprising:

[0010] 在所述腔体中形成保护层; [0010] forming a protective layer in the cavity;

[0011] 处理所述保护层和各所述凸台以露出各所述凸台的上表面,且使各所述凸台的上表面、所述保护层的上表面与所述衬底的上表面平齐。 [0011] The process and the protective layer to expose each of said bosses each of said upper surface of the boss and said upper surface of each boss on the upper surface of the protective layer and the substrate, flush with the surface.

[0012] 可选的,在上述封装工艺中,所述在所述保护层和所述衬底上形成与各所述凸台上表面电连接的多条导线包括: [0012] Optionally, in the packaging process, the plurality of wires forming the surface of the stage is electrically connected to each of the projections comprises on the protective layer and the substrate:

[0013] 采用重布线层工艺在所述保护层和所述衬底上形成与各所述凸台上表面电连接的多条导线。 [0013] The process of forming the rewiring layer plurality of wires electrically connected to the surface of each of the bosses on the protective layer and the substrate.

[0014]可选的,在上述封装工艺中,在所述提供衬底之前,包括: [0014] Optionally, in the packaging process, prior to said providing a substrate, comprising:

[0015] 在所述芯片的各电极上分别形成凸台。 [0015] The bosses are formed on each electrode of the chip.

[0016]可选的,在上述封装工艺中,所述凸台为金属块或金属柱。 [0016] Optionally, in the packaging process, the boss is a metallic or metal posts.

[0017] 可选的,在上述封装工艺中,所述衬底由金属、塑料、陶瓷或树脂中的至少一种构成。 [0017] Optionally, in the packaging process, the substrate made of metal, plastic, ceramic or a resin composed of at least one.

[0018] 可选的,在上述封装工艺中,所述芯片为有源芯片或无源芯片。 [0018] Optionally, in the packaging process, the chip is an active chip or a passive chip.

[0019] 可选的,在上述封装工艺中,所述导线为金属线。 [0019] Optionally, in the packaging process, the wire is a metal wire.

[0020] 第二方面,本发明实施例提供了一种芯片的封装结构,包括: [0020] a second aspect, the present invention provides a packaging structure of a chip, comprising:

[0021] 衬底,所述衬底中形成有腔体; [0021] substrate, the substrate is formed with a cavity;

[0022] 至少一个芯片,设置在所述腔体的底面,所述芯片的电极上形成有凸台,所述芯片的电极上表面低于所述衬底的上表面; [0022] at least one chip, disposed on the bottom surface of the cavity, an electrode is formed on a boss of the chip, the substrate surface lower than the upper surface of the upper electrode of the chip;

[0023] 保护层,形成所述腔体中; [0023] protective layer, forming the cavity;

[0024] 多条导线,形成于所述保护层和所述衬底上,且与各所述凸台上表面电连接; [0024] a plurality of wires, and formed on the protective layer on the substrate, and the surface of each stage is electrically connected to the convex;

[0025] 绝缘层,形成于所述导线和所述保护层上,所述绝缘层上形成有至少一个窗口; [0025] The insulating layer formed on the conductor and the protective layer, the upper insulating layer is formed with at least one window;

[0026] 多个焊球,形成于所述绝缘层上,通过所述至少一个窗口与各所述导线电连接。 [0026] The plurality of solder balls, formed on the insulating layer, each of said wires is electrically connected to the at least one window.

[0027] 本发明实施例提供了一种芯片的封装工艺和封装结构,首先在衬底中形成腔体,将至少一个设置有凸台的芯片设置在腔体的底面,并使衬底的上表面高于芯片的电极上表面,在腔体中形成保护层,通过使用腔体和保护层使得芯片被密封起来,避免被损伤;然后在保护层和衬底上形成与各凸台上表面电连接的多条导线,在多条导线和保护层上形成绝缘层,并在绝缘层上形成至少一个窗口,以设置与各导线电连接的焊球,通过使用多条导线和凸台将芯片的电极引出到焊球上,使得通过焊球能够与芯片进行数据传输。 In the bottom surface of the cavity, the [0027] embodiment provides a structure of a packaging process and packaging chip of the invention, the cavity is first formed in the substrate, at least one projection is provided with a chip and a substrate is provided above the surface of the chip on the electrode surface, forming a protective layer in the cavity, by using the cavity and the protective layer such that the chip is sealed, to avoid being damaged; and each boss is formed on the protective layer surface potential and the substrate a plurality of connecting wires, a plurality of wires formed on the insulating layer and the protective layer, and at least one window is formed on the insulating layer, a solder ball is provided to an electrical conductor connected to each of the plurality of wires by use of the chip and the boss electrode lead to the solder ball, making it possible to perform data transmission with the chip through the solder balls.

附图说明 BRIEF DESCRIPTION

[0028]图1A是本发明实施例一中提供的一种芯片的封装工艺流程示意图; [0028] FIG 1A is a process flow diagram of a chip package according to an embodiment of the present invention is provided;

[0029]图1B-1F是本发明实施例一中提供的一种芯片的封装工艺中各步骤的结构剖面示意图; [0029] FIGS. 1B-1F is a configuration process for a chip package according to a provided in the embodiments of the present invention, the steps a schematic sectional view;

[0030]图2为本实施例二中提供的一种芯片的封装工艺一步骤的结构剖面示意图; Structure [0030] FIG 2 A chip package according to the second step of a process provided in the present embodiment a schematic sectional view;

[0031]图3为本实施例三中提供的一种芯片的封装结构剖面示意图; A schematic cross-sectional structure of a chip package provided in the three [0031] The present embodiment 3;

具体实施方式 Detailed ways

[0032]下面结合附图和实施例对本发明作进一步的详细说明。 Drawings and embodiments of the present invention will be further described in detail [0032] below in conjunction. 可以理解的是,此处所描述的具体实施例仅仅用于解释本发明,而非对本发明的限定。 It will be appreciated that the specific embodiments described herein are merely to illustrate the invention, not limitation of the invention. 另外还需要说明的是,为了便于描述,附图中仅示出了与本发明相关的部分而非全部结构。 Also to be noted also that, for convenience of description, the accompanying drawings illustrate only some, but not all of the structure associated with the present invention.

[0033] 实施例一 [0033] Example a

[0034]图1A是本发明实施例一中提供的一种芯片的封装工艺流程示意图,图1B-1F是本发明实施例一中提供的一种芯片的封装工艺中各步骤的结构剖面示意图。 [0034] FIG 1A is a process flow diagram of a chip package according to an embodiment of the present invention is provided in FIG. 1B-1F is a process for packaging a chip according to an embodiment of the present invention in a schematic sectional configuration of each step. 参考图1A-1F,本实施例提供的封装工艺具体包括如下步骤: With reference to FIGS. 1A-1F, the packaging process according to this embodiment includes the following steps:

[0035] 步骤110、提供衬底,在衬底中形成腔体。 [0035] In step 110, a substrate, a cavity formed in the substrate.

[0036] 参考图1B,通过刻蚀、电镀、注塑、压铸等工艺,可以制出带有腔体111的衬底11。 [0036] Referring to Figure 1B, by etching, electroplating, injection molding, casting and other processes, it can be made with the cavity 111 of the substrate 11. 如果芯片的功率较大,则可以选用金属衬底来封装芯片;如果芯片,是高频率芯片,则可以选用陶瓷衬底来封装芯片。 If the power of the chip is large, the metal substrate can be packaged chips selected; if the chip is a high-frequency chip, a ceramic substrate may be chosen to encapsulate the chip. 实际设计中,会根据芯片的特点来选择合适的衬底材料。 In actual design, will be selected according to the characteristics suitable substrate material chip.

[0037] 步骤120、将至少一个设置有凸台的芯片设置在腔体的底面,并使衬底的上表面高于芯片的电极上表面。 [0037] Step 120, the chip is provided with at least a projection provided in a bottom surface of the cavity, and the upper surface of the substrate above the upper surface of the electrode chip.

[0038] 参考图1C,芯片12可以有多个,图中示意性的仅画出一个,。 [0038] Referring to Figure 1C, the chip 12 may have a plurality, of which only one shown schematically. 在芯片12的电极上形成有凸台121,凸台121用于延伸芯片12的电极,使其能够与其他层相连接,比如与导线层中的导线连接。 Formed on the electrode chip 12, a boss 121, the boss 121 for extending the electrode chip 12, it is possible, for example connected to the conductor layer and is connected to the other conductor layer. 在形成凸台121之后,将带有凸台121的芯片12贴在腔体111的底面上,可以采用贴片工艺来实现芯片的贴片过程。 After the formation of the boss 121, the boss 121 with the chip 12 on the bottom surface of the cavity 111, the chip technology may be used to implement the chip placement process. 另外,衬底11的上表面高于芯片12的电极上表面,这样芯片就会完全处于腔体111之中,利于对芯片进行更完善的保护。 Further, the upper surface of the substrate 11 is higher than the upper surface of the electrode chip 12, so that the chip will be completely within the cavity 111, to facilitate better chip protection.

[0039] 步骤130、在腔体中形成保护层,并在保护层和衬底上形成与各凸台上表面电连接的多条导线。 [0039] Step 130, forming a protective layer in the cavity, and forming a plurality of wires electrically connected to the surface projections to each stage on the protective layer and the substrate.

[0040] 参考图1D,在腔体中填充保护层13,保护层13完全覆盖在芯片12之上。 [0040] 1D, a filling in the cavity protective layer 13, protective layer 13 completely covers over the chip 12. 在形成保护层13后,在其上方形成与各凸台121的上表面电连接的多条导线14,从而将各芯片12的电极引出到导线14上。 After forming the protective layer 13, a plurality of wires 14 electrically connected to the upper surface of each boss 121 at the top thereof, so that the electrodes of the chip 12 to the lead wires 14.

[0041] 步骤140、在多条导线和保护层上形成绝缘层,并在绝缘层上形成至少一个窗口。 [0041] Step 140, the insulating layer is formed on the plurality of wires and the protective layer, and at least one window is formed on the insulating layer.

[0042] 参考图1E,在所有导线14和保护层13上形成绝缘层15,在绝缘层15中形成至少一个窗口151,窗口151用于将第一导线14的表面露出。 [0042] Referring 1E, the insulating layer is formed on all of the wires 14 and the protective layer 1315, the insulating layer 15 is formed in the at least one window 151, the window 151 for the surface of the first lead 14 is exposed. 在形成窗口151时,可以选择刻蚀工艺或者其他工艺来完成这一过程。 When the window 151 is formed, the etching process may be selected, or other processes to complete this process.

[0043] 步骤150、通过窗口设置与各导线电连接的焊球。 [0043] Step 150, each wire is electrically connected to the solder balls through the window.

[0044] 参考图1F,在形成窗口151后,在窗口151所在位置形成与各导线14电连接的焊球16,从而通过焊球16将芯片12的电极引出。 [0044] Referring 1F, a window 151 is formed in the solder ball 14 is electrically connected to the lead wires 16 is formed at a position where the window 151, so that the solder balls 16 by lead 12 of the chip electrodes.

[0045] 可选的,在上述实施例的基础上,在提供衬底之前,包括:在芯片12的各电极上分别形成凸台121。 [0045] Alternatively, in the above embodiment, before the substrate is provided, comprising: projections 121 are formed on each electrode 12 of the chip. 可以选择通过电镀、植球或印刷等工艺在芯片12的各电极上形成凸台121。 You may be selected by electroplating boss 121, bumping or printing process is formed on each electrode 12 of the chip.

[0046]可选的,在上述实施例的基础上,凸台121可以为金属块或金属柱。 [0046] Alternatively, in the above embodiment, the boss 121 may be a metal block or metal posts. 根据实际需要,凸台也可以设计为其他形状。 According to actual needs, the boss can also be designed in other shapes.

[0047] 可选的,在上述实施例的基础上,衬底11可以由金属、塑料、陶瓷或树脂中的至少一种构成。 [0047] Alternatively, in the above embodiment, the substrate 11 may be composed of at least one metal, plastic, ceramic or resin. 根据要封装保护的芯片12的特点,可以选择相应的衬底材料来形成衬底,使得能够更有效的保护芯片12。 According to the characteristics of the protection to be packaged chip 12, you can select the appropriate substrate material to form the substrate, making it possible to more effectively protect the chip 12.

[0048] 可选的,在上述实施例的基础上,导线14可以为金属线,根据实际需要,也可以为其他导电材料,比如透明电极材料等。 [0048] Alternatively, in the above embodiment, the wire 14 may be a metal wire, according to actual needs, or may be other conductive material, such as a transparent electrode material or the like.

[0049] 可选的,在上述实施例的基础上,芯片为有源芯片或无源芯片。 [0049] Alternatively, in the above embodiment, the active chip or a passive chip chip.

[0050] 本发明提供了一种芯片的封装工艺,首先在衬底中形成腔体,将至少一个设置有凸台的芯片设置在腔体的底面,并使衬底的上表面高于芯片的电极上表面,在腔体中形成保护层,通过使用腔体和保护层使得芯片被密封起来,避免被损伤;然后在保护层和衬底上形成与各凸台上表面电连接的多条导线,在多条导线和保护层上形成绝缘层,并在绝缘层上形成至少一个窗口,以设置与各导线电连接的焊球,通过使用多条导线和凸台将芯片的电极引出到焊球上,使得通过焊球能够与芯片进行数据传输。 [0050] The present invention provides a process for packaging the chip, the substrate is first formed in the cavity, at least one chip is provided with a projection provided on the bottom surface of the cavity, the upper surface of the chip and the substrate is greater than on the electrode surface, forming a protective layer in the cavity, by using the cavity and the protective layer such that the chip is sealed, to avoid being damaged; and then forming a plurality of wires electrically connected to the surface projections to each stage on the protective layer and the substrate forming an insulating layer on the plurality of wires and the protective layer, and at least one window is formed on the insulating layer to each wire is provided with the solder balls are electrically connected by using a plurality of wires and the boss of the chip into the ball electrode extraction on, enabling data transmission through the solder balls and the chip.

[0051] 实施例二 [0051] Second Embodiment

[0052] 本实施例以上述实施例为基础,将所述在所述腔体中形成保护层具体为:处理所述保护层和各所述凸台以露出各所述凸台的上表面,且使各所述凸台的上表面、所述保护层的上表面与所述衬底的上表面平齐。 [0052] In the present embodiment based on the above-described embodiments, the protective layer is specifically formed in the cavity: processing the protective layer and each of the bosses at the exposed surface of each of the boss, and the upper surface of each of the boss, the upper surface of the protective layer is flush with the upper surface of the substrate.

[0053]图2为本实施例二中提供的一种芯片的封装工艺一步骤的结构剖面示意图,参考图2,处理保护层13和各凸台121以露出各凸台121的上表面,在形成保护层13后,保护层13一般会覆盖在各凸台121的上表面,则需要对保护层和各凸台121进行研磨或者刻蚀,使各凸台121的上表面漏出,且使各凸台121的上表面、保护层13的上表面与衬底11的上表面平齐。 Structure [0053] FIG 2 A chip package according to the second step of a process provided in the present embodiment a schematic sectional view, with reference to FIG. 2, the process and the protective layer 13 to expose the respective bosses 121 on the surface of each projection 121, in after 13, protective layer 13 typically covers the surface of each boss 121 forming the protective layer, the protective layer is required for each of the bosses 121 and polished or etched, the upper surface of each projection 121 from leaking, and the respective the upper surface of the boss 121, the upper surface of the protective layer 13 and the substrate 11 is flush with the upper surface.

[0054] 可选的,在上述实施例的基础上,在所述保护层和所述衬底上形成与各所述凸台上表面电连接的多条导线包括:采用重布线层工艺在所述保护层和所述衬底上形成与各所述凸台上表面电连接的多条导线。 [0054] Alternatively, in the above embodiments, the protective layer is formed on said substrate and said plurality of conductors each electrically connected to the surface of said boss comprises: using the process of the redistribution layer forming a plurality of wires electrically connected to the surface of each of the bosses on said protective layer and the substrate. 具体的,采用重布线层工艺在保护层13和衬底11上上形成与各凸台121上表面电连接的导线。 Specifically, using the process of forming the rewiring layer on the respective wire and electrically connected to the boss 121 on the surface of the protective layer 13 and the substrate 11.

[0055] 可选的,在上述实施例的基础上,在所述提供衬底之前,包括:在所述芯片的各电极上分别形成凸台。 [0055] Alternatively, in the above embodiment, before the providing of the substrate, comprising: a projection formed on each electrode of the chip. 具体的,选用在芯片12的电极表面进行电镀、植球和/或印刷等工艺来形成凸台121。 Specifically, the boss 121 selected by plating, bumping and / or printing process on the surface of the electrode chip 12 is formed.

[0056] 本发明提供了一种芯片的封装工艺,首先在衬底中形成腔体,将至少一个设置有凸台的芯片设置在腔体的底面,并使衬底的上表面高于芯片的电极上表面,处理保护层和各凸台以露出各凸台的上表面,且使各凸台的上表面、保护层的上表面与衬底的上表面平齐,通过使用腔体和保护层使得芯片被密封起来,避免被损伤;然后在保护层和衬底上形成与各凸台上表面电连接的多条导线,在多条导线和保护层上形成绝缘层,并在绝缘层上形成至少一个窗口,以设置与各导线电连接的焊球,通过使用多条导线和凸台将芯片的电极引出到焊球上,使得通过焊球能够与芯片进行数据传输。 [0056] The present invention provides a process for packaging the chip, the substrate is first formed in the cavity, at least one chip is provided with a projection provided on the bottom surface of the cavity, the upper surface of the chip and the substrate is greater than on the electrode surface, the protective layer and the treatment station to expose each convex surface of each boss and the upper surface of each boss, the upper surface of the upper surface of the substrate is flush with the protective layer, by using the cavity and the protective layer such that the chip is sealed, to avoid injury; then formed on the protective layer and the substrate a plurality of wires electrically connected to each surface of the boss, the insulating layer is formed on the plurality of wires and a protective layer formed on the insulating layer and at least one window, to set a solder ball electrically connected to each conductor, by using a plurality of wires and the boss to the chip electrode lead solder balls, so that data transmission can be performed by the chip solder balls.

[0057] 实施例三 [0057] Example three

[0058]图3为本实施例三中提供的一种芯片的封装结构剖面示意图,参考图3,本发明实施例中提供的一种芯片的封装结构,具体包括:衬底31、至少一个芯片32、保护层33、多条第一导线34、绝缘层35和多个焊球36。 A schematic cross-sectional structure of a chip package provided in the three [0058] The present embodiment of FIG. 3, with reference to FIG. 3, the structure of a chip package provided in the embodiment of the present invention, comprises: a substrate 31, at least one chip 32, protective layer 33, a first plurality of wires 34, the insulating layer 35 and a plurality of solder balls 36.

[0059] 参考图3,具体的,所述衬底31中形成有腔体; [0059] Referring to FIG 3, specifically, with a cavity 31 formed in the substrate;

[0060] 至少一个芯片32,设置在所述腔体的底面,所述芯片32的电极上形成有凸台321,所述芯片32的电极上表面低于所述衬底31的上表面; [0060] at least one chip 32, the electrode disposed on the bottom surface of the cavity, the die 32 is formed with a projection 321, the surface of the substrate 31 below the upper surface of the upper electrode chip 32;

[0061] 保护层33,形成所述腔体中; [0061] The protective layer 33 is formed in the cavity;

[0062] 多条导线34,形成于所述保护层33和所述衬底31上,且与各所述凸台321上表面电连接; [0062] The plurality of wires 34, formed on the protective layer 33 and the substrate 31, and is electrically connected to the upper surface of each of the boss 321;

[0063] 绝缘层35,形成于所述导线34和所述保护层33上,所述绝缘层35上形成有至少一个窗口; [0063] The insulating layer 35 is formed on the wire 34 and the protective layer 33, the insulating layer is formed with at least one window 35;

[0064] 多个焊球36,形成于所述绝缘层35上,通过所述至少一个窗口与各所述导线34电连接。 [0064] The plurality of solder balls 36 are formed on the insulating layer 35, electrically connected to the lead 34 through each of said at least one window.

[0065] 本发明实施例提供了一种芯片的封装结构,首先在衬底中形成腔体,将至少一个设置有凸台的芯片设置在腔体的底面,并使衬底的上表面高于芯片的电极上表面,在腔体中形成保护层,通过使用腔体和保护层使得芯片被密封起来,避免被损伤;然后在保护层和衬底上形成与各凸台上表面电连接的多条导线,在多条导线和保护层上形成绝缘层,并在绝缘层上形成至少一个窗口,以设置与各导线电连接的焊球,通过使用多条导线和凸台将芯片的电极引出到焊球上,使得通过焊球能够与芯片进行数据传输。 [0065] The embodiment provides a package structure of a chip of the present invention, a cavity is first formed in the substrate, the chip is provided with at least a projection provided in a bottom surface of the cavity, and the upper surface of the substrate is greater than upper surface of the chip electrodes, forming a protective layer in the cavity, by using the cavity and the protective layer such that the chip is sealed, to avoid injury; electrically connected to each surface of the plurality of bosses is then formed on the protective layer and the substrate wires, a plurality of wires formed on the insulating layer and the protective layer, and at least one window is formed on the insulating layer, is provided with solder balls in connecting electrical wires, by using a plurality of wires and the boss to the chip electrode extraction solder balls, so that data transmission can be performed by the chip solder balls.

[0066] 注意,上述仅为本发明的较佳实施例及所运用技术原理。 [0066] Note that, examples, and techniques using the principles described above is only the preferred embodiment of the present invention. 本领域技术人员会理解,本发明不限于这里所述的特定实施例,对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本发明的保护范围。 Those skilled in the art will appreciate, the present invention is not limited to the particular embodiments described herein, the skilled person that various obvious changes, and substitutions without readjustment departing from the scope of the present invention. 因此,虽然通过以上实施例对本发明进行了较为详细的说明,但是本发明不仅仅限于以上实施例,在不脱离本发明构思的情况下,还可以包括更多其他等效实施例,而本发明的范围由所附的权利要求范围决定。 Thus, while the above embodiments of the present invention has been described in detail, but the present invention is not limited to the above embodiments, without departing from the spirit of the present invention may further comprise additional other equally effective embodiments, the present invention by the scope of the appended claims range determination.

Claims (9)

1.一种芯片的封装工艺,其特征在于,包括: 提供衬底; 在所述衬底中形成腔体,将至少一个设置有凸台的芯片设置在所述腔体的底面,并使所述衬底的上表面高于所述芯片的电极上表面,其中所述凸台位于所述芯片的电极上;在所述腔体中形成保护层,并在所述保护层和所述衬底上形成与各所述凸台上表面电连接的多条导线; 在所述多条导线和所述保护层上形成绝缘层,并在所述绝缘层上形成至少一个窗口,以设置与各所述导线电连接的焊球。 1. A chip packaging process, characterized by comprising: providing a substrate; forming a bottom surface of the cavity, at least one chip is provided with a projection disposed in the cavity in the substrate, and the higher than the upper surface of said substrate of the chip on the electrode surface, wherein said boss is located on the electrode of the chip; forming a protective layer in the cavity, and said protective layer and said substrate is formed on the surface of a plurality of wires electrically connected to each of said bosses; forming an insulating layer on the plurality of wires and the protective layer, and at least one window is formed on the insulating layer, is provided to each of the said wire is electrically connected to the solder balls.
2.根据权利要求1所述的封装工艺,其特征在于,所述在所述腔体中形成保护层包括: 在所述腔体中形成保护层; 处理所述保护层和各所述凸台以露出各所述凸台的上表面,且使各所述凸台的上表面、所述保护层的上表面与所述衬底的上表面平齐。 The packaging process according to claim 1, wherein said protective layer is formed in the cavity comprises: forming a protective layer in the cavity; processing the protective layer and each of the bosses to expose the upper surface of each of the boss and the upper surface of each of the boss, the upper surface of the protective layer is flush with the upper surface of the substrate.
3.根据权利要求1或2所述的封装工艺,其特征在于,所述在所述保护层和所述衬底上形成与各所述凸台上表面电连接的多条导线包括: 采用重布线层工艺在所述保护层和所述衬底上形成与各所述凸台上表面电连接的多条导线。 The packaging process of claim 1 or claim 2, wherein said plurality of wires forming the surface of the stage is electrically connected to each of the projections comprises on the protective layer and the substrate: The weight process of forming a wiring layer plurality of wires electrically connected to the surface of each of the bosses on the protective layer and the substrate.
4.根据权利要求1或2所述的封装工艺,其特征在于,在所述提供衬底之前,包括: 在所述芯片的各电极上分别形成凸台。 The packaging process of claim 1 or claim 2, wherein, prior to said providing a substrate, comprising: a projection formed on each electrode of the chip, respectively.
5.根据权利要求1所述的封装工艺,其特征在于,所述凸台为金属块或金属柱。 The packaging process according to claim 1, wherein the boss is a metallic or metal posts.
6.根据权利要求1所述的封装工艺,其特征在于,所述衬底由金属、塑料、陶瓷或树脂中的至少一种构成。 The packaging process according to claim 1, wherein said substrate is made of metal, plastic, ceramic or a resin composed of at least one.
7.根据权利要求1所述的封装工艺,其特征在于,所述芯片为有源芯片或无源芯片。 The packaging process according to claim 1, wherein the chip is an active chip or a passive chip.
8.根据权利要求1所述的封装工艺,其特征在于,所述导线为金属线。 8. The packaging process according to claim 1, wherein the wire is a metal wire.
9.一种芯片的封装结构,其特征在于,包括: 衬底,所述衬底中形成有腔体; 至少一个芯片,设置在所述腔体的底面,所述芯片的电极上形成有凸台,所述芯片的电极上表面低于所述衬底的上表面; 保护层,形成所述腔体中; 多条导线,形成于所述保护层和所述衬底上,且与各所述凸台上表面电连接; 绝缘层,形成于所述导线和所述保护层上,所述绝缘层上形成有至少一个窗口; 多个焊球,形成于所述绝缘层上,通过所述至少一个窗口与各所述导线电连接。 9. A chip package structure, characterized by comprising: a substrate with a cavity formed in the substrate; at least one chip, an electrode is provided on the bottom surface of the cavity, the die has a convex stage, lower than the upper surface of the chip on the electrode surface of the substrate; a protective layer, forming the cavity; a plurality of wires formed on the protective layer and the substrate, and each of the electrically connecting said boss surface; an insulating layer formed on the conductor and the protective layer, the at least one window is formed on the insulating layer; a plurality of solder balls, formed on the insulating layer, by the at least one window and each of said wires is electrically connected.
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CN106129015A (en) * 2016-07-11 2016-11-16 华天科技(昆山)电子有限公司 Packaging structure comprising interconnected embedded chips and flip chips and manufacturing method of packaging structure

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