CN106415827A - 冷却器一体型半导体模块 - Google Patents
冷却器一体型半导体模块 Download PDFInfo
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Abstract
提供以紧凑的结构具有优异的散热性能,且与冷却器的焊料接合的可靠性高、经济性好的冷却器一体型半导体模块。该冷却器一体型半导体模块具备:绝缘基板(6)、设置于所述绝缘基板(6)的正面的电路层(5)、与所述电路层(5)电连接的半导体元件(3)、设置于所述绝缘基板(6)的背面的金属层(7)、覆盖所述绝缘基板(6)、所述电路层(5)、所述半导体元件(3)和所述金属层(7)的一部分的密封树脂(2)、配置于所述金属层(7)的下表面侧的冷却器(9)、至少配置于所述密封树脂(2)的与所述冷却器(9)相向的面的镀覆层(10)、以及将所述镀覆层(10)与所述冷却器(9)进行连接的接合部件(8)。
Description
技术领域
本发明涉及一种在控制大电流、高电压的电力变换装置等中使用的电力用半导体模块。
背景技术
在以混合动力汽车、电动汽车等为代表的使用马达的机器中,一直期望节能效果优异的电力变换装置。在该电力变换装置中广泛使用有搭载了例如IGBT(Insulated Gate Bipolar Transistor:绝缘栅双极型晶体管)等电力用(以下,称为功率)功率半导体元件的功率半导体模块。为了将向功率半导体元件通入大电流时产生的热量有效地进行散热,要求功率半导体模块为连接于冷却器、小型且散热性能优异的结构。
例如,下述的专利文献1所公开的半导体模块具备在陶瓷基板的两个面配置金属层而成的绝缘电路基板。在绝缘电路基板的一侧的主表面上接合有多个功率半导体元件,在另一侧的主表面上接合有金属制的厚的散热基板。该绝缘电路基板被容纳于树脂壳体中,注入凝胶状树脂,从而构成功率半导体模块。并且,该半导体模块通过螺栓和螺母隔着散热油脂被固定于冷却器。
另一方面,在下述的专利文献2中公开了在将树脂密封模块与冷却器进行焊料接合后,在焊料接合部的周围区域的缝隙中填充密封树脂而成的半导体模块。
此外,在下述的专利文献3中公开了如下半导体模块,该半导体模块具备:金属块、通过焊料层接合于该金属块上的半导体元件、对上述金属块与上述半导体元件进行塑模(mold)而成的树脂塑模部,并且在上述金属块表面的镀覆区域和粗糙化区域之中,上述半导体元件搭载于镀覆区域。
现有技术文献
专利文献
专利文献1:日本特开2008-288414号公报
专利文献2:日本特开2012-142465号公报
专利文献3:日本特开2012-146919号公报
发明内容
技术问题
然而,在专利文献2所记载的半导体模块中,存在如下问题:增加将树脂填充到包围焊料接合部的密封树脂下表面与冷却器之间的缝隙中的工序的问题、和/或在接合于冷却器的半导体模块有多个的情况下不容易将树脂可靠地填充到缝隙中的问题。
另一方面,在专利文献3所记载的半导体模块中,由于在半导体元件与冷却板之间存在形成有镀覆区域和粗糙化区域的金属块,因此成为密封树脂与半导体元件、金属块、焊料、冷却板直接接触的结构,不仅不能称为紧凑的结构,还存在必需确保在各种界面上的粘合性的问题。
因此,考虑上述问题点,本发明的目的在于提供一种冷却器一体型半导体模块,该冷却器一体型半导体模块以紧凑的结构具有优异的散热性能,且与冷却器的焊料接合的可靠性高、经济性好。
技术方案
为了解决上述课题,实现该目的,本发明的冷却器一体型半导体模块的特征在于,具备:绝缘基板;电路层,设置于上述绝缘基板的正面;半导体元件,与上述电路层电连接;金属层,设置于上述绝缘基板的背面;密封树脂,覆盖上述绝缘基板、上述电路层、上述半导体元件和上述金属层的一部分;冷却器,配置于上述金属层的下表面侧;镀覆层,至少配置于上述密封树脂的与上述冷却器相向的面;以及接合部件,将上述镀覆层与上述冷却器进行连接。
优选地,在本发明的冷却器一体型半导体模块中,上述密封树脂的与上述镀覆层的界面的粗糙度以算术平均粗糙度计为5μm以上。
优选地,在本发明的冷却器一体型半导体模块中,至少上述密封树脂的与上述冷却器相向的面是利用选自化学蚀刻、机械切削、喷砂法、激光处理中的任一方法进行粗糙化而成的面,或者是通过在传递成型用金属模具上预先形成的粗糙面来成形的面。
优选地,在本发明的冷却器一体型半导体模块中,上述接合部件的厚度为250μm以下。
优选地,在本发明的冷却器一体型半导体模块中,上述接合部件是组成为Sn8%Sb3%Ag的焊料。
优选地,在本发明的冷却器一体型半导体模块中,上述镀覆层具有1μm以上且5μm以下的厚度,并含有选自铜、镍、金、银中的至少一种以上的金属。
技术效果
根据本发明,能够提供一种以紧凑的结构具有优异的散热性能,且与冷却器的焊料接合的可靠性高、经济性好的冷却器一体型半导体模块。
附图说明
图1是表示本发明的冷却器一体型半导体模块的一个实施方式的剖视图。
图2是示出本发明的冷却器一体型半导体模块的比较例的剖视图。
图3是本发明的冷却器一体型半导体模块的实施例与比较例的塑性应变幅的比率(%)的比较图。
符号说明
1:绝缘布线基板
2:密封树脂
3:半导体元件
4:焊料层
5:电路层
6:绝缘基板、陶瓷基板
7:金属层
8、18:焊料层
9:冷却器、散热片底座
9a:散热片
9b:制冷剂流路
10:镀覆层
11、20:半导体模块
100、200:冷却器一体型半导体模块
具体实施方式
以下,参照附图对本发明的冷却器一体型半导体模块的一个实施方式进行说明。应予说明,在以下的实施例的说明以及附图中,对同样的结构标记相同的符号,并省略重复的说明。此外,为了易于观察或易于理解,在实施例中进行说明的附图并未以正确的比例、尺寸比进行绘制。本发明只要未超出其主旨,就不限于以下所说明的实施例的记载。
图1中,通过剖视图示出了本发明的冷却器一体型半导体模块的一个实施方式。冷却器一体型半导体模块100具备:具有绝缘布线基板1和半导体元件3的半导体模块11、以及热连接于半导体模块11的冷却器9。绝缘布线基板1具有绝缘基板6、配置在绝缘基板6的一侧的主表面的电路层5、配置在绝缘基板6的另一侧的主表面的金属层7,并在电路层5上通过焊料层4接合有半导体元件3,这些全部被密封树脂2所被覆。在本发明中,在半导体模块11的与冷却器9相向的面上设置有镀覆层10。
对于半导体元件3的种类并不特别限定。例如,可以是IGBT、功率MOSFET(Metal Oxide Semiconductor Field Effect Transistor:金属氧化物半导体场效应晶体管)或FWD(Free Wheeling Diode:续流二极管),还可以是将它们形成在一个半导体元件中的RB-IGBT(Reverse Blocking-Insulated GateBipolar Transistor:逆阻型绝缘栅双极型晶体管)或RC-IGBT(ReverseConducting-Insulated Gate Bipolar Transistor:反向导通型绝缘栅双极型晶体管)。
在半导体元件3的上表面的电极膜(未图示)上导电连接有包含导电性良好的铜、铝合金等金属,并由引脚布线、引线布线和/或引线框布线等构成的电路布线(未图示)的一侧的端部。此外,该电路布线(未图示)的另一侧的端部连接于从密封树脂2引到外部的外部连接端子(未图示)。半导体元件3的下表面的电极膜(未图示)通过焊料层4热性能良好且电气性良好地连接于电路层5的所需的位置。电路层5为铜等导电性良好的金属箔等被预先接合于绝缘性的陶瓷基板等绝缘基板上表面而成的电路层。作为焊料层4的焊料的种类,可使用SnSb系、SnSbAg系的无铅焊料等。但是,优选该焊料层4的焊料的熔点比后述的焊料层8的焊料的熔点温度高,以使焊料层4在焊料层8的形成时不会再次熔融。该电路层5与预先接合于绝缘基板6的背面侧的金属层7以使它们两层间具有电气上可靠绝缘的预定的爬电距离的方式分别配置在从绝缘基板的外周边靠向内侧的位置。金属层7优选包括导电性良好的铜等。
冷却器9在内部具备被多个散热片9a分隔的制冷剂流路9b。该冷却器9通过焊料层8直接接合于上述绝缘基板6的下表面侧的金属层7。与在半导体模块背面和冷却器之间存在厚的散热基板或导热性差的散热油脂的以往的接合结构相比,本发明所具备的接合结构在尺寸小巧的情况下热阻小,能够改善冷却效率(散热性能)。
应予说明,在图1所示的冷却器一体型半导体模块100的剖视图中,仅搭载有一个半导体元件3,但是二合一(2in1)模块等则并联连接多个半导体元件从而能够增大额定输出。例如,可以采用将三个无散热基板的二合一结构的树脂密封模块单元(以下,仅称为单元)焊料接合于冷却器的上表面的六合一半导体模块构成、或将六个一合一(1in1)结构的树脂密封单元进行排列的单元集合结构的模块构成。这样,在将分割得较小的单元集合的构成的无散热基板结构的模块中,能够减小树脂体积,从而降低应力,抑制密封树脂的龟裂。此外,在本发明中,通过镀覆层10来确保半导体模块11与冷却器9的接合强度,因此,即使增加半导体元件数量,也能够防止由起因于热膨胀系数差的热应力(翘曲应力)引起的龟裂、剥离等。
此外,也可以将多个半导体元件3的种类替换为种类各不相同的半导体元件。例如,可以为在将IGBT与FWD两个元件排列并进行焊料连接之后,以反向并联连接的方式进行布线连接的结构。
进一步地,图1中也可以在电路层5的上表面或金属层7的下表面插入铜等导热性良好的金属块(未图示)并进行焊料接合。通过该金属块的插入,能够将在半导体元件3产生的热量立即传递到热容大且热阻比焊料小的金属块,能够进一步降低热阻。此外,在金属层7的下部设置金属块的结构能够抑制在焊料接合到冷却器9时产生的热应力(翘曲应力),还能够降低对厚度薄的绝缘基板6的不良影响,因此是优选的。能够降低上述不良影响的理由是因为起因于绝缘基板6与冷却器9之间的热膨胀系数差的热应力被夹在中间的金属块所抑制。
在本发明的冷却器一体型半导体模块中,覆盖半导体模块11的密封树脂2以金属层7的背面露出的方式而形成。该密封树脂2只要是具有预定的绝缘性能,且成型性良好的树脂即可,并不特别限定其树脂材料,例如优选使用环氧树脂等。
在本发明的冷却器一体型半导体模块中,在露出于半导体模块11的下表面的金属层7和该金属层7的周围的密封树脂2的下表面形成有镀覆层10。如果在半导体模块11的下表面的整个面设置镀覆层10,则能够抑制在焊料接合后产生的起因于上述热膨胀系数差的翘曲。
对于镀覆层10并不特别限定,可以优选使用例如铜、镍、金、银等金属的单层膜,或包含它们的金属膜的层叠膜,或含有这些金属中的至少一种以上的金属的合金膜。此外,镀覆层10的厚度优选为1μm以上且5μm以下的范围。如果镀覆层10的厚度小于1μm则过于薄,因此在与冷却器9进行焊料接合时,镀覆层10被焊料熔蚀而消失,抑制翘曲的功能变弱,产生焊料龟裂、焊料断裂的问题。另一方面,大于5μm的厚度会导致成本上升。
如果被粘着该镀覆层10的密封树脂2的下表面被粗糙化,则镀覆层10对密封树脂2的粘附性提高,因此特别优选。作为将树脂下表面粗糙化的方法,可以使用例如化学蚀刻、机械切削、喷砂(Sandblast)、激光处理或预先将成型金属模具的表面进行粗糙化等方法。特别地,如果粗糙化的程度以JIS标准B0601所规定的算术平均粗糙度计为5μm以上,则镀覆层10的粘附强度变高,因此是优选的。与此相对,如果表面粗糙度小于5μm,则粘附强度低,镀覆层变得容易从树脂下表面剥离。例如,如果镀覆层10在焊料接合时或其后的热循环(Heat cycle)后从密封树脂的下表面剥离,则由于热应力而在绝缘布线基板产生翘曲,因此不优选。如果在镀覆层10的形成前将密封树脂2的下表面粗糙化从而提高镀覆层10与密封树脂2的粘附强度,则能够防止镀覆层10的剥离,从而防止翘曲。
在本发明的冷却器一体型半导体模块中,形成于半导体模块11的下表面的镀覆层10通过焊料层8与冷却器9接合。应予说明,由于接合半导体模块11与冷却器9的工序在半导体模块11的制造工序中的树脂密封工序之后,所以如果半导体模块11与冷却器9的接合时的焊接温度高,则产生因密封树脂2的收缩应力导致半导体元件3损坏的问题。因此,焊料层8优选为熔点低且高强度的SnSbAg系。特别地,在本发明中,在密封树脂2的下表面的整个面粘着有镀覆层10,并将半导体模块11的下表面的整个面与冷却器9进行焊料接合。其结果,即使在焊料接合工序中在焊料上产生龟裂,也由于焊料的接合面积大,而能够使从焊料层的端部产生的焊料龟裂的容许长度加长,能够期待可靠性的提高。此外,由于能够将半导体模块11的密封树脂下表面整个面固定于冷却器,所以能够抑制在温度循环中的半导体模块11的变形,提高焊料层8的可靠性(例如,龟裂的抑制),防止树脂断裂等不良。
如以上所说明,根据本发明的实施方式,能够提高冷却器一体型半导体模块100的可靠性。
在未采用本发明的实施方式的情况下,可预料产生如下问题。在图2所示的冷却器一体化半导体模块200中,在焊料层18的周围的密封树脂2与冷却器9之间产生缝隙。由于在绝缘布线基板1与冷却器9的线性热膨胀系数上存在差异,所以起因于该差异的热应力的影响容易表现在厚度薄、机械强度低的绝缘布线基板1上。其结果,有可能在绝缘布线基板1上容易产生变形,使焊料接合部18的可靠性成为问题。此外,在将无散热基板结构的半导体模块20通过嵌件成型(Insert molding)进行树脂密封的情况下,如果搭载在模块20内的功率半导体元件3的数量逐渐增加,则树脂体积变得过大,变得容易在树脂上产生龟裂。
实施例
以下,对通过热应力模拟来预测冷却器一体型半导体模块的温度循环(-40℃~105℃)的可靠性的实施例进行说明。
[实施例]
图1中示出了用于实施例的计算的冷却器一体型半导体模块100的剖面。半导体模块11的绝缘布线基板1具备:厚度0.32mm的以氮化硅为主要成分的陶瓷制的绝缘基板6、配置在绝缘基板6的一侧的主表面的厚度0.4mm的由铜合金构成的电路层5、以及配置在绝缘基板6的另一侧的主表面的厚度0.4mm的由铜合金构成的金属层7。在电路层5上通过SnSb系焊料层4接合有一个IGBT结构的半导体元件3。对绝缘布线基板1和半导体元件3进行被覆的密封树脂2通过环氧树脂的嵌件成型而形成。并且,在半导体模块11的背面的整个面配置有厚度5μm的镍镀覆层10。另一方面,冷却器9具备:通过铝合金(A6063)的挤出成型而形成的厚度1mm的外壳、以及厚度0.8mm的散热片。半导体模块11通过厚度0.25mm的Sn8%Sb3%Ag焊料层8与冷却器9连接。金属组成比率以质量百分比表示。即,包含:Sn 89%、Sb 8%、Ag 3%。但是,在各组成比率中,也可以包含在焊料的生产工序中不可避免的微量的杂质。
[比较例]
图2中示出了用于比较例的计算的冷却器一体型半导体模块200的剖面。在半导体模块20的背面未形成有镍镀覆层10,且在焊料层18的周围区域,在密封树脂2的下表面与冷却器9之间产生有缝隙。但是,除此以外的构成与实施例相同。
[热应力模拟]
在热应力模拟中,计算使整个半导体模块的温度从-40℃变化到105℃时,在焊料层8产生的塑性应变幅(%),将计算结果示于图3。
通常,焊料的低周疲劳寿命遵循下述(1)式的曼森-科菲定律(Manson-Coffin law)。
ΔεpNfb=C …(1)
(Δεp:塑性应变幅,Nf:疲劳寿命,b、C:基于材料的常数)
根据图3,如果本发明的冷却器一体型半导体模块的塑性应变幅比率以比较例的塑性应变幅比率为100%,则本发明中为20%,降低到五分之一。因此,如果遵循曼森-科菲定律,则塑性应变幅小的本发明的冷却器一体型半导体模块的寿命变得更长。
根据以上说明的本发明的实施例,没有用于利用螺栓螺母将半导体模块固定于冷却器所需的以往的散热基板,还不需要散热油脂,因此外形紧凑,散热性能变高。在将半导体模块直接焊料接合于冷却器时,由于焊料接合部扩展到半导体模块下表面的整个镀覆层,所以与没有镀覆层的以往半导体模块相比,焊料接合部的良品率变高,可靠性提高。
Claims (6)
1.一种冷却器一体型半导体模块,其特征在于,具备:
绝缘基板;
电路层,设置于所述绝缘基板的正面;
半导体元件,与所述电路层电连接;
金属层,设置于所述绝缘基板的背面;
密封树脂,覆盖所述绝缘基板、所述电路层、所述半导体元件和所述金属层的一部分;
冷却器,配置于所述金属层的下表面侧;
镀覆层,至少配置于所述密封树脂的与所述冷却器相向的面;以及
接合部件,将所述镀覆层与所述冷却器进行连接。
2.根据权利要求1所述的冷却器一体型半导体模块,其特征在于,
所述密封树脂的与所述镀覆层的界面的粗糙度以算术平均粗糙度计为5μm以上。
3.根据权利要求2所述的冷却器一体型半导体模块,其特征在于,
至少所述密封树脂的与所述冷却器相向的面是利用选自化学蚀刻、机械切削、喷砂法、激光处理中的任一方法进行粗糙化而成的面,或者是通过在传递成型用金属模具上预先形成的粗糙面来成形的面。
4.根据权利要求1所述的冷却器一体型半导体模块,其特征在于,
所述接合部件的厚度为250μm以下。
5.根据权利要求1所述的冷却器一体型半导体模块,其特征在于,
所述接合部件是组成为Sn8%Sb3%Ag的焊料。
6.根据权利要求1所述的冷却器一体型半导体模块,其特征在于,
所述镀覆层具有1μm以上且5μm以下的厚度,并含有选自铜、镍、金、银中的至少一种以上的金属。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007184315A (ja) * | 2006-01-04 | 2007-07-19 | Hitachi Ltd | 樹脂封止型パワー半導体モジュール |
JP2007294626A (ja) * | 2006-04-25 | 2007-11-08 | Hitachi Ltd | 半導体パワーモジュール |
US20120168919A1 (en) * | 2011-01-04 | 2012-07-05 | Eom Joo-Yang | Semiconductor package and method of fabricating the same |
US20120289137A1 (en) * | 2011-05-09 | 2012-11-15 | Robert Bruce Amesbury | Device for killing wounded fowl |
WO2013118478A1 (ja) * | 2012-02-09 | 2013-08-15 | 富士電機株式会社 | 半導体装置 |
CN103765577A (zh) * | 2011-09-26 | 2014-04-30 | 日立汽车系统株式会社 | 功率模块 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3841768B2 (ja) | 2003-05-22 | 2006-11-01 | 新光電気工業株式会社 | パッケージ部品及び半導体パッケージ |
US7228020B2 (en) * | 2004-08-31 | 2007-06-05 | Finisar Corporation | Optoelectronic arrangement having a surface-mountable semiconductor module and a cooling element |
JP4525636B2 (ja) * | 2006-06-09 | 2010-08-18 | 株式会社日立製作所 | パワーモジュール |
US8004075B2 (en) | 2006-04-25 | 2011-08-23 | Hitachi, Ltd. | Semiconductor power module including epoxy resin coating |
JP5061717B2 (ja) | 2007-05-18 | 2012-10-31 | 富士電機株式会社 | 半導体モジュール及び半導体モジュールの製造方法 |
JP5383717B2 (ja) | 2011-01-04 | 2014-01-08 | 三菱電機株式会社 | 半導体装置 |
JP5251991B2 (ja) | 2011-01-14 | 2013-07-31 | トヨタ自動車株式会社 | 半導体モジュール |
JP6093186B2 (ja) * | 2013-01-11 | 2017-03-08 | 本田技研工業株式会社 | 半導体モジュール用冷却器 |
JP5751273B2 (ja) * | 2013-04-02 | 2015-07-22 | トヨタ自動車株式会社 | 半導体装置 |
JP6337957B2 (ja) * | 2014-03-19 | 2018-06-06 | 富士電機株式会社 | 半導体モジュールユニットおよび半導体モジュール |
-
2015
- 2015-05-11 JP JP2016529166A patent/JP6183556B2/ja active Active
- 2015-05-11 WO PCT/JP2015/063442 patent/WO2015198724A1/ja active Application Filing
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-
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007184315A (ja) * | 2006-01-04 | 2007-07-19 | Hitachi Ltd | 樹脂封止型パワー半導体モジュール |
JP2007294626A (ja) * | 2006-04-25 | 2007-11-08 | Hitachi Ltd | 半導体パワーモジュール |
US20120168919A1 (en) * | 2011-01-04 | 2012-07-05 | Eom Joo-Yang | Semiconductor package and method of fabricating the same |
US20120289137A1 (en) * | 2011-05-09 | 2012-11-15 | Robert Bruce Amesbury | Device for killing wounded fowl |
CN103765577A (zh) * | 2011-09-26 | 2014-04-30 | 日立汽车系统株式会社 | 功率模块 |
WO2013118478A1 (ja) * | 2012-02-09 | 2013-08-15 | 富士電機株式会社 | 半導体装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN115413401A (zh) * | 2020-04-24 | 2022-11-29 | 株式会社村田制作所 | 高频模块以及通信装置 |
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US20160322275A1 (en) | 2016-11-03 |
US9530713B2 (en) | 2016-12-27 |
CN106415827B (zh) | 2019-03-08 |
JP6183556B2 (ja) | 2017-08-23 |
JPWO2015198724A1 (ja) | 2017-04-20 |
WO2015198724A1 (ja) | 2015-12-30 |
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