CN106330629A

CN106330629A - Ethernet interface and data processing device and method thereof

Info

Publication number: CN106330629A
Application number: CN201510369062.4A
Authority: CN
Inventors: 韩学敬; 余晨; 安康; 王志忠
Original assignee: Shenzhen ZTE Microelectronics Technology Co Ltd
Current assignee: Shenzhen ZTE Microelectronics Technology Co Ltd
Priority date: 2015-06-29
Filing date: 2015-06-29
Publication date: 2017-01-11
Also published as: WO2017000417A1

Abstract

The embodiment of the invention discloses a data processing device of an ethernet interface. The data processing device comprises a selection module and an interface module. The selection module is used for selecting a bandwidth of an ethernet interface and the interface module is used for processing data that are sent or received by the ethernet interface based on the selected bandwidth, wherein resources inside the module are used in a time-sharing multiplexing mode when the data that are sent or received by the ethernet interface are processed based on different bandwidths. In addition, the embodiment of the invention also discloses an ethernet interface and a data processing method of the ethernet interface.

Description

A kind of Ethernet interface and data processing equipment, method

Technical field

The present invention relates to the Ethernet Interface Design technology, particularly relate to a kind of Ethernet interface and data process Device, method.

Background technology

Along with development and the deep application of ethernet technology, higher bandwidth, faster speed and service More diversification becomes the inexorable trend of its development.So, the router device interconnected for backbone network is carried Go out higher requirement.

Network processor chip is one of core of router device, in order to meet different application scene pair Ethernet interface type, interface quantity and the demand of process bandwidth, network processor chip provides abundant Ethernet interface and other ethernet devices or chip realize interconnection.Network processor chip can carry simultaneously For the Ethernet interface of various bandwidth grade, such as, network processor chip supports 1G, 10G, 40G simultaneously With 100G Ethernet interface.

At present, when consolidated network processor chips realize multiple Ethernet interface, each Ethernet interface Use corresponding resources of chip, then according to the quantity each used carries out repeatedly example；If according to so Mode remove to realize whole Ethernet interfaces of above-mentioned network processor chip, then, whole network processing unit The shared in the chips resource in the interface section of chip will be the most, and then increase chip cost.

Summary of the invention

For solving above-mentioned technical problem, embodiment of the present invention expectation provides at a kind of Ethernet interface and data thereof Reason device, method, can effectively reduce storage resource and calculation resources that Ethernet interface is used.

The technical scheme is that and be achieved in that:

Embodiments provide the data processing equipment of a kind of Ethernet interface, including selecting module and connecing Mouth die block, wherein,

Select module, for selecting the bandwidth of Ethernet interface；

Interface module, is used for based on selected bandwidth sending from Ethernet interface or the message data of reception Process, based on different bandwidth, the message data sending from Ethernet interface or receiving is being processed Time, with the resource of this inside modules described in the form multiplexing of timesharing.

In such scheme, described interface module includes at least with next height layer: media access control MAC Sublayer and physical code PCS sublayer；Wherein,

Media access control sublayer, processes, at base for the message data received self based on selected bandwidth When the described message data self received is processed by different bandwidth, with the form multiplexing self of timesharing Internal resource；

PCS sublayer, processes, at base for the message data received self based on selected bandwidth When the described message data self received is processed by different bandwidth, with the form multiplexing self of timesharing Internal resource.

In such scheme, described PCS sublayer includes cross clock domain converting unit, is used for realizing media access control sublayer Clock is changed to the cross clock domain of PCS sublayer clock；

Described PCS sublayer, is used for when processing, based on different bandwidth, the message data that self receives, With cross clock domain converting unit described in the form multiplexing of timesharing.

In such scheme, described selection module, for selecting Ethernet interface at multiple band alleviating distention in middle-JIAO to be selected Bandwidth, the plurality of bandwidth to be selected includes the first bandwidth and the second bandwidth, a width of first band of the second band Wide N times, N is the natural number more than 1.

In such scheme, described interface module includes at least with next height layer: media access control sublayer and PCS Layer；Wherein, described media access control sublayer has N number of first bandwidth input port and a second bandwidth input Mouthful；Described PCS sublayer has N number of first bandwidth input port and a second bandwidth input port；

N number of first bandwidth input port of described media access control sublayer is in selected a width of first bandwidth of band Time, according to the mode of polling dispatching to described media access control sublayer incoming message data, or to described media access control sublayer Parallel incoming message data；Described media access control sublayer is defeated to each first bandwidth input port based on the first bandwidth The message data entered processes；Described media access control sublayer is at the report inputting each the first bandwidth input port When literary composition data process, with the resource of the form multiplexing therein of timesharing；

Described PCS sublayer, for when selected a width of first bandwidth of band, from N number of first bandwidth input Port receives message data parallel, the message number received each first bandwidth input port based on the first bandwidth According to processing；When the message data receiving each the first bandwidth input port processes, with timesharing The resource of form multiplexing therein；

Described media access control sublayer, for when selected a width of second bandwidth of band, carries from one second Wide input port receives message data, the message number received the second bandwidth input port based on the second bandwidth According to processing；

Described PCS sublayer, for when selected a width of second bandwidth of band, from one the second bandwidth Input port receives message data, the message number received a second bandwidth input port based on the second bandwidth According to processing.

In such scheme, the resource within described interface module includes at least one resource following: calculation resources With storage resource.

The embodiment of the present invention also proposed a kind of Ethernet interface, including any one Ethernet interface above-mentioned Data processing equipment.

The embodiment of the present invention also proposed the data processing method of a kind of Ethernet interface, including:

Select the bandwidth of Ethernet interface；

Based on selected bandwidth, the message data sending from Ethernet interface or receiving is processed, at base When the message data sending from Ethernet interface or receiving is processed by different bandwidth, with the shape of timesharing Resource within Ethernet interface described in formula multiplexing.

In such scheme, described Ethernet interface includes at least with next height layer: media access control sublayer and PCS Sublayer；

The described message data based on selected bandwidth to sending from Ethernet interface carries out process and includes: institute State the message data that self receives by media access control sublayer based on selected bandwidth to process；And/or, described The message data that self is received by PCS sublayer based on selected bandwidth processes；

Described media access control sublayer or PCS sublayer based on different bandwidth to the described message data self received When processing, with the resource of the form multiplexing therein of timesharing.

Described PCS sublayer based on different bandwidth to described self receive message data process time, With cross clock domain converting unit described in the form multiplexing of timesharing.

A kind of Ethernet interface of embodiment of the present invention offer and data processing equipment, method, at Ethernet When interface sends or receives message data, the storage resource of timesharing therein and calculation resources, it is thus possible to have Effect reduces the cost of network processor chip.

Accompanying drawing explanation

Fig. 1 is the composition structural representation of the data processing equipment of first embodiment of the invention Ethernet interface；

Fig. 2 is the composition structural representation of embodiment of the present invention 10G-XFI Ethernet interface sending side；

Fig. 3 is the composition structural representation of embodiment of the present invention 40G Ethernet interface sending side；

Fig. 4 is the composition of the media access control sublayer of the data sending device of second embodiment of the invention Ethernet interface Structural representation；

Fig. 5 be the Ethernet interface of second embodiment of the invention data sending device in CRC32 computing unit Principle schematic；

Fig. 6 is the composition knot of the PCS sublayer of the data sending device of second embodiment of the invention Ethernet interface Structure schematic diagram；

Fig. 7 is that the asynchronous FIFO unit of the data sending device of second embodiment of the invention Ethernet interface enters Time diagram after the adjustment of row sequential；

Fig. 8 is the composition structural representation that embodiment of the present invention 10G-XFI Ethernet interface receives side；

Fig. 9 is the composition structural representation that embodiment of the present invention 40G Ethernet interface receives side；

Figure 10 is the composition of the PCS sublayer of the data sink of third embodiment of the invention Ethernet interface Structural representation；

Figure 11 is the composition of the media access control sublayer of the data sink of third embodiment of the invention Ethernet interface Structural representation；

Figure 12 is the flow chart of the data processing method of fifth embodiment of the invention Ethernet interface.

Detailed description of the invention

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly Chu, it is fully described by.

First embodiment

Fig. 1 is the composition structural representation of the data sending device of first embodiment of the invention Ethernet interface, As it is shown in figure 1, this device includes: selection module 100 and interface module 101, wherein,

Select module 100, for selecting the bandwidth of Ethernet interface.

Here, select module 100 to select the bandwidth of an Ethernet interface, the bandwidth of Ethernet interface every time Can be 10G or 40G.

Interface module 101 includes at least with next height layer: medium education (Media Access Control, MAC) sublayer 102 and physical code (physical coding sublayer, PCS) sublayer 103.

Here, when Ethernet interface sends message data, the outfan of media access control sublayer 102 is situated between by physics Matter independent interfaces connects PCS sublayer 103.When Ethernet interface receives message data, media access control sublayer 102 Input by physical medium independent interfaces connect PCS sublayer 103.

When Ethernet interface sends message data, the input of PCS sublayer 103 is unrelated by physical medium Interface connects media access control sublayer 102.The output of PCS sublayer 103 when Ethernet interface receives message data Hold and connect media access control sublayer 102 by physical medium independent interfaces.

If media access control sublayer 102 and PCS sublayer 103 is the ingredient of interface module 101, MAC Interconnection is realized by physical medium independent interfaces between sublayer 102 and PCS sublayer 103.

When the ingredient that media access control sublayer 102 is interface module 101, interface module 101 is based on selected The message data that described interface module is received by the bandwidth selected processes, and illustrates the most in two kinds of situation. The first situation, when Ethernet interface needs to send data, interface module 101 is based on selected bandwidth The process processing the message data self received includes: media access control sublayer 102 is based on selected bandwidth The message data receiving self processes, and the message data after processing sends to PCS sublayer.Second Kind of situation, when Ethernet interface needs to receive data, interface module 101 based on selected bandwidth to from The message data process that carries out processing that body receives includes: media access control sublayer 102 based on selected bandwidth to from The message data from PCS sublayer that body receives processes.Here, at the message data of media access control sublayer Reason process meets the function of IEEE802 standard definition, such as, during a width of 10G of selected band, MAC The message data processing procedure of sublayer meets IEEE802.3ae standard；During the selected a width of 40G of band, MAC The message data processing procedure of sublayer meets IEEE802.3ab standard.

When the ingredient that PCS sublayer 103 is interface module 101, interface module 101 is based on selected Bandwidth message data that self is received process, illustrate the most in two kinds of situation.The first feelings Condition, when Ethernet interface needs to send data, self is connect by interface module 101 based on selected bandwidth The process that the message data received carries out processing includes: self is connect by PCS sublayer 103 based on selected bandwidth The message data from media access control sublayer received processes.The second situation, when Ethernet interface needs to connect When receiving data, the message data that self receives is processed by interface module 101 based on selected bandwidth Process includes: the message data that self is received by PCS sublayer 103 based on selected bandwidth processes, Message data after processing sends to media access control sublayer.Here, the message data processing procedure of PCS sublayer Meet the function of IEEE802 standard definition, such as, during a width of 10G of selected band, the report of PCS sublayer Literary composition data handling procedure meets IEEE802.3ae standard；During the selected a width of 40G of band, PCS sublayer Message data processing procedure meets IEEE802.3ab standard.

Here, interface module 101, for obtaining selected bandwidth, based on selected bandwidth to described The message data that interface module receives processes, at the message data received self based on different bandwidth When processing, with the resource of therein described in the form multiplexing of timesharing.

Here, the resource within interface module 101 includes at least one resource following: calculation resources and storage Resource, calculation resources here can be logical operations resource, and storage resource can be random access memory (Random-Access Memory, RAM) resource.It can be seen that when interface module is based on different bands When width carries out data process, the internal identical resource of interface module can be used in the different time, it is clear that meeting Reduce resource consumption during Ethernet interface transmission message data.Such as, interface module is carrying out 10G bandwidth When the data of grade process the data process with 40G bandwidth class, owing to the time processed is different, can make By the identical RAM resource of interface module.

Further, media access control sublayer 102 for based on different bandwidth to the described message number self received According to when processing, with the resource within the form multiplexing media access control sublayer of timesharing.Here, in media access control sublayer The resource in portion includes at least one resource following: calculation resources and storage resource, calculation resources here is permissible Being logical operations resource, storage resource can be RAM resource.

Further, PCS sublayer 103, for based on different bandwidth to described self receive message When data process, with the resource of the form multiplexing PCS sublayer internal of timesharing.Here, in PCS sublayer The resource in portion includes at least one resource following: calculation resources and storage resource, calculation resources here is permissible Being logical operations resource, storage resource can be RAM resource.

Further, PCS sublayer 103 includes cross clock domain converting unit 104, is used for realizing media access control sublayer Clock is changed to the cross clock domain of PCS sublayer clock.PCS sublayer 103, for based on different bandwidth When the message data receiving described PCS sublayer processes, with cross clock domain described in the form multiplexing of timesharing Converting unit.Here, cross clock domain converting unit 104 can use asynchronous First Input First Output (First Input First Output, FIFO) realize.

In the first embodiment of the invention, described selection module 100 selects the bandwidth of Ethernet interface to include: Selecting module 100 to select the bandwidth of Ethernet interface at multiple band alleviating distention in middle-JIAO to be selected, the plurality of waiting selects Bandwidth include the first bandwidth and the second bandwidth, the second with a width of first bandwidth N times, N is more than 1 Natural number.Here, the first bandwidth can be 10G, and the second bandwidth is 40G, and second carries a width of first bandwidth 4 times.

Illustrate the most in two kinds of situation.

The first situation: Ethernet interface sends data.

Media access control sublayer 102 has N number of first bandwidth input port and a second bandwidth input port, and There is N number of first bandwidth output port and a second bandwidth output port；Described PCS sublayer has N Individual first bandwidth input port and a second bandwidth input port, and there is N number of first bandwidth output port With a second bandwidth output port.Here, the output port of media access control sublayer 102 is to send out to PCS sublayer Sending the port of message data, the input port of PCS sublayer 103 receives message data from media access control sublayer Port.

N number of first bandwidth input port of described media access control sublayer is in selected a width of first bandwidth of band Time, according to the mode of polling dispatching (RR poll) to described media access control sublayer incoming message data；Described Media access control sublayer 102 based on the first bandwidth to each first bandwidth input port input message data at Reason, the message data after processing is sent by the N number of first bandwidth output port of self.Described Media access control sublayer 102 is when the message data receiving each the first bandwidth input port processes, with timesharing The resource within form multiplexing media access control sublayer.Here, N number of first bandwidth input port of media access control sublayer According to polling dispatching (RR poll) mode to described media access control sublayer incoming message data time, every time from The data bit width of the message data of each first bandwidth input port input is equal, such as, be 256bit.Need It is noted that if media access control sublayer 102 does not receives report in any one first bandwidth input port Literary composition data, then need also exist for receiving the time of message data into the first corresponding bandwidth input port distribution；Example As, 4 the first bandwidth input ports of media access control sublayer are respectively labeled as port 0, port 1, port 2 and Port 3；In the cycle of each polling dispatching, according to port 0, port 1, port 2 and the order of port 3 If there is no message number to media access control sublayer incoming message data arbitrary first bandwidth input port such as port 0 According to input, then need also exist for distributing to port 0 and receive the time of message data accordingly.

Described PCS sublayer 103, for when selected a width of first bandwidth of band, from N number of first bandwidth Input port receives message data parallel, the report received each first bandwidth input port based on the first bandwidth Literary composition data process, and the message data after processing is sent by self output port.Institute State PCS sublayer 103, be used for when the message data receiving each the first bandwidth input port processes, Resource with the form multiplexing PCS sublayer internal of timesharing.

Described media access control sublayer or PCS sublayer, for when selected a width of second bandwidth of band, from described One the second bandwidth input port receives message data, based on the second bandwidth, the second bandwidth input port is connect The message data received processes, the second bandwidth outfan by self of the message data after processing Mouth sends.

The second situation: Ethernet interface receives data.

Further, PCS sublayer 103 includes N number of first bandwidth input port and a second bandwidth input Port, and there is N number of first bandwidth output port and a second bandwidth output port；Described MAC Layer 102 has N number of first bandwidth input port and a second bandwidth input port, and has N number of first Bandwidth output port and a second bandwidth output port.Here, the output port of PCS sublayer 103 be to Media access control sublayer sends the port of message data, and the input port of media access control sublayer 102 is to receive from PCS sublayer The port of message data.

Described PCS sublayer 103, for when selected a width of first bandwidth of band, from N number of first bandwidth Input port receives message data parallel, the report received each first bandwidth input port based on the first bandwidth Literary composition data process, and the message data after processing is sent by the N number of first bandwidth output port of self Go out.Described PCS sublayer 103, for entering at the message data receiving each the first bandwidth input port When row processes, with the resource of the form multiplexing PCS sublayer internal of timesharing.

N number of first bandwidth input port of described media access control sublayer is for the parallel N group message data that receives, tool Saying, N number of first bandwidth input port of described media access control sublayer is for receiving from PCS sublayer parallel body The message data of N number of first bandwidth output port output of 103.Described media access control sublayer 102 is based on first The message data that each first bandwidth input port is received by bandwidth processes, the message data after processing Sent by the N number of first bandwidth output port of self.Described media access control sublayer 102, for right When the message data that each the first bandwidth input port receives processes, with in the form multiplexing self of timesharing The resource in portion.

Here, when N number of first bandwidth input port of media access control sublayer receives N group message data parallel, connect The data bit width often organizing message data received is equal, such as, be 64bit.If it should be noted that MAC Sublayer 102 does not receives message data in any one first bandwidth input port, then need also exist for as right The the first bandwidth input port distribution answered receives the time of message data；Such as, 4 first of media access control sublayer Bandwidth input port is respectively labeled as port 0, port 1, port 2 and port 3；At each polling dispatching Cycle, according to the order of port 0, port 1, port 2 and port 3 to media access control sublayer incoming message data If arbitrary first bandwidth input port such as port 0 does not has message data to input, then need also exist for distributing to Port 0 receives the time of message data accordingly.

Further, each first bandwidth input port is received based on the first bandwidth when media access control sublayer 102 Message data when processing, media access control sublayer 102 uses one group of report that 4 FIFO storages are corresponding respectively Literary composition data；4 FIFO are according to the mode of polling dispatching outside outgoing message data.

Described media access control sublayer 102 or PCS sublayer 103, is used for when selected a width of second bandwidth of band, Message data is received from one the second bandwidth input port, defeated to second bandwidth based on the second bandwidth The message data that inbound port receives processes, one second band by self of the message data after processing Wide output port sends.

In actual applications, described selection module 100 can be by the central processing unit being positioned in network processing unit (Central Processing Unit, CPU), microprocessor (Micro Processor Unit, MPU), number Word signal processor (Digital Signal Processor, DSP) or field programmable gate array (Field Programmable Gate Array, FPGA) etc. realize.

In first embodiment of the invention, interface module and selection module are the Ethernet of network processor chip The ingredient of interface, so, when interface module carries out data process, the resource of multiplexing therein, Thus reduce being manufactured into of the resource that used and network processor chip when Ethernet interface sends message data This.

Second embodiment

In order to enable more to embody the purpose of the present invention, on the basis of first embodiment of the invention, carry out into one The illustration of step.In second embodiment of the invention, Ethernet interface needs to send data, and two to be selected A width of 10G and 40G of band selected, wherein the first bandwidth is 10G, and the second bandwidth is 40G.10G Ethernet Sending side and the 40G Ethernet interface sending side of interface all can be implemented separately, and explanation is the most real separately below Show the technical scheme of 10G-XFI Ethernet interface sending side and 40G Ethernet interface sending side is implemented separately Technical scheme.

Fig. 2 is the composition structural representation of embodiment of the present invention 10G-XFI Ethernet interface sending side, such as figure Shown in 2, this 10G-XFI Ethernet interface sending side includes media access control sublayer 201 and PCS sublayer 202； Media access control sublayer 201 connects PCS sublayer 202 by XGMII interface.

Specifically, media access control sublayer 201 includes that the first cross clock domain cell fifo 203, first inputs control Unit 204 and the first message send processing unit 205；Wherein, the first cross clock domain cell fifo 203 is used Change in realizing the media access control sublayer clock clock frequency to PCS sublayer clock, such as, media access control sublayer clock Frequency is at least 270MHz, and the clock frequency of PCS sublayer clock is 257.8125MHz, this first across Clock frequency is converted to 257.8125MHz by clock zone cell fifo 203.Here, the first cross clock domain Cell fifo 203 can use asynchronous FIFO to realize, it can be seen that through the first cross clock domain FIFO After the clock frequency conversion of unit, 10G-XFI Ethernet interface sending side is all operated under PCS clock zone.

First input control unit 204, for sending stream control message and work message, here, work successively Message refers to the message for carrying user's valid data.Specifically, stream is produced according to the flow control signal received Control message, and have precedence over the output of work message to the first message transmission processing unit 205.Stream control message and work Sharing same data channel as message, therefore, while sending stream control message, the first input controls single The message data of input is cached by unit 204.When stream control message is sent, then from caching, read work Make message, work message is sent to the first message transmission processing unit 205.

First message sends processing unit 205, for carrying out following process for the message received: short Bao Tian Add patch (PAD), message source address field is replaced, mis-marked (err) is blocked and misplayed to message overlength；Will Message after process is sent out.Here, when adding patch for short bag, it is ensured that Ethernet data bag Data bit width reaches 64 bytes.

Media access control sublayer 201 also include CRC32 computing unit 206, a first frame encapsulation unit 207, One frame gap (inter-packet gap, IPG) computing unit 208 and the first frame transmitting element 209.First Message sends the processing unit 205 message after processing and is respectively sent to a CRC32 computing unit 206, the first frame encapsulation unit 207 and IPG computing unit 208.

Oneth CRC32 computing unit 206, for calculating the CRC32 school of each complete message received Test value, and this CRC32 check value is sent to the first frame encapsulation unit 207.

Oneth IPG computing unit 208, for according to the message received, calculating each two to be sent The adjacent frame gap between ethernet frame, frame gap represents byte quantity that needs insert such as, frame gap Meansigma methods be 12.The value of each frame gap calculated is sent to first by the oneth IPG computing unit 208 Frame encapsulation unit 207.

First frame encapsulation unit 207, for according to the value of each frame gap received and each message CRC32 check value, is packaged into the ethernet frame of correspondence by each message received.

First frame transmitting element 209, for form that each ethernet frame is allowed according to XGMII interface to Outgoing delivers to PCS sublayer 202, it is achieved ethernet frame is to the format mapping of XGMII interface.The most each with Too net frame is 64 Bit datas according to the message data that the form that XGMII interface allows is sent out.

Specifically, PCS sublayer 202 includes first coding unit the 210, first scrambling unit 211 and first Converting unit 212.

The data of 64 bits received, for being encoded by 64b/66b, are compiled by the first coding unit 210 Code is 66 Bit datas.

First scrambling unit 211, the data after encoding 64b/66b make the scrambling of 10G bandwidth class Operation.

First converting unit 212, for the message data after Scrambling Operation is carried out data width conversion, will It is converted into 40 Bit datas and outwards exports, to meet the requirement to receiving data of the PMA sublayer.First turn Changing in unit 212 and comprise synchronization fifo, this synchronization fifo is for carrying out sequential tune to the message data received Whole.

Fig. 3 is the composition structural representation of embodiment of the present invention 40G Ethernet interface sending side, such as Fig. 3 institute Showing, this 40G Ethernet interface sending side includes media access control sublayer 301 and PCS sublayer 302；Media access control sublayer 301 connect PCS sublayer 302 by XLGMII interface.

Specifically, media access control sublayer 301 includes that the second cross clock domain cell fifo 303, second inputs control Unit the 304, second message sends processing unit the 305, the 2nd CRC32 computing unit the 306, second frame envelope Dress unit the 307, the 2nd IPG computing unit 308 and the second frame transmitting element 309.

The media access control sublayer 301 and 10G-XFI Ethernet interface sending side of 40G Ethernet interface sending side The implementation of media access control sublayer 201 is essentially identical, the media access control sublayer 301 of 40G Ethernet interface sending side The corresponding composition portion of each component units and the media access control sublayer 201 of 10G-XFI Ethernet interface sending side Point implementation essentially identical, distinctive points is, the second cross clock domain cell fifo 303 and first across The implementation of clock zone cell fifo 203 is different, and the second frame transmitting element 309 and the first frame send single The implementation of unit 209 is different.

Specifically, the second cross clock domain cell fifo 303, for changing the clock frequency of media access control sublayer PCS sublayer clock frequency for any one LANE.

Further, the second frame transmitting element 309 is for permitting each ethernet frame according to XLGMII interface The form permitted is sent out to PCS sublayer 302, it is achieved ethernet frame is to the format mapping of XLGMII interface. At this moment, message data is sent out by the second frame transmitting element 309 by 4 parallel data channel (LANE) Deliver to PCS sublayer 302, the form that each ethernet frame allows according to XLGMII interface is being sent out Time, the data bit width of the message data that every LANE sends is 64 bits.

Specifically, PCS sublayer 302 includes the second coding unit the 310, the 3rd coding unit the 311, the 4th volume Code unit the 312, the 5th coding unit the 313, second scrambling unit 314, first inserts unit 315, second Insert unit 316, the 3rd insert unit 317, the 4th insert unit the 318, second converting unit 319, the Three converting unit the 320, the 4th converting unit 321 and the 5th converting units 322.Wherein, the second coding unit The implementation of 310 to the 5th coding units 313 is all identical with the implementation of the first coding unit 210, I will not elaborate.

Second scrambling unit receives what the second coding unit 310 to the 5th coding unit 313 sent for parallel Message data, for carrying out the Scrambling Operation of 40G bandwidth class, after scrambling to the message data received Every part of message data sends to corresponding insertion unit.

Each insertion unit for receive message data at LANE reserved location on insert with Mark code corresponding for this LANE.Arrange the implementation method of reserved location at every LANE to may is that and work as When message data is sent to PCS sublayer 302 by the second frame transmitting element 309 by 4 parallel LANE, Every LANE reserves the position inserting mark code, when Ethernet interface receives data, mark The LANE sequence that code may be used for realizing on 4 LANE of PCS sublayer adjusts and on 4 LANE Message data aligns；Message data after each insertion unit will insert mark code sends to corresponding conversion list Unit.

Being provided with asynchronous FIFO in each converting unit, asynchronous FIFO completes the second cross clock domain cell fifo The PCS sublayer clock frequency of the LANE produced in 303 turning to each bar LANE PCS sublayer clock frequency Change, after completing clock frequency conversion, the message data of reception is carried out sequential adjustment；Corresponding converting unit Message data after sequential being adjusted carries out data width conversion, converts thereof into 40 Bit datas the most defeated Go out.

The data of the Ethernet interface of second embodiment of the invention send transposition can support two kinds of mode of operations, The first is 10G-XFI Ethernet interface pattern, and the second is 40G Ethernet interface pattern, Qi Zhong 4 ports can be could support up under 10G-XFI Ethernet interface pattern and send message data, at 40G ether Under network interface pattern, support that 1 port sends message data.The Ethernet interface of second embodiment of the invention Message data send at least following sublayer of transposition: media access control sublayer and PCS sublayer.Work as media access control sublayer Message data with the Ethernet interface that PCS sublayer is all second embodiment of the invention sends the composition portion of transposition Timesharing, under 10G-XFI Ethernet interface pattern, media access control sublayer connects PCS by XGMII interface Layer；Under 40G Ethernet interface pattern, media access control sublayer connects PCS sublayer by XLGMII interface.

Fig. 4 is the composition of the media access control sublayer of the data sending device of second embodiment of the invention Ethernet interface Structural representation, as shown in Figure 4, this media access control sublayer includes: the 3rd input control unit the 401, the 3rd report Literary composition sends processing unit the 402, the 3rd CRC32 computing unit the 403, the 3rd frame encapsulation unit the 404, the 3rd IPG computing unit 405 and the 3rd frame transmitting element 406.

Specifically, the 3rd input control unit 401, for receiving message data according to the bandwidth being pre-selected. Here, a width of 10G or 40G of band being pre-selected.3rd input control unit 401 has 4 10G bands Wide input port and the input port of 1 40G bandwidth.

As the described a width of 10G of the band being pre-selected, 4 10G bandwidth of the 3rd input control unit 401 Input port according to the mode of polling dispatching (RR poll) to described media access control sublayer incoming message data, The data bit width of the message data of the input port input of each 10G bandwidth is consistent.Specifically, the 3rd is defeated Enter the input port of 4 10G bandwidth of control unit 401 according to the mode of polling dispatching to described MAC Sublayer incoming message data include: the most repeatedly receive from the input port of 4 10G bandwidth Message data, when circulation receives message data every time, carries out message data according to the input port order set Receive；For instance, it is possible to the input port receiving the 10G bandwidth of message data is respectively port 0, port 1, port 2 and port 3, the input port order of setting is port 0, port 2, port 1 and port 3, When then circulation receives message data every time, receive identical from port 0, port 2, port 1 and port 3 successively The message data of data bit width.Here, if the input port of 4 10G bandwidth all can receive message number According to, then total bit wide of the message data received is 256bit.

It should be noted that the input port of any one 10G bandwidth of the 3rd input control unit 401 connects Can not receive message data, then need also exist for receiving into corresponding input port distribution the time of message data.Example As, 4 10G bandwidth input ports are respectively labeled as port 0, port 1, port 2 and port 3；Often The cycle of individual polling dispatching, according to the order of port 0, port 1, port 2 and port 3 to media access control sublayer If incoming message data arbitrary first bandwidth input port such as port 0 does not has message data to input, then same Sample needs to distribute to port 0 and receives the time of message data accordingly.

As a width of 40G of the band being pre-selected, the 3rd input control unit 401 is from fixing 40G bandwidth Input port receives message data, and the bit wide of the message data received is 256bit.It should be noted that If the input port of this 40G bandwidth is an input port in the input port of 4 10G bandwidth, then The process that 3rd input control unit 401 receives message data from the input port of fixing 40G bandwidth is permissible Regard as be pre-selected with a kind of special circumstances during a width of 10G, now continuous this 40G bandwidth of poll Input port.

Further, as a width of 10G of the band being pre-selected, in the 3rd input control unit 401, can To use 4 RAM to cache the work message of input when sending stream control message, each RAM caches The work message of one input port input.As a width of 40G of the band being pre-selected, by these above-mentioned 4 RAM is spliced into a RAM, the work message that input port is inputted by the RAM generated after using splicing Cache.It can be seen that no matter be pre-selected bandwidth time 10G or 40G, the 3rd input control In unit 401, as long as using 4 RAM just can complete the caching of work message, reduce RAM money The consumption in source.

Here, during a width of 10G of band being pre-selected, media access control sublayer is for each 10G bandwidth input port The message data of input carries out time-division processing, and during time-division processing, the 3rd message sends processing unit 402, the 3rd CRC32 computing unit the 403, the 3rd frame encapsulation unit the 404, the 3rd IPG computing unit 405 With the 3rd frame transmitting element 406 all by the form multiplexing with timesharing.

Here, the 3rd message sends processing unit 402 and the realization side of the first message transmission processing unit 205 Formula is identical, the 3rd CRC32 computing unit 403 and the implementation phase of a CRC32 computing unit 206 With, the 3rd frame encapsulation unit 404 is identical with the implementation of the first frame encapsulation unit 207；When being pre-selected Band a width of 10G time, the 3rd IPG computing unit 405 and the implementation of an IPG computing unit 208 Identical, as a width of 40G of the band being pre-selected, the 3rd IPG computing unit 405 and the 2nd IPG calculates single The implementation of unit 308 is identical；The most all it is not repeated to describe.

Below as a example by the 3rd CRC32 computing unit 403, the principle of time-sharing multiplex is described.

Fig. 5 be the Ethernet interface of second embodiment of the invention data sending device in CRC32 computing unit Principle schematic, as it is shown in figure 5, as a width of 10G of the band being pre-selected, the 3rd CRC32 calculates Unit 403 can receive multiple message, and some messages are the packet header of packet, and some messages are packet Bag tail.In Fig. 5, data_in represents that sop_in represents the bag that current message is packet when the message of input Head, eop_in represents the bag tail that current message is packet, and vld_in represents that current message is effective, mty_in Representing the invalidation word joint number of bag tail (eop_in) burst, port_in represents the 10G bandwidth corresponding to data_in The port numbers of input port.

As a width of 10G of the band being pre-selected, it is single that the message fragment being currently entered calculates son through CRC32 Unit can obtain a value of calculation crc_val, according to 10G bandwidth input port corresponding for crc_val after calculating Port numbers port_dly (port_dly be port_in play bat, align with crc_val), result of calculation is temporary It is stored in the depositor of corresponding ports, i.e. according to the port numbers of 10G bandwidth input port corresponding for crc_val, In four depositor port0 to port3, select the depositor that corresponding depositor is deposited as result of calculation, The result of calculation that depositor is deposited uses the when of needing to wait and input corresponding ports data next time.init_val Representing the CRC32 result of calculation of last corresponding ports incoming message, init_val is the binary system of 32 bits Data, if the message now inputted is packet header (sop_in), then init_val value is complete 1, otherwise, root From corresponding depositor, result of calculation is read according to port_in.

As a width of 40G of the band being pre-selected, it is contemplated that message can input continuously, then be currently entered divides The result of calculation of sheet can be loaded directly on init_val, and no longer stores in depositor.No matter which kind of works Pattern, when the bag tail that incoming message is packet, calculated crc_val is to be exported complete The CRC32 check value of whole message.

So, during the data of the Ethernet interface of second embodiment of the invention send transposition, it is only necessary to one CRC32 calculates logic, adds simple peripheral control logic, can be achieved with the message CRC32 of 4 ports The calculating of check value, saves logical operations resource.

3rd frame transmitting element 406, for when a width of 10G of the band being pre-selected, by each ethernet frame The form allowed according to XGMII interface is sent out to PCS sublayer 202, it is achieved ethernet frame is to XGMII The format mapping of interface；When a width of 40G of the band being pre-selected, by each ethernet frame according to XLGMII The form that interface allows is sent out to PCS sublayer 202, it is achieved ethernet frame is to the lattice of XLGMII interface Formula maps.Here, the 3rd frame transmitting element 406 has 4 XGMII interfaces and 1 XLGMII connects Mouthful, wherein, XLGMII interface includes 4 parallel LANE.

3rd frame transmitting element 406 use 16 RAM realize ethernet frame to XGMII interface or XLGMII interface mappings.As a width of 10G of the band being pre-selected, for each XGMII interface, use 4 RAM carry out the ethernet frame format mapping to XGMII interface；As a width of 40G of the band being pre-selected Time, for this XLGMII interface, use above-mentioned 16 RAM to realize ethernet frame to XLGMII interface Format mapping.It can be seen that by the RAM multiplexing between different mode, save RAM resource.

Here, the 3rd frame transmitting element 406 is when the second frame transmitting element 309 is by 4 articles of parallel LANE When sending message data to PCS sublayer, every LANE reserves the position inserting mark code, When Ethernet interface receives data, mark code may be used for realizing on 4 LANE of PCS sublayer LANE sequence adjusts and the message data alignment on 4 LANE.

It should be noted that MAC of the data sending device of second embodiment of the invention Ethernet interface Layer can realize the basic function of the media access control sublayer sending side of defined in IEEE802.3 standard.The present invention The media access control sublayer of the data sending device of the second embodiment Ethernet interface all counts under MAC clock zone According to process, do not make cross clock domain conversion.

Fig. 6 is the composition knot of the PCS sublayer of the data sending device of second embodiment of the invention Ethernet interface Structure schematic diagram, as shown in Figure 6, this PCS sublayer includes that the first data selection unit the 601, the 6th coding is single Unit the 602, the 7th coding unit the 306, the 8th coding unit the 604, the 9th coding unit the 605, the 3rd scrambling Unit the 606, the 4th scrambling unit the 607, the 5th scrambling unit the 608, the 6th scrambling unit the 609, the 7th adds Disturb unit the 610, the 5th and insert unit the 611, the 6th insertion unit the 612, the 7th insertion unit the 613, the 8th Insert unit the 614, second data selection unit the 615, first asynchronous FIFO unit the 616, second asynchronous FIFO Unit the 617, the 3rd asynchronous FIFO unit the 618, the 4th asynchronous FIFO unit the 619, the 6th converting unit 620, the 7th converting unit the 621, the 8th converting unit 622 and the 9th converting unit 623.

Specifically, the first data selection unit 601, for receiving message data based on selected bandwidth； As a width of 40G of the band being pre-selected, receive the message data of 4 LANE of XLGMII interface, will The message data of every LANE of the XLGMII interface received sends to corresponding coding unit；When in advance During a width of 10G of band selected, receive the message data of XGMII interface, by the message number of XGMII interface According to sending to corresponding coding unit.

Here, each coding unit will be for encoding by 64b/66b, by the message number of 64 bits of reception According to being encoded to 66 bit message data；According to the bandwidth being pre-selected, the 66 bit message data generated are entered Row sends, and as a width of 10G of the band being pre-selected, sends the 66 bit message data generated to the 4th Scrambling unit the 607, the 5th scrambling unit the 608, the 6th scrambling unit 609 or the 7th scrambling unit 610.When During a width of 40G of band being pre-selected, the 66 bit message data generated are sent to the 3rd scrambling unit 606.

As a width of 10G of the band being pre-selected, the 4th scrambling unit 607, the 5th scrambling unit 608, The message data of reception is carried out adding of 10G bandwidth class by six scrambling units 609 or the 7th scrambling unit 610 Disturbing process, the message data after scrambling being processed sends to the second data selection unit 615.When being pre-selected Band a width of 40G time, the message data of the 3rd scrambling unit 606 4 articles of LANE for receiving is carried out The Scrambling Operation of 40G bandwidth class, is respectively sent to the message data of 4 LANE after Scrambling Operation 5th inserts unit 611 inserts unit 614 to the 8th.

Here, each insertion unit inserts on the reserved location of the LANE at the message data received The mark code corresponding with this LANE, will insert the message data after mark code and send to the second data selection Unit 615.

Second data selection unit 615, for according to the bandwidth being pre-selected, selects from four scrambling units 607 Receive message data to the 7th scrambling unit 610, or inserting unit 611 from the 5th inserts unit to the 8th 614 receive message data.If a width of 10G of the band being pre-selected, the second data selection unit 615 is from Four scrambling units 607 receive message data to the 7th scrambling unit 610；If the band being pre-selected is a width of 40G, the second data selection unit 615 is inserted unit 611 from the 5th and is inserted unit 614 reception report to the 8th Literary composition data；The message data received is sent to corresponding asynchronous FIFO list by the second data selection unit 615 Unit.

Here, each asynchronous FIFO unit be used for media access control sublayer clock to PCS sublayer clock time Clock frequency rate is changed, and adjusts in sequential under the control controlling logic, the message data of reception is carried out sequential adjustment, Message data after sequential adjusts is sent to corresponding converting unit by each asynchronous FIFO unit, each The effect that asynchronous FIFO unit carries out sequential adjustment to the message data received is to ensure that converting unit is reported Bit is not lost during literary composition data width conversion.Fig. 7 is the message of second embodiment of the invention Ethernet interface The asynchronous FIFO unit of data sending device carries out the time diagram after sequential adjustment, as it is shown in fig. 7, Cnt represents the PCS clock cycle, and vld represents the sequential chart after sequential adjusts, from figure 7 it can be seen that asynchronous After cell fifo carries out sequential adjustment, within 33 PCS clock cycle, export 20 message datas.

It can be seen that the data sending device of the Ethernet interface for second embodiment of the invention, no matter in advance The bandwidth first selected is 10G or 40G, from media access control sublayer clock to the clock frequency of PCS sublayer clock Conversion all realizes in corresponding asynchronous FIFO unit, before asynchronous FIFO unit carries out clock frequency conversion, The message data dispensing device of the Ethernet interface of second embodiment of the invention is all operated under MAC clock zone, Compared with prior art, save FIFO resource, and make the easier of cross clock domain operation change.This In, FIFO resource refers mainly to RAM resource.

The data sending device of the Ethernet interface of second embodiment of the invention, it is possible to achieve IEEE802.3 marks The basic function of the PCS sublayer sending side of defined in standard；As a width of 40G of the band being pre-selected, permissible Exporting 4 Lane, every Lane speed is 10.3125Gbps, and bit wide is 40bit.

3rd embodiment

In order to enable more to embody the purpose of the present invention, on the basis of first embodiment of the invention, carry out into one The illustration of step.In third embodiment of the invention, Ethernet interface needs to receive data, and two to be selected A width of 10G and 40G of band selected, wherein the first bandwidth is 10G, and the second bandwidth is 40G.10G Ethernet The reception side of interface and 40G Ethernet interface receive side and all can be implemented separately, and explanation is the most real separately below Existing 10G-XFI Ethernet interface receives the technical scheme of side and 40G Ethernet interface reception side is implemented separately Technical scheme.

Fig. 8 is the composition structural representation that embodiment of the present invention 10G-XFI Ethernet interface receives side, such as figure Shown in 8, this 10G-XFI Ethernet interface receives side and includes media access control sublayer 801 and PCS sublayer 802； Media access control sublayer 801 connects PCS sublayer 802 by XGMII interface.

Specifically, PCS sublayer 802 includes the tenth converting unit the 803, first Descrambling unit 804 and first Decoding unit 805；Wherein, the tenth converting unit 803 is provided with synchronization subelement, the tenth converting unit 803 are used for carrying out data width conversion, and the 40 bit message data received are transformed into 66 bit message numbers According to, and carry out shifting adjustment to message data according to the displacement adjustment signal synchronizing subelement feedback.Same step The synchronous head of the 66 bit message data that unit is inputted by detection, carries out the synchronizing process of message data, and In the case of message data does not synchronize, feedback shift adjusts signal, it can be seen that the tenth converting unit 803 synchronizing processes that can complete the message data received.

First Descrambling unit 804, for making 10G bandwidth class to the message data of the tenth converting unit output Descrambling operation.

First decoding unit 805, for being decoded by 66b/64b, the 66 bit message data solutions that will receive Code is 64 bit message data.The message data that first decoding unit 805 decoding generates is ethernet frame.

Specifically, media access control sublayer 801 includes that the first message recovery unit the 806, the oneth CRC32 verification is single Unit's the 807, first message receives processing unit 808, first-class control packet processing unit 809 and the 3rd across clock Territory cell fifo 810.

First message recovery unit 806, by XGMII interface from the report of the first decoding unit 805 Literary composition data, are descapsulated into Ethernet message by the ethernet frame of reception.

Oneth CRC32 verification unit 807, for receiving Ethernet message from the first message recovery unit 806, Verifying the CRC32 field of each message received, the meeting that verification makes mistakes is beaten in message EOP position Upper ERR labelling；Message checking result is sent to the first message reception process by the oneth CRC32 verification unit Unit 808.

First message receives processing unit 808, for message being carried out phase according to the check results of each message Should process, here, the process of message includes: destination address field (DAF) inspection, overlength are blocked, the inspection of T/L field Look into, remove patch, stream control message identification and termination.If the first message receives what processing unit 808 processed Be stream control message, then the stream control message after processing sends to first-class control packet processing unit 809；First Stream control message process unit 809, convection current control message does parsing further, generates flow control signal, by stream control letter Number output to the 3rd cross clock domain cell fifo 810.If the first message receives what processing unit 808 processed It is work message, then work message and corresponding flow control signal is sent to the 3rd cross clock domain cell fifo 810。

3rd cross clock domain cell fifo 810, for realizing PCS sublayer clock to media access control sublayer clock Clock frequency is changed, and such as, media access control sublayer clock frequency is at least 270MHz, and PCS sublayer clock Clock frequency be 257.8125MHz, the 3rd cross clock domain cell fifo 810 by clock frequency change For 270MHz.

Fig. 9 is the composition structural representation that embodiment of the present invention 40G Ethernet interface receives side, such as Fig. 9 institute Showing, this 40G Ethernet interface receives side and includes media access control sublayer 901 and PCS sublayer 902；Media access control sublayer 901 connect PCS sublayer 902 by XLGMII interface.

Specifically, PCS sublayer 902 include the 11st converting unit 903, the 12nd converting unit 904, 13 converting unit the 905, the 14th converting unit the 906, first detector unit the 907, second detector units 908, 3rd detector unit the 909, the 4th detector unit the 910, first alignment unit the 911, second Descrambling unit 912, Second decoding unit the 913, the 3rd decoding unit the 914, the 4th decoding unit 915 and the 5th decoding unit 916. When Ethernet interface receives message data, PCS sublayer 902 receives the message data of 4 LANE, each Converting unit, for receiving the message data of a LANE of correspondence, to the corresponding LANE received Message data carry out data width conversion, data width conversion will be carried out and send to corresponding detector unit. Here, the 11st converting unit 903 carries out the mistake of message data width conversion to the 14th converting unit 906 Cheng Jun and the tenth converting unit 803 are identical, and I will not elaborate.

Each detector unit, for detecting and this LANE pair on the LANE residing for the message data received The mark code answered, and the message data received and testing result are sent to the first alignment unit 911.

First alignment unit 911, according to the testing result received, to 4 the LANE message datas received Carry out registration process, the message data after registration process is sent to the second Descrambling unit 912；First alignment Unit 911 can use 4 asynchronous FIFOs to realize.

Second Descrambling unit 912, for carrying out 40G bandwidth class to 4 the LANE message datas received Scramble process, and every LANE message data after scramble process is sent to corresponding decoding unit.

Each decoding unit, is decoded processing to the message data received.Here, the second decoding unit 913 All identical with the first decoding unit 805 to the decoding process of the 5th decoding unit 916, the most detailed State.

Specifically, media access control sublayer 901 includes that the second message recovery unit the 917, the 2nd CRC32 verification is single The 918, second message receiving area of unit reason unit 919, second control message process unit 920 and the 4th are across clock Territory cell fifo 921；Wherein, the second message recovery unit 917 is for by XLGMII interface solution The message data of 4 LANE after code process, handles together the message data received, here, The processing procedure of the second message recovery unit 917 message data to receiving and the first message recovery unit 806 Identical, I will not elaborate.

The implementation of the 2nd CRC32 verification unit 918 and the realization of a CRC32 verification unit 807 Mode is identical, and the implementation of the second message receiving area reason unit 919 receives processing unit 808 with the first message Implementation identical, the implementation of second control message process unit 920 and first-class control packet process The implementation of unit 809 is identical, the implementation of the 4th cross clock domain cell fifo 921 with the 3rd across The implementation of clock zone cell fifo 810 is identical, and I will not elaborate.

The data receiver transposition of the Ethernet interface of third embodiment of the invention can support two kinds of mode of operations, The first is 10G-XFI Ethernet interface pattern, and the second is 40G Ethernet interface pattern, Qi Zhong 4 ports can be could support up under 10G-XFI Ethernet interface pattern and receive message data, at 40G ether Under network interface pattern, support that 1 port receives message data.

Figure 10 is the composition of the PCS sublayer of the data sink of third embodiment of the invention Ethernet interface Structural representation, as shown in Figure 10, this PCS sublayer includes: the 15th converting unit the 1001, the 16th Converting unit the 1002, the 17th converting unit the 1003, the 18th converting unit the 1004, the 5th detector unit 1005, the 6th detector unit the 1006, the 7th detector unit the 1007, the 8th detector unit 1008, second is right Neat unit the 1009, the 3rd Descrambling unit the 1010, the 4th Descrambling unit the 1011, the 5th Descrambling unit 1012, 6th Descrambling unit the 1013, the 7th Descrambling unit the 1014, the 3rd data selection unit the 1015, the 6th decoding Unit 1016, the 7th decoding unit 1017, the 8th decoding unit 1018, the 9th decoding unit 1019, Four data selection unit 1020.

As a width of 10G of the band being pre-selected, the 15th converting unit 1001 is to the 18th converting unit 1004 In each converting unit for receiving the message data of 10G bandwidth input port of correspondence；When be pre-selected When carrying a width of 40G, in the 15th converting unit 1001 to the 18th converting unit 1004, each conversion is single Unit is for receiving the message data of a corresponding LANE in 40G bandwidth input port.PCS sublayer supports 4 The message data input of bar LANE, the message data bit wide of every LANE is 40 bits, every LANE Speed is 10.3125Gbps, and the PCS clock between 4 LANE is with frequency not homophase.

In 15th converting unit 1001 to the 18th converting unit 1004, each converting unit is used for docking The message data received processes, and the message data after processing sends to corresponding detector unit；Here, Each converting unit, to the processing procedure of message data and the tenth converting unit 803, is not described in detail in this.

5th detector unit 1005 is to the 8th detector unit 1008, and each detector unit is for being pre-selected Band a width of 10G time, export after the message data of reception is played bat to the second alignment unit 1009；In advance During a width of 40G of band selected, corresponding with this LANE to detecting on the LANE residing for the message data received Mark code, and by receive message data and testing result send to the second alignment unit 1009.

Being provided with 4 asynchronous FIFOs in second alignment unit 1009, these 4 asynchronous FIFOs are in advance During a width of 10G of band selected, complete the clock frequency conversion to media access control sublayer clock of the PCS sublayer clock, Message data after carrying out clock frequency conversion sends to corresponding Descrambling unit；Specifically, message number After being sent to the second alignment unit, directly write in the asynchronous FIFO of correspondence, non-at asynchronous FIFO Being read out by message data in the case of sky, the clock zone of writing of this asynchronous FIFO is PCS clock zone, reads Clock zone is MAC clock zone, i.e. when a width of 10G of the band being pre-selected, and different in the second alignment unit Step FIFO only realizes the cross clock domain translation function of message data.

These 4 asynchronous FIFOs are for when a width of 40G of the band being pre-selected, it is achieved 4 LANE of reception The alignment operation of message data, and complete the clock frequency conversion to media access control sublayer clock of the PCS sublayer clock, The message data completing alignment operation and clock frequency conversion is sent to the 3rd Descrambling unit 1010；Specifically Say, according to message data and the testing result of corresponding LANE, from detect mark code position start by Message data is written in the asynchronous FIFO that the second alignment unit is corresponding, only whole as 4 asynchronous fifo These 4 asynchronous fifo are initiated read operations when of non-NULL simultaneously the most simultaneously, this asynchronous FIFO write clock Territory is PCS clock zone, and reading clock zone is MAC clock zone.It can be seen that it is a width of at the band being pre-selected During 40G, the asynchronous FIFO in the second alignment unit realizes the registration process of message data and cross clock domain turns Change function.

3rd Descrambling unit 1010, carries out 40G bandwidth class for every the LANE message data received Scramble process, by after scramble process message data send to the 3rd data selection unit 1015；4th solves Disturb unit 1011 to each Descrambling unit in the 7th Descrambling unit 1014 for the message data received is entered The scramble process of row 10G bandwidth class, sends to the 3rd data selection single by the message data after scramble process Unit 1015.

3rd data selection unit 1015, for when a width of 10G of the band being pre-selected, selects to solve from the 4th Disturb unit 1011 and receive message data to the 7th Descrambling unit 1014；When a width of 40G of the band being pre-selected, Select to receive the message data of 4 articles of LANE from the 3rd Descrambling unit.3rd data selection unit is by reception Message data sends to corresponding decoding unit.

Each decoding unit in 6th decoding unit 1016 to the 9th decoding unit 1019 is for reception Message data carries out 66b/64b decoding, and the 66 bit message data received are decoded as 64 bit message numbers According to, the message data decoding generation here is ethernet frame.6th decoding unit 1016 is to the 9th decoding unit The ethernet frame generated after decoding is sent to the 4th data selection unit by each decoding unit in 1019 1020。

4th data selection unit 1020, is used for when a width of 10G of the band being pre-selected, the ether that will receive Net frame is sent to PCS sublayer by XGMII interface；When a width of 40G of the band being pre-selected, will receive Ethernet frame by XLGMII interface send to media access control sublayer.Here, the ethernet frame being sent out Message data bit wide be 64 bits.

The PCS sublayer of the data sink of third embodiment of the invention Ethernet interface is capable of In IEEE802.3 standard, the PCS sublayer of defined receives the basic function of side, can be connect by XLGMII Mouth sends data to media access control sublayer or sends data by 4 XGMII interfaces to media access control sublayer.

Figure 11 is the composition of the media access control sublayer of the data sink of third embodiment of the invention Ethernet interface Structural representation, as shown in figure 11, this media access control sublayer includes: the 3rd message recovery unit the 1101, the 4th Message recovery unit the 1102, the 5th message recovery unit the 1103, the 6th message recovery unit the 1104, the 7th Message recovery unit the 1105, first bit wide concatenation unit the 1106, second bit wide concatenation unit the 1107, the 3rd Bit wide concatenation unit the 1108, the 4th bit wide concatenation unit the 1109, first packet buffer unit 1110, second Packet buffer unit the 1111, the 3rd packet buffer unit the 1112, the 4th packet buffer unit the 1113, the 3rd CRC32 verification unit the 1114, the 3rd message receives processing unit 1115 and the 3rd stream control message process unit 1116。

Specifically, the 3rd message recovery unit 1101, for being descapsulated into Ethernet by the ethernet frame of reception Message, is sent out this Ethernet message；4th message recovery unit 1102 is to the 7th message recovery unit In 1105, each message recovery unit, should for the ethernet frame of reception is descapsulated into Ethernet message Ethernet message is sent out.

First bit wide concatenation unit 1106, for when a width of 40G of the band being pre-selected, receives the 3rd message The Ethernet message that recovery unit 1101 sends；Be pre-selected when being opened for 10G, receive the 4th report The Ethernet that literary composition recovery unit 1102 sends to message recovery unit corresponding in the 7th message recovery unit 1105 Message.Here, when a width of 40G of the band being pre-selected, it is also possible to use the second bit wide concatenation unit 1107, 3rd bit wide concatenation unit 1108 or the 4th bit wide concatenation unit 1109 receive the 3rd message recovery unit The 1101 Ethernet messages sent, it is also possible to use newly-increased bit wide concatenation unit to receive the 3rd message and recover single The Ethernet message that unit 1101 sends.

Each bit wide concatenation unit, for being spliced by the multiple Ethernet messages received successively, generates 256 Ethernet message after the splicing of bit, sends Ethernet message after the splicing of 256 bits to corresponding message Buffer unit.

Each packet buffer unit is for caching Ethernet message after the splicing of 256 bits received； As a width of 40G of the band being pre-selected, Ethernet message from the first packet buffer unit, reading is gone out Ethernet message is respectively sent to the 3rd CRC32 verification unit 1114 and the 3rd message receives processing unit 1115。

As the described a width of 10G of the band being pre-selected, four packet buffer unit are according to the mode of polling dispatching To media access control sublayer incoming message data, the data of the message data of the input port input of each 10G bandwidth Bit wide is consistent.Here, the data bit width of the message data that each packet buffer unit inputs every time is identical, all It is 256 bits.Specifically, four packet buffer unit according to the mode of polling dispatching to media access control sublayer Incoming message data include: the most repeatedly receive message data from four packet buffer unit, often When secondary circulation receives message data, carry out message data reception according to the order of the packet buffer unit set.

It should be noted that any one the packet buffer unit in four packet buffer unit does not has message data When media access control sublayer inputs, then need also exist for receiving message data into corresponding packet buffer unit distribution Time.

Message as the media access control sublayer of the data sink of third embodiment of the invention Ethernet interface delays The another kind of implementation of memory cell, as a width of 10G of the band being pre-selected, each packet buffer unit makes Carry out Ethernet packet buffer with a synchronization fifo, as a width of 40G of the band being pre-selected, only use One packet buffer unit carries out the caching of Ethernet message.As a width of 10G of the band being pre-selected, according to The mode of polling dispatching judges the synchronization fifo whether non-NULL of each packet buffer unit, and non-NULL is then read Taking, sky is not read out, and no matter is to read or do not read, all can take a time slot of polling dispatching. So, the Ethernet message in four packet buffer unit can interweave in the way of polling dispatching and is input to the 3rd Message receives processing unit.

As a width of 40G of the band being pre-selected, when reading Ethernet message, all can judge the first message every time Whether the synchronization fifo in buffer unit, and non-NULL is then read out, and sky is not read out.So, read The message taken can be input to the 3rd message from fixing packet buffer unit and receive processing unit.At this moment, to report The message of literary composition buffer unit read can be regarded as being pre-selected with the report of message buffer unit during a width of 10G A kind of special circumstances that literary composition reads.

As a width of 10G of the band being pre-selected, media access control sublayer reads for from each packet buffer unit Message data carry out time-division processing, during time-division processing, the 3rd CRC32 verification unit 1114, 3rd message receives processing unit 1115 and the 3rd stream control message process unit 1116 all by the form with timesharing Multiplexing.Here, the 3rd CRC32 verification unit 1114 and the realization side of a CRC32 verification unit 807 Formula is identical, and the 3rd message receives processing unit 1115 and the implementation of the first message reception processing unit 808 Identical, the 3rd stream control message process unit 1116 and the implementation phase of first-class control packet processing unit 809 With, the most all it is not repeated to describe.By the 3rd CRC32 verification unit the 1114, the 3rd message is received Processing unit 1115 and the time-sharing multiplex of the 3rd stream control message process unit 1116, save logical resource.

The media access control sublayer of the data sink of third embodiment of the invention Ethernet interface realizes IEEE802.3 In standard, the media access control sublayer of defined receives the basic function of side.Media access control sublayer can be same on input direction Time support that four XGMII interfaces or 1 XLGMII interface carry out message data input；At outbound course On, the message fragment bit wide of output is 256bit, when carrying out message data output, according to selected band Width carries out the output of Ethernet message.

Here, side is received for the 10G-XFI Ethernet interface shown in Fig. 8, Ethernet message after to When the output port of media access control sublayer sends, just carry out the PCS sublayer clock clock zone to media access control sublayer clock Conversion；Receiving side for the 40G Ethernet interface shown in Fig. 9, the cross clock domain operation of message data includes: The PCS to any one LANE is changed from the PCS clock zone of each bar LANE in the first alignment unit Clock zone, Ethernet message is when sending to the output port of media access control sublayer, by a corresponding LANE's PCS clock zone is changed to media access control sublayer clock zone.And at the number of third embodiment of the invention Ethernet interface According to receiving in device, the bandwidth no matter being pre-selected is 10G or 40G, the cross clock domain behaviour of message data It is all within the asynchronous FIFO of the second alignment unit realizing, as such, it is possible to save FIFO resource, and And make the easier of cross clock domain operation change.

4th embodiment

The embodiment of the present invention also proposed a kind of Ethernet interface, this Ethernet interface include above-mentioned any one The data processing equipment of Ethernet interface.

5th embodiment

For the method for first embodiment of the invention, the embodiment of the present invention also proposed a kind of Ethernet interface Data processing method.

Figure 12 is the flow chart of the data processing method of sixth embodiment of the invention Ethernet interface, such as Figure 12 Shown in, the method includes:

Step 1200: select the bandwidth of Ethernet interface.

Here, Ethernet interface includes at least with next height layer: media access control sublayer and PCS sublayer.

This step specifically includes: select the bandwidth of Ethernet interface at multiple band alleviating distention in middle-JIAO to be selected, described many Individual bandwidth to be selected includes the first bandwidth and the second bandwidth, and the second with a width of first bandwidth N times, N is Natural number more than 1.

Step 1201: the message data sending from Ethernet interface or receiving is carried out based on selected bandwidth Process, when the message data sending from Ethernet interface or receiving being processed based on different bandwidth, With the resource within Ethernet interface described in the form multiplexing of timesharing.

Here, carry out process based on the selected bandwidth message data to sending from Ethernet interface to include: The message data that self is received by described media access control sublayer based on selected bandwidth processes, after processing Message data send to PCS sublayer；And/or, described PCS sublayer based on selected bandwidth to self The message data received processes.

The described message data self received is being carried out by media access control sublayer or PCS sublayer based on different bandwidth During process, with the resource of the form multiplexing therein of timesharing.

Further, described PCS sublayer includes cross clock domain converting unit, when being used for realizing media access control sublayer Clock is changed to the cross clock domain of PCS sublayer clock；Described PCS sublayer based on different bandwidth to described from When the message data that body receives processes, with cross clock domain converting unit described in the form multiplexing of timesharing.

Those skilled in the art are it should be appreciated that embodiments of the invention can be provided as method, system or meter Calculation machine program product.Therefore, the present invention can use hardware embodiment, software implementation or combine software and The form of the embodiment of hardware aspect.And, the present invention can use and wherein include calculating one or more The computer-usable storage medium of machine usable program code (includes but not limited to disk memory and optical storage Device etc.) form of the upper computer program implemented.

The present invention is with reference to method, equipment (system) and computer program according to embodiments of the present invention Flow chart and/or block diagram describe.It should be understood that can be by computer program instructions flowchart and/or side Flow process in each flow process in block diagram and/or square frame and flow chart and/or block diagram and/or the knot of square frame Close.Can provide these computer program instructions to general purpose computer, special-purpose computer, Embedded Processor or The processor of other programmable data processing device is to produce a machine so that by computer or other can The instruction that the processor of programming data processing equipment performs produces for realizing in one flow process or multiple of flow chart The device of the function specified in flow process and/or one square frame of block diagram or multiple square frame.

These computer program instructions may be alternatively stored in and can guide computer or other programmable data processing device In the computer-readable memory worked in a specific way so that be stored in this computer-readable memory Instruction produces the manufacture including command device, and this command device realizes at one flow process of flow chart or multiple stream The function specified in journey and/or one square frame of block diagram or multiple square frame.

These computer program instructions also can be loaded in computer or other programmable data processing device, makes Sequence of operations step must be performed to produce computer implemented place on computer or other programmable devices Reason, thus the instruction performed on computer or other programmable devices provides for realizing flow chart one The step of the function specified in flow process or multiple flow process and/or one square frame of block diagram or multiple square frame.

The above, only presently preferred embodiments of the present invention, it is not intended to limit the protection model of the present invention Enclose.

Claims

1. the data processing equipment of an Ethernet interface, it is characterised in that described device includes: select mould Block and interface module, wherein,

Select module, for selecting the bandwidth of Ethernet interface；

Device the most according to claim 1, it is characterised in that described interface module includes below at least One sublayer: media access control MAC sublayer and physical code PCS sublayer；Wherein,

Device the most according to claim 2, it is characterised in that described PCS sublayer includes across clock Territory converting unit, for realizing the cross clock domain conversion to PCS sublayer clock of the media access control sublayer clock；

Device the most according to claim 1, it is characterised in that described selection module, for multiple Band alleviating distention in middle-JIAO to be selected selects the bandwidth of Ethernet interface, and the plurality of bandwidth to be selected includes the first bandwidth With the second bandwidth, the second with a width of first bandwidth N times, N is the natural number more than 1.

Device the most according to claim 4, it is characterised in that described interface module includes below at least One sublayer: media access control sublayer and PCS sublayer；Wherein, described media access control sublayer has N number of first bandwidth Input port and a second bandwidth input port；Described PCS sublayer has N number of first bandwidth input port With a second bandwidth input port；

6. according to the device described in any one of claim 1 to 5, it is characterised in that in described interface module The resource in portion includes at least one resource following: calculation resources and storage resource.

7. an Ethernet interface, it is characterised in that described Ethernet interface includes claim 1 to 6 The data processing equipment of the Ethernet interface described in any one.

8. the data processing method of an Ethernet interface, it is characterised in that described method includes:

Select the bandwidth of Ethernet interface；

Method the most according to claim 8, it is characterised in that described Ethernet interface include at least with Next sublayer: media access control sublayer and PCS sublayer；

Method the most according to claim 9, it is characterised in that described PCS sublayer includes across clock Territory converting unit, for realizing the cross clock domain conversion to PCS sublayer clock of the media access control sublayer clock；