CN106292106B - A kind of circuit structure of array substrate - Google Patents

A kind of circuit structure of array substrate Download PDF

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Publication number
CN106292106B
CN106292106B CN201610794551.9A CN201610794551A CN106292106B CN 106292106 B CN106292106 B CN 106292106B CN 201610794551 A CN201610794551 A CN 201610794551A CN 106292106 B CN106292106 B CN 106292106B
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China
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sub
pixel
main
data line
tft
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CN201610794551.9A
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Chinese (zh)
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CN106292106A (en
Inventor
璧典附
赵丽
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深圳市华星光电技术有限公司
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    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line

Abstract

The present invention provides a kind of circuit structure of array substrate, comprising: a plurality of grid line;Multiple data lines;Picture element matrix;Multiple thin film transistor (TFT)s;Wherein, every grid line is by the grid of connection a line thin film transistor (TFT) to control a line sub-pixel, each sub-pixel connects a main data line and one data line by a thin film transistor (TFT), main data line is connect by a thin film transistor (TFT) with main pixel region, secondary data line is connect by another thin film transistor (TFT) with sub-pixel area, and the voltage of the data-signal of main data line input is greater than time voltage of the data-signal of data line input.The present invention realizes the colour cast compensation to the big visual angle of liquid crystal display panel, effectively prevents the problem of liquid crystal display panel aperture opening ratio becomes smaller.

Description

A kind of circuit structure of array substrate

[technical field]

The present invention relates to field of liquid crystal display, in particular to a kind of circuit structure of array substrate.

[background technique]

The flat display apparatus such as liquid crystal display (Liquid Crystal Display, LCD) are because having high image quality, saving Electricity, fuselage are thin and the advantages that have a wide range of application, and be widely used in mobile phone, TV, personal digital assistant, digital camera, The various consumer electrical products such as laptop, desktop computer, become the mainstream in display device.Liquid on existing market Crystal device is largely backlight liquid crystal display comprising liquid crystal display panel (TFT-LCD) and backlight module (backlight module).The working principle of liquid crystal display panel is that liquid crystal point is placed in the parallel glass substrate of two panels Son, there are many tiny electric wires vertically and horizontally for two panels glass substrate centre, and liquid crystal molecule is controlled whether by being powered and is changed The light refraction of backlight module is come out and generates picture by direction.For the LCD display panel on current mainstream market, it can divide It is twisted-nematic (Twisted Nematic, TN) or super twisted nematic (Super Twisted respectively for three types Nematic, STN) type, plane conversion (In-Plane Switching, IPS) type and vertical orientation (Vertical Alignment, VA) type.Wherein, VA type liquid crystal display panel has high comparison compared to other kinds of liquid crystal display panel Degree, shows in large scale, as TV etc. has very wide application.But since VA type liquid crystal display panel is turned using vertical The diversity ratio of dynamic liquid crystal, liquid crystal molecule birefringence is larger, and colour cast (color shift) problem under big visual angle is caused to compare Seriously, so that the luminance difference seen from different perspectives of VA type liquid crystal display panel is larger, distortion is caused.

As the common display technology of liquid crystal display panel, VA (Vertical Alignment) display pattern has height Contrast and without advantages such as friction matchings.But the also some disadvantages of simultaneous, wherein the colour cast problem under different angle of visibilities It is the key subjects that VA product design must face.8 domain structures are the usual means that VA mode improves big visual angle colour cast problem.Mesh Preceding 8 domain structures design is based on electrical principles, under the premise of guaranteeing the azimuth of liquid crystal molecule is 45 °, by controlling liquid crystal The size of voltage, makes in the same sub-pixel that wherein the liquid crystal molecule deflection angle on 4 farmlands and other 4 farmlands is different, realizes 8 The different liquid crystal aligning of kind, the colour cast problem at big visual angle is compensated with this.In the prior art, 2D1G, 2G1D or electric resistance partial pressure skill Art is the common technology for solving the problems, such as VA type liquid crystal display panel colour cast at present.A kind of existing film using 2D1G technology is brilliant Body pipe (TFT) array substrate, multiple sub-pixels including array arrangement, it is main pixel region and sub-pixel that each sub-pixel, which is divided equally, Area, the main pixel region of each sub-pixel connect a main pixel region TFT, and the sub-pixel area of each sub-pixel connects a pixel region, A grid line is arranged in corresponding every a line sub-pixel, and corresponding each column sub-pixel setting is located at the secondary picture of its arranged on left and right sides Plain area's data line and main pixel region data line, sub-pixel area data line provide time data-signal extremely by sub-pixel area TFT The sub-pixel area, the main pixel region data line provide main data signal to the main pixel region by main pixel region TFT.Institute The potential difference that the potential difference between main data signal and common voltage is greater than between the secondary data-signal and common voltage is stated, is made Winner's pixel region is different from the charge rate in sub-pixel area, to propose high color reproduction degree under different viewing angles, improves colour cast.On Although colour cast can be improved by stating the existing tft array substrate using 2D1G technology, this design is needed the number of data line Mesh doubles, and not only makes the increased costs for driving IC, and it is crowded also to will cause fanout area (Fanout), aggravates RC delay (RC), charge efficiency is reduced, the competitiveness of product is influenced.

[summary of the invention]

The purpose of the present invention is to provide a kind of circuit structures of array substrate, aobvious at big visual angle to improve VA display pattern Colour cast problem under showing, while improving the problem of multidomain structure pixel aperture ratio and liquid crystal display panel penetrance reduce.

Technical scheme is as follows:

A kind of circuit structure of array substrate, comprising:

It is a plurality of to be parallel to each other and horizontally arranged grid line, for driving picture element matrix;

The a plurality of data line for being parallel to each other and being vertically arranged is divided into alternately arranged main data line two-by-two and time data Line, and be mutually perpendicular to a plurality of grid line, it is used for the picture element matrix input data signal;

Picture element matrix, including it is multiple at array arrange sub-pixels, each sub-pixel be divided into main pixel region and time Pixel region, the main pixel region and the sub-pixel area are insulated from each other, for receiving and showing the data-signal;

Multiple thin film transistor (TFT)s, the grid of each thin film transistor (TFT) are connect with a grid line, source electrode and one The connection of data line described in item, drains and connect with the main pixel region of sub-pixel or the sub-pixel area;

Wherein, every grid line is by the grid of thin film transistor (TFT) described in connection a line to control sub- picture described in a line Element, each sub-pixel connect the main data line and a secondary data line, institute by the thin film transistor (TFT) It states main data line to connect by a thin film transistor (TFT) with the main pixel region, the secondary data line passes through another film Transistor is connect with the sub-pixel area, and the voltage of the data-signal of main data line input is defeated greater than the secondary data line The voltage of the data-signal entered.

Preferably, every main data line two sides pass through each sub- picture of each thin film transistor (TFT) connection respectively The main pixel region of element, every secondary data line two sides pass through each thin film transistor (TFT) respectively and connect each son The sub-pixel area of pixel.

Preferably, multiple thin film transistor (TFT)s are divided into main thin film transistor (TFT) and time thin film transistor (TFT) two parts, every institute It states and is all connected with the main thin film transistor (TFT) at left and right sides of main data line, be all connected with institute at left and right sides of every secondary data line State time thin film transistor (TFT).

Preferably, the main pixel region of each sub-pixel arranges in the horizontal direction with the sub-pixel area, one In the row sub-pixel, the main pixel region of the two neighboring sub-pixel and the arrangement mode in the sub-pixel area on the contrary, In a column sub-pixel, the main pixel region and the arrangement mode phase in the sub-pixel area of the two neighboring sub-pixel Together.

Preferably, the sub-pixel includes red sub-pixel, green sub-pixels and blue subpixels, and two neighboring described The color of sub-pixel is different.

A kind of circuit structure of array substrate, comprising:

It is a plurality of to be parallel to each other and horizontally arranged grid line, for driving picture element matrix;

The a plurality of data line for being parallel to each other and being vertically arranged is divided into alternately arranged main data line two-by-two and time data Line, and be mutually perpendicular to a plurality of grid line, it is used for the picture element matrix input data signal;

Picture element matrix, including it is multiple at array arrange sub-pixels, each sub-pixel be divided into main pixel region and time Pixel region, the main pixel region and the sub-pixel area are insulated from each other, for receiving and showing the data-signal;

Multiple thin film transistor (TFT)s, the grid of each thin film transistor (TFT) are connect with a grid line, source electrode and one The connection of data line described in item, drains and connect with the main pixel region of sub-pixel or the sub-pixel area;

Wherein, every grid line is by the grid of thin film transistor (TFT) described in two rows of connection to control sub- picture described in two rows Element, each sub-pixel connect the main data line and a secondary data line, institute by the thin film transistor (TFT) It states main data line to connect by a thin film transistor (TFT) with the main pixel region, the secondary data line passes through another film Transistor is connect with the sub-pixel area, and the voltage of the data-signal of main data line input is defeated greater than the secondary data line The voltage of the data-signal entered.

Preferably, the main pixel region of each sub-pixel arranges along the vertical direction with the sub-pixel area, one In the row sub-pixel, the main pixel region of the two neighboring sub-pixel and the arrangement mode in the sub-pixel area on the contrary, In a column sub-pixel, the main pixel region and the arrangement mode phase in the sub-pixel area of the two neighboring sub-pixel Instead.

Preferably, in time data line described in the main data line described in same or same, two adjacent films Transistor be separately connected the two neighboring sub-pixel the main pixel region or the sub-pixel area, and two films Transistor grid line traffic control as described in same.

Preferably, the sub-pixel includes red sub-pixel, green sub-pixels and blue subpixels, and two neighboring described The color of sub-pixel is different.

Preferably, multiple thin film transistor (TFT)s are divided into main thin film transistor (TFT) and time thin film transistor (TFT) two parts, every institute It states main data line and is all connected with the main thin film transistor (TFT), every secondary data line is all connected with the secondary thin film transistor (TFT).

Beneficial effects of the present invention:

A kind of circuit structure of array substrate of the invention, using change data line and grid line driving method design, Main pixel region and the sub-pixel area for controlling each sub-pixel respectively keep the driving voltage value in two kinds of regions different, and change whereby The charging situation of the main pixel region of each sub-pixel and sub-pixel area in liquid crystal display panel, and then influence main pixel region and sub-pixel area Liquid crystal molecule deflection angle, realize to the compensation of the colour cast at liquid crystal display panel big visual angle, effectively prevent liquid crystal display The problem of panel aperture ratio becomes smaller.

[Detailed description of the invention]

Fig. 1 is a kind of partial schematic diagram of the circuit structure of array substrate of the embodiment of the present invention;

Fig. 2 is the partial schematic diagram of the circuit structure of another array substrate of the embodiment of the present invention.

[specific embodiment]

The explanation of following embodiment is to can be used to the particular implementation of implementation to illustrate the present invention with reference to additional schema Example.The direction term that the present invention is previously mentioned, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outside", " side " Deng being only the direction with reference to annexed drawings.Therefore, the direction term used be to illustrate and understand the present invention, rather than to The limitation present invention.The similar unit of structure is to be given the same reference numerals in the figure.

Embodiment one

Basic principle of the invention is, by the way that each sub-pixel to be divided into two parts insulated from each other, a part For main pixel region Main, remaining part is sub-pixel area Sub, then by the main pixel region Main and sub-pixel area Sub Different voltage is inputted respectively, keeps the liquid crystal deflection angle of two pixel regions insulated from each other different, to realize to liquid crystal The colour cast at the big visual angle of display panel compensates.

Referring to FIG. 1, Fig. 1 is a kind of partial schematic diagram of the circuit structure of array substrate of the present embodiment, it can be with from Fig. 1 See, a kind of circuit structure of array substrate of the invention, comprising:

It is a plurality of to be parallel to each other and horizontally arranged grid line, for driving picture element matrix.G (n-1), G as shown in Figure 1 (n) and G (n+1).

The a plurality of data line for being parallel to each other and being vertically arranged is divided into alternately arranged main data line MD two-by-two and time data Line SD, and be mutually perpendicular to a plurality of grid line, it is used for the picture element matrix input data signal.D as shown in Figure 1 (j-1), D (j) and D (j+1).

Picture element matrix, including multiple sub-pixels arranged at array, each sub-pixel is divided into main pixel region Main With sub-pixel area Sub, the main pixel region Main and the sub-pixel area Sub are insulated from each other, for receiving and showing the number It is believed that number.The part that Fig. 1 dotted line encloses is exactly the sub-pixel.

In the present embodiment, the sub-pixel includes red sub-pixel, green sub-pixels and blue subpixels, and adjacent two The color of a sub-pixel is different.

Multiple thin film transistor (TFT)s, the grid of each thin film transistor (TFT) are connect with a grid line, source electrode and one The connection of data line described in item, drain electrode are connect with the main pixel region Main or the sub-pixel area Sub of a sub-pixel.

In the present embodiment, multiple thin film transistor (TFT)s are divided into main thin film transistor (TFT) TM and time thin film transistor (TFT) TS two Point, it is all connected with the main thin film transistor (TFT) TM at left and right sides of every main data line MD, every secondary data line SD's The left and right sides is all connected with the secondary thin film transistor (TFT) TS.

Wherein, every grid line is by the grid of thin film transistor (TFT) described in connection a line to control sub- picture described in a line Element, each sub-pixel connect a main data line MD and a secondary data line by the thin film transistor (TFT) SD, the main data line MD are connect by a thin film transistor (TFT) with the main pixel region Main, and the secondary data line SD is logical It crosses another thin film transistor (TFT) to connect with the sub-pixel area Sub, and the electricity of the data-signal of main data line MD input Pressure is greater than the voltage of the data-signal of the secondary data line SD input.It is to be understood that being the main data line MD output letter Number grayscale value, be greater than the grayscale value of the secondary data line SD output signal, the main pixel region Main described in this way and described time The grey menu of pixel region Sub just difference, i.e. the corresponding liquid crystal deflection angle of two pixel regions can be different, to solve Colour cast problem.

In the present embodiment, it is each to pass through each thin film transistor (TFT) connection respectively for every two sides the main data line MD The main pixel region Main of the sub-pixel, every two sides secondary data line SD pass through each thin film transistor (TFT) respectively Connect the sub-pixel area Sub of each sub-pixel.

In the present embodiment, the main pixel region Main and the sub-pixel area Sub of each sub-pixel are along level Direction arranges, in the sub-pixel described in a line, the main pixel region Main of the two neighboring sub-pixel and the sub-pixel The arrangement mode of area Sub on the contrary, in a column sub-pixel, the main pixel region Main of the two neighboring sub-pixel with The arrangement mode of the sub-pixel area Sub is identical.This arrangement side of the main pixel region Main and the sub-pixel area Sub Formula is to make a sub-pixel at left and right sides of the main data line MD close to its pixel region all be the master Pixel region Main, and for making the picture of a sub-pixel at left and right sides of a secondary data line SD close to it Plain area is all the sub-pixel area Sub, thus facilitates connection.

A kind of circuit structure of array substrate of the invention, using change data line and grid line driving method design, The main pixel region Main and sub-pixel area Sub for controlling each sub-pixel respectively keep the driving voltage value in two kinds of regions different, and borrow This changes the charging situation of the main pixel region Main and sub-pixel area Sub of each sub-pixel in liquid crystal display panel, and then influences main picture The deflection angle of the liquid crystal molecule of plain area Main and sub-pixel area Sub realizes the colour cast benefit to the big visual angle of liquid crystal display panel It repays, effectively prevents the problem of liquid crystal display panel aperture opening ratio becomes smaller.

Embodiment two

Basic principle of the invention is, by the way that each sub-pixel to be divided into two parts insulated from each other, a part For main pixel region Main, remaining part is sub-pixel area Sub, then by the main pixel region Main and sub-pixel area Sub Different voltage is inputted respectively, keeps the liquid crystal deflection angle of two pixel regions insulated from each other different, to realize to liquid crystal The colour cast at the big visual angle of display panel compensates.

Referring to FIG. 2, Fig. 2 is a kind of partial schematic diagram of the circuit structure of array substrate of the present embodiment, it can be with from Fig. 2 See, a kind of circuit structure of array substrate of the invention, comprising:

It is a plurality of to be parallel to each other and horizontally arranged grid line, for driving picture element matrix.G (n-1) as shown in Figure 2 and G (n)。

The a plurality of data line for being parallel to each other and being vertically arranged is divided into alternately arranged main data line MD two-by-two and time data Line SD, and be mutually perpendicular to a plurality of grid line, it is used for the picture element matrix input data signal.D as shown in Figure 2 (j-1), D (j), D (j+1) and D (j+2).

Picture element matrix, including multiple sub-pixels arranged at array, each sub-pixel is divided into main pixel region Main With sub-pixel area Sub, the main pixel region Main and the sub-pixel area Sub are insulated from each other, for receiving and showing the number It is believed that number.The part that Fig. 2 dotted line encloses is exactly the sub-pixel.

In the present embodiment, the sub-pixel includes red sub-pixel, green sub-pixels and blue subpixels, and adjacent two The color of a sub-pixel is different.

Multiple thin film transistor (TFT)s, the grid of each thin film transistor (TFT) are connect with a grid line, source electrode and one The connection of data line described in item, drain electrode are connect with the main pixel region Main or the sub-pixel area Sub of a sub-pixel.

In the present embodiment, multiple thin film transistor (TFT)s are divided into main thin film transistor (TFT) TM and time thin film transistor (TFT) TS two Point, every main data line MD is all connected with the main thin film transistor (TFT) TM, and every secondary data line SD is all connected with described time Thin film transistor (TFT) TS.

Wherein, every grid line is by the grid of thin film transistor (TFT) described in two rows of connection to control sub- picture described in two rows Element, each sub-pixel connect a main data line MD and a secondary data line by the thin film transistor (TFT) SD, the main data line MD are connect by a thin film transistor (TFT) with the main pixel region Main, and the secondary data line SD is logical It crosses another thin film transistor (TFT) to connect with the sub-pixel area Sub, and the electricity of the data-signal of main data line MD input Pressure is greater than the voltage of the data-signal of the secondary data line SD input.It is to be understood that being the main data line MD output letter Number grayscale value, be greater than the grayscale value of the secondary data line SD output signal, the main pixel region Main described in this way and described time The grey menu of pixel region Sub just difference, i.e. the corresponding liquid crystal deflection angle of two pixel regions can be different, to solve Colour cast problem.

In the present embodiment, the main pixel region Main and sub-pixel area Sub of each sub-pixel is along vertical Direction arranges, in the sub-pixel described in a line, the main pixel region Main of the two neighboring sub-pixel and the sub-pixel The arrangement mode of area Sub on the contrary, in a column sub-pixel, the main pixel region Main of the two neighboring sub-pixel with The arrangement mode of the sub-pixel area Sub is opposite.This arrangement side of the main pixel region Main and the sub-pixel area Sub Formula is to make a sub-pixel of grid line or more two sides close to its pixel region all be the main pixel Area Main is the sub-pixel area Sub, thus facilitates connection.

In the present embodiment, in time data line SD described in main data line MD or same described in same, adjacent two A thin film transistor (TFT) be separately connected the two neighboring sub-pixel the main pixel region Main or the sub-pixel area Sub, and two thin film transistor (TFT) grid line traffic controls as described in same.

A kind of circuit structure of array substrate of the invention, using change data line and grid line driving method design, The main pixel region Main and sub-pixel area Sub for controlling each sub-pixel respectively keep the driving voltage value in two kinds of regions different, and borrow This changes the charging situation of the main pixel region Main and sub-pixel area Sub of each sub-pixel in liquid crystal display panel, and then influences main picture The deflection angle of the liquid crystal molecule of plain area Main and sub-pixel area Sub realizes the colour cast benefit to the big visual angle of liquid crystal display panel It repays, effectively prevents the problem of liquid crystal display panel aperture opening ratio becomes smaller.

In conclusion although the present invention has been disclosed above in the preferred embodiment, but above preferred embodiment is not to limit The system present invention, those skilled in the art can make various changes and profit without departing from the spirit and scope of the present invention Decorations, therefore protection scope of the present invention subjects to the scope of the claims.

Claims (8)

1. a kind of circuit structure of array substrate characterized by comprising
It is a plurality of to be parallel to each other and horizontally arranged grid line, for driving picture element matrix;
The a plurality of data line for being parallel to each other and being vertically arranged is divided into alternately arranged main data line two-by-two and time data line, and It is mutually perpendicular to, is used for the picture element matrix input data signal with a plurality of grid line;
Picture element matrix, including multiple sub-pixels arranged at array, each sub-pixel is divided into main pixel region and sub-pixel Area, the main pixel region and the sub-pixel area are insulated from each other, for receiving and showing the data-signal;
Multiple thin film transistor (TFT)s, the grid of each thin film transistor (TFT) are connect with a grid line, source electrode and an institute Data line connection is stated, drains and is connect with the main pixel region of sub-pixel or the sub-pixel area;
Wherein, every grid line by the grid of thin film transistor (TFT) described in connection a line to control sub-pixel described in a line, Each sub-pixel connects the main data line and a secondary data line, the master by the thin film transistor (TFT) Data line is connect by a thin film transistor (TFT) with the main pixel region, and the secondary data line passes through another film crystal Pipe is connect with the sub-pixel area, and the voltage of the data-signal of main data line input is greater than the secondary data line input The voltage of data-signal;
The main pixel region of each sub-pixel arranges in the horizontal direction with the sub-pixel area, the sub-pixel described in a line In, the main pixel region of the two neighboring sub-pixel and the arrangement mode in the sub-pixel area are on the contrary, in column In pixel, the main pixel region of the two neighboring sub-pixel is identical as the arrangement mode in the sub-pixel area.
2. circuit structure according to claim 1, which is characterized in that every main data line two sides pass through each respectively The thin film transistor (TFT) connects the main pixel region of each sub-pixel, and every secondary data line two sides pass through respectively respectively A thin film transistor (TFT) connects the sub-pixel area of each sub-pixel.
3. circuit structure according to claim 1, which is characterized in that multiple thin film transistor (TFT)s are divided into main film crystal Guan Yuci thin film transistor (TFT) two parts, are all connected with the main thin film transistor (TFT) at left and right sides of every main data line, and every The secondary thin film transistor (TFT) is all connected at left and right sides of the secondary data line.
4. circuit structure according to claim 1, which is characterized in that the sub-pixel includes red sub-pixel, green Pixel and blue subpixels, and the color of the two neighboring sub-pixel is different.
5. a kind of circuit structure of array substrate characterized by comprising
It is a plurality of to be parallel to each other and horizontally arranged grid line, for driving picture element matrix;
The a plurality of data line for being parallel to each other and being vertically arranged is divided into alternately arranged main data line two-by-two and time data line, and It is mutually perpendicular to, is used for the picture element matrix input data signal with a plurality of grid line;
Picture element matrix, including multiple sub-pixels arranged at array, each sub-pixel is divided into main pixel region and sub-pixel Area, the main pixel region and the sub-pixel area are insulated from each other, for receiving and showing the data-signal;
Multiple thin film transistor (TFT)s, the grid of each thin film transistor (TFT) are connect with a grid line, source electrode and an institute Data line connection is stated, drains and is connect with the main pixel region of sub-pixel or the sub-pixel area;
Wherein, every grid line by the grid of thin film transistor (TFT) described in two rows of connection to control sub-pixel described in two rows, Each sub-pixel connects the main data line and a secondary data line, the master by the thin film transistor (TFT) Data line is connect by a thin film transistor (TFT) with the main pixel region, and the secondary data line passes through another film crystal Pipe is connect with the sub-pixel area, and the voltage of the data-signal of main data line input is greater than the secondary data line input The voltage of data-signal;
The main pixel region of each sub-pixel arranges along the vertical direction with the sub-pixel area, the sub-pixel described in a line In, the main pixel region of the two neighboring sub-pixel and the arrangement mode in the sub-pixel area are on the contrary, in column In pixel, the main pixel region of the two neighboring sub-pixel is opposite with the arrangement mode in the sub-pixel area.
6. circuit structure according to claim 5, which is characterized in that described in the main data line described in same or same In secondary data line, two adjacent thin film transistor (TFT)s be separately connected the two neighboring sub-pixel the main pixel region or The sub-pixel area, and two thin film transistor (TFT) grid line traffic controls as described in same.
7. circuit structure according to claim 5, which is characterized in that the sub-pixel includes red sub-pixel, green Pixel and blue subpixels, and the color of the two neighboring sub-pixel is different.
8. circuit structure according to claim 5, which is characterized in that multiple thin film transistor (TFT)s are divided into main film crystal Guan Yuci thin film transistor (TFT) two parts, every main data line are all connected with the main thin film transistor (TFT), every secondary data Line is all connected with the secondary thin film transistor (TFT).
CN201610794551.9A 2016-08-31 2016-08-31 A kind of circuit structure of array substrate CN106292106B (en)

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CN106292106B true CN106292106B (en) 2019-11-26

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