CN106252234A - Nmos pass transistor and preparation method thereof, CMOS transistor - Google Patents
Nmos pass transistor and preparation method thereof, CMOS transistor Download PDFInfo
- Publication number
- CN106252234A CN106252234A CN201610740789.3A CN201610740789A CN106252234A CN 106252234 A CN106252234 A CN 106252234A CN 201610740789 A CN201610740789 A CN 201610740789A CN 106252234 A CN106252234 A CN 106252234A
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- insulating barrier
- layer
- manufacture method
- ion implanting
- nmos pass
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- 238000002360 preparation method Methods 0.000 title description 3
- 230000004888 barrier function Effects 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 19
- 238000009413 insulation Methods 0.000 claims description 2
- 208000027418 Wounds and injury Diseases 0.000 abstract description 3
- 230000006378 damage Effects 0.000 abstract description 3
- 208000014674 injury Diseases 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 35
- 150000002500 ions Chemical class 0.000 description 30
- 238000010586 diagram Methods 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- DNAUJKZXPLKYLD-UHFFFAOYSA-N alumane;molybdenum Chemical compound [AlH3].[Mo].[Mo] DNAUJKZXPLKYLD-UHFFFAOYSA-N 0.000 description 2
- HKBLLJHFVVWMTK-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti].[Ti] HKBLLJHFVVWMTK-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- CWYNVVGOOAEACU-UHFFFAOYSA-N Fe2+ Chemical compound [Fe+2] CWYNVVGOOAEACU-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000005622 photoelectricity Effects 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Abstract
The invention provides the manufacture method of a kind of nmos pass transistor, comprising: form light shield layer on substrate and cover the cushion of light shield layer；Form polysilicon layer on the buffer layer；Polysilicon layer includes pars intermedia, first end and the second end；First end and the second end are carried out ion implanting for the first time；First end is carried out second time ion implanting；Form the first insulating barrier covering polysilicon layer on the buffer layer；First insulating barrier is formed grid；First insulating barrier is formed the second insulating barrier covering grid；Form source electrode and drain electrode over the second dielectric；One of source electrode and two first ends contact, and drain and contact with another of two first ends.The present invention utilizes the flow behavior again of photoresistance to make N-type heavily doped region and N-type is lightly doped district, make ion implanting without pass through the first insulating barrier, reduce the injury to the first insulating barrier, so that the symmetry of N-type heavily doped region and the lightly doped symmetry of N-type are more preferably.
Description
Technical field
The present invention relates to the processing technology of MOS transistor, particularly to a kind of nmos pass transistor and preparation method thereof, CMOS
Transistor.
Background technology
Along with the evolution of photoelectricity Yu semiconductor technology, also drive the fluffy of flat faced display (Flat Panel Display)
The exhibition of breaking out, and in many flat faced displays, liquid crystal display (Liquid Crystal Display is called for short LCD) is because having
Many advantageous characteristic such as high spatial utilization ratio, low consumpting power, radiationless and low EMI, it has also become the master in market
Stream.
At present, widely used as the switch element of LCD is amorphous silicon membrane audion (a-Si TFT), but a-Si
TFT LCD requires still to be restricted meeting slim, light weight, high-fineness, high brightness, high reliability, low-power consumption etc..Low temperature is many
Compared with crystal silicon (Lower Temperature Polycrystal Silicon, LTPS) TFT LCD and a-Si TFT LCD,
Meet above-mentioned requirements aspect, there is clear superiority.
But in current LTPS technology, need to carry out ion implanting (Implant processing procedure) to improve mobility.?
In LTPS processing procedure, need to carry out NCD (channel doping), NP (N-type heavy doping), NM (N-type is lightly doped), PP (p-type heavy doping) etc.
Repeatedly ion implanting (Implant) processes, thus form channel doping district, N-type heavily doped region, N-type are lightly doped district, p-type is heavily doped
Miscellaneous district.But, in the LTPS processing procedure of present technology, need during ion implanting to make ion pass gate insulator, so
Gate insulator can be damaged, and the symmetry of the N-type heavily doped region formed and N-type that the symmetry in district is lightly doped is the most deficient
Good.
Summary of the invention
For solving above-mentioned technical problem, it is an object of the invention to provide the manufacture method of a kind of nmos pass transistor, its
Including: on substrate, form light shield layer and cover the cushion of described light shield layer；Described cushion is formed polysilicon layer；
Described polysilicon layer includes pars intermedia, the first end laying respectively at described pars intermedia both sides and is positioned at described pars intermedia and institute
State the second end between first end；Described first end and described the second end are carried out ion implanting for the first time；To institute
State first end and carry out second time ion implanting；Described cushion is formed the first insulating barrier covering described polysilicon layer；
Described first insulating barrier is formed grid；Described first insulating barrier is formed the second insulating barrier covering described grid；?
Source electrode and drain electrode is formed on described second insulating barrier；Described source electrode runs through described second insulating barrier and described first insulating barrier and two
One of described first end contacts, and described drain electrode runs through the first end described in described second insulating barrier and described first insulating barrier and two
Another contact in portion.
Further, described first end and described the second end are carried out the concrete grammar bag of ion implanting for the first time
Include: form the photoresist layer covering described pars intermedia；Use the described first end that do not covered by described photoresist layer of N-type ion pair and
Described the second end carries out ion implanting.
Further, the concrete grammar that described first end carries out second time ion implanting includes: to described photoresist layer
Toast, make described photoresist layer deliquescing and flow to its both sides, thus covering the second end described in two；Use N-type ion pair
The described first end that described photoresist layer after not flowed by deliquescing covers carries out ion implanting again；Described photoresist layer is gone
Remove.
Further, described manufacture method farther includes: on described second insulating barrier formed cover described source electrode and
The flatness layer of described drain electrode；Through hole is formed, to expose described drain electrode in described flatness layer.
Another object of the present invention also resides in a kind of nmos pass transistor utilizing above-mentioned manufacture method to make of offer.
A further object of the present invention is again to provide a kind of CMOS transistor, by nmos pass transistor and PMOS transistor structure
Becoming, described nmos pass transistor is made up of above-mentioned manufacture method.
Beneficial effects of the present invention: compared with prior art, the manufacture method of the nmos pass transistor of the present invention, utilize photoresistance
(Reflow) characteristic that flows again make N-type heavily doped region and N-type district be lightly doped so that ion implanting is exhausted without pass through first
Edge layer, reduces the ion implanting injury to the first insulating barrier, and utilizes the flow behavior again of photoresistance so that N-type heavily doped region
Symmetry and the lightly doped symmetry of N-type more preferably.
Accompanying drawing explanation
By combining the following description that accompanying drawing is carried out, above and other aspect, feature and the advantage of embodiments of the invention
Will become clearer from, in accompanying drawing:
Fig. 1 is the phenomenon schematic diagram occurring after photoresistance is baked flowing again；
Fig. 2 a to Fig. 2 j is the flow chart of the manufacture method of nmos pass transistor according to an embodiment of the invention；
Fig. 3 a and Fig. 3 b shows the method flow diagram that first end and the second end carry out ion implanting for the first time；
Fig. 3 c to Fig. 3 e shows the method flow diagram that first end carries out second time ion implanting.
Detailed description of the invention
Hereinafter, with reference to the accompanying drawings to describe embodiments of the invention in detail.However, it is possible to come real in many different forms
Execute the present invention, and the present invention should not be construed as limited to the specific embodiment that illustrates here.On the contrary, it is provided that these are implemented
Example is to explain the principle of the present invention and actual application thereof, so that others skilled in the art are it will be appreciated that the present invention
Various embodiments and be suitable for the various amendments of specific intended application.In the accompanying drawings, identical label will be used for table all the time
Show identical element.
First the phenomenon of (Reflow) of occurring after being baked photoresistance flowing again illustrates.Fig. 1 is after photoresistance is baked
The phenomenon schematic diagram flowed again occurs.
With reference to Fig. 1, photoresistance has flow behavior again, when photoresistance there will be flow phenomenon again after being baked (Oven).This
It is because photoresistance to be made up of organic material, so the photoresistance being made up of organic material becomes after there will be first deliquescing in baking process
Hard process, and during deliquescing, photoresistance there will be flowing, and the live width (CD) of whole photoresistance can be made to become big.
Next the flow behavior again utilizing above-mentioned photoresistance is made low temperature polycrystalline silicon (Lower Temperature
Polycrystal Silicon, LTPS) thin film transistor (TFT) (Thin Film Transistor, TFT) is described in detail.?
In the description of the following examples, nmos pass transistor is used to illustrate as an example of low-temperature polysilicon film transistor.
Fig. 2 a to Fig. 2 j is the flow chart of the manufacture method of nmos pass transistor according to an embodiment of the invention.
First, with reference to Fig. 2 a, form light shield layer 101 on the substrate 100 and cover the cushion 102 of this light shield layer 101.
Here, cushion 102 can be the single layer structure formed by insulant, it is also possible to formed by least two insulant
Laminated construction.Such as, cushion 102 can be the SiN formed on the substrate 100 by pecvd processx/SiOxLaminated construction.
Substrate 100 can for example, one transparent glass substrate or resin substrate.Light shield layer 101 can be such as by ferrous matenial
Material is made, and the present invention is also not especially limited.
Then, with reference to Fig. 2 b, cushion 102 forms polysilicon layer 103.Here, the generation type of polysilicon layer 103
Can be for example the mode that sputters on the surface of cushion 102, form a non-crystalline silicon (a-Si) layer, then make amorphous with annealing way
Silicon layer recrystallization.
Further, in advance polysilicon layer 103 is divided into: pars intermedia 1031, lay respectively at the of pars intermedia 1031 both sides
One end 1032 and the second end between pars intermedia 1031 and each first end 1,032 1033, certain present invention is also
Not in this, as restriction.
Then, with reference to Fig. 2 c, first end 1032 and the second end 1033 are carried out ion implanting for the first time.
Fig. 3 a and Fig. 3 b shows the method flow diagram that first end and the second end carry out ion implanting for the first time.First
With initial reference to Fig. 3 a, form the photoresist layer PR covering pars intermedia 1031；Here, photoresist layer PR does not cover first end 1032 and second
End 1033.Referring next to Fig. 3 b, use first end 1032 and the second end that N-type ion pair do not covers by photoresist layer PR
1033 carry out ion implanting.Here, N-type ion can use phosphorus/arsenic (P/As) ion, but the present invention is not in this, as restriction.
Then, with reference to Fig. 2 d, first end 1032 is carried out second time ion implanting.
Fig. 3 c to Fig. 3 e shows the method flow diagram that first end carries out second time ion implanting.With reference first to figure
3c, toasts photoresist layer PR, makes photoresist layer PR deliquescing and flows to its both sides, thus covering the second end 1033.Then
With reference to Fig. 3 d, the first end 1032 that the photoresist layer PR after using N-type ion pair not flowed by deliquescing covers carries out ion again
Inject.Referring finally to Fig. 3 e, photoresist layer PR is removed.Here, N-type ion can use phosphorus/arsenic (P/As) ion, but the present invention is also
Not in this, as restriction.
So, through the step shown in Fig. 2 c and Fig. 2 d, first end 1032 becomes N-type heavily doped region, and the second end
1033 become N-type is lightly doped district.
Then, with reference to Fig. 2 e, cushion 102 forms the first insulating barrier 104 covering polysilicon layer 103.Here,
One insulating barrier 104 can be the single layer structure formed by insulant, it is also possible to be by folding that at least two insulant is formed
Rotating fields.Such as, the first insulating barrier 104 can be the SiN formed on cushion 102 by pecvd processx/SiOxLamination is tied
Structure.
Then, with reference to Fig. 2 f, the first insulating barrier 104 forms grid 105.Here, grid 105 can be for example molybdenum aluminum molybdenum
(MoAlMo) structure or titanium aluminum titanium (TiAlTi) structure.
Then, with reference to Fig. 2 g, the first insulating barrier 104 forms the second insulating barrier 106 covering grid 105.Here,
Two insulating barriers 106 can be the single layer structure formed by insulant, it is also possible to is by folding that at least two insulant is formed
Rotating fields.Such as, the second insulating barrier 106 can be the SiN formed on the first insulating barrier 104 by pecvd processx/SiOxLamination
Structure.
Then, with reference to Fig. 2 h, the second insulating barrier 106 forms source electrode 107 and drain electrode 108；It is exhausted that source electrode 107 runs through second
Edge layer 106 contacts with one of first end described in two 1032 after the first insulating barrier 104, and drain electrode 108 runs through the second insulating barrier
106 contact with another of first end described in two 1032 with after the first insulating barrier 104.Here, source electrode 107 and drain electrode 108 can
E.g. molybdenum aluminum molybdenum (MoAlMo) structure or titanium aluminum titanium (TiAlTi) structure.
When nmos pass transistor is applied to liquid crystal as low-temperature polysilicon film transistor according to an embodiment of the invention
When showing in device, the manufacture method of nmos pass transistor also includes the system shown by Fig. 2 i and Fig. 2 j according to an embodiment of the invention
Journey.
With continued reference to Fig. 2 i, the second insulating barrier 106 is formed and covers source electrode 107 and the flatness layer 109 of drain electrode 108.This
In, flatness layer 109 can use organic insulation to make.
Finally, with reference to Fig. 2 j, flatness layer 109 forms through hole 110, drain electrode 108 to be exposed.
So, when this nmos pass transistor is applied in liquid crystal display, can on flatness layer 109 formation of deposits pixel electricity
Pole, wherein, this pixel electrode is contacted with described drain electrode 108 by through hole 110.
Additionally, in a liquid crystal display, low-temperature polysilicon film transistor can also use CMOS (Complementary Metal Oxide Semiconductor) partly to lead
Body (CMOS) transistor, it is formed by nmos pass transistor and PMOS transistor.Formed CMOS transistor time, nmos pass transistor and
PMOS transistor can concurrently form, and the manufacture method of nmos pass transistor can use the nmos pass transistor shown in Fig. 2
Manufacture method.
In sum, the manufacture method of nmos pass transistor according to an embodiment of the invention, utilize flowing again of photoresistance
(Reflow) characteristic makes N-type heavily doped region and N-type is lightly doped district so that ion implanting, without pass through the first insulating barrier, subtracts
Few ion implanting injury to the first insulating barrier, and utilize the flow behavior again of photoresistance so that the symmetry of N-type heavily doped region
Symmetry lightly doped with N-type is more preferably.
Although illustrate and describing the present invention with reference to specific embodiment, but it should be appreciated by those skilled in the art that:
In the case of without departing from the spirit and scope of the present invention limited by claim and equivalent thereof, can carry out at this form and
Various changes in details.
Claims (6)
1. the manufacture method of a nmos pass transistor, it is characterised in that including:
Substrate is formed light shield layer and covers the cushion of described light shield layer；
Described cushion is formed polysilicon layer；Described polysilicon layer includes pars intermedia, lays respectively at described pars intermedia both sides
First end and the second end between described pars intermedia and described first end；
Described first end and described the second end are carried out ion implanting for the first time；
Described first end is carried out second time ion implanting；
Described cushion is formed the first insulating barrier covering described polysilicon layer；
Described first insulating barrier is formed grid；
Described first insulating barrier is formed the second insulating barrier covering described grid；
Described second insulating barrier is formed source electrode and drain electrode；Described source electrode runs through described second insulating barrier and described first insulation
Layer contacts with one of first end described in two, and described drain electrode runs through described in described second insulating barrier and described first insulating barrier and two
Another contact of first end.
Manufacture method the most according to claim 1, it is characterised in that described first end and described the second end are carried out
The concrete grammar of ion implanting includes for the first time:
Form the photoresist layer covering described pars intermedia；
The described first end and the described the second end that use N-type ion pair not covered by described photoresist layer carry out ion implanting.
Manufacture method the most according to claim 2, it is characterised in that described first end is carried out second time ion implanting
Concrete grammar include:
Described photoresist layer is toasted, makes described photoresist layer deliquescing and flow to its both sides, thus covering the second end described in two
Portion；
The described first end that described photoresist layer after using N-type ion pair not flowed by deliquescing covers carries out ion note again
Enter；
Described photoresist layer is removed.
4. according to the manufacture method described in any one of claims 1 to 3, it is characterised in that described manufacture method farther includes:
Described second insulating barrier is formed and covers described source electrode and the flatness layer of described drain electrode；
Through hole is formed, to expose described drain electrode in described flatness layer.
5. the nmos pass transistor that the manufacture method that a kind utilizes described in any one of claim 1 to 4 makes.
6. a CMOS transistor, is made up of nmos pass transistor and PMOS transistor, it is characterised in that described nmos pass transistor by
Manufacture method described in any one of Claims 1-4 is made.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610740789.3A CN106252234A (en) | 2016-08-26 | 2016-08-26 | Nmos pass transistor and preparation method thereof, CMOS transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610740789.3A CN106252234A (en) | 2016-08-26 | 2016-08-26 | Nmos pass transistor and preparation method thereof, CMOS transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106252234A true CN106252234A (en) | 2016-12-21 |
Family
ID=57596545
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610740789.3A Pending CN106252234A (en) | 2016-08-26 | 2016-08-26 | Nmos pass transistor and preparation method thereof, CMOS transistor |
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| Country | Link |
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| CN (1) | CN106252234A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018218712A1 (en) * | 2017-06-02 | 2018-12-06 | 武汉华星光电技术有限公司 | Low-temperature polysilicon tft substrate and manufacturing method therefor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4503601A (en) * | 1983-04-18 | 1985-03-12 | Ncr Corporation | Oxide trench structure for polysilicon gates and interconnects |
| US20020102785A1 (en) * | 2001-01-26 | 2002-08-01 | James Ho | Method for forming shallow junctions by increasing width of photoresist and using implanting through poly film |
| CN1525554A (en) * | 2003-02-26 | 2004-09-01 | 友达光电股份有限公司 | Method for producing low-temperature polysilicon thin film transistor |
| CN103165529A (en) * | 2013-02-20 | 2013-06-19 | 京东方科技集团股份有限公司 | Preparation method of array baseplate |
| CN105470197A (en) * | 2016-01-28 | 2016-04-06 | 武汉华星光电技术有限公司 | Production method of low temperature poly silicon array substrate |
-
2016
- 2016-08-26 CN CN201610740789.3A patent/CN106252234A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4503601A (en) * | 1983-04-18 | 1985-03-12 | Ncr Corporation | Oxide trench structure for polysilicon gates and interconnects |
| US20020102785A1 (en) * | 2001-01-26 | 2002-08-01 | James Ho | Method for forming shallow junctions by increasing width of photoresist and using implanting through poly film |
| CN1525554A (en) * | 2003-02-26 | 2004-09-01 | 友达光电股份有限公司 | Method for producing low-temperature polysilicon thin film transistor |
| CN103165529A (en) * | 2013-02-20 | 2013-06-19 | 京东方科技集团股份有限公司 | Preparation method of array baseplate |
| CN105470197A (en) * | 2016-01-28 | 2016-04-06 | 武汉华星光电技术有限公司 | Production method of low temperature poly silicon array substrate |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018218712A1 (en) * | 2017-06-02 | 2018-12-06 | 武汉华星光电技术有限公司 | Low-temperature polysilicon tft substrate and manufacturing method therefor |
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