CN106162318A - Time deinterleaving circuit and execution time deinterleaving processing method - Google Patents

Time deinterleaving circuit and execution time deinterleaving processing method Download PDF

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Publication number
CN106162318A
CN106162318A CN201510207854.1A CN201510207854A CN106162318A CN 106162318 A CN106162318 A CN 106162318A CN 201510207854 A CN201510207854 A CN 201510207854A CN 106162318 A CN106162318 A CN 106162318A
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memory
unit
time
memory module
units
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CN201510207854.1A
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Chinese (zh)
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王俊杰
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晨星半导体股份有限公司
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Publication of CN106162318A publication Critical patent/CN106162318A/en

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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41Structure of client; Structure of client peripherals
    • H04N21/426Characteristics of or Internal components of the client
    • H04N21/42607Characteristics of or Internal components of the client for processing the incoming bitstream
    • H04N21/42623Characteristics of or Internal components of the client for processing the incoming bitstream involving specific decryption arrangements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network, synchronizing decoder's clock; Client middleware
    • H04N21/438Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving MPEG packets from an IP network
    • H04N21/4385Multiplex stream processing, e.g. multiplex stream decrypting
    • H04N21/43853Multiplex stream processing, e.g. multiplex stream decrypting involving multiplex stream decryption
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00Television systems
    • H04N7/01Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0117Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
    • H04N7/012Conversion between an interlaced and a progressive signal

Abstract

The invention discloses a time deinterleaving circuit and execution time deinterleaving processing method, which is applied to a communication system and is used for carrying out time deinterleaving processing on an interleaved signal, and the interleaved signal comprises a plurality of units. The time deinterleaving circuit comprises a memory module, used for storing these units, wherein these units form a plurality of unit groups with a plurality of units as unit, and the reading and writing of the memory module uses a unit group as unit; and a temporary memory module, used for temporarily storing the parts of these units to arrange the output sequence of these units.

Description

时间解交错电路与执行时间解交错处理的方法 The method of performing time deinterleaving circuit and the processing time deinterleaver

技术领域 FIELD

[0001] 本发明是关于时间解交错的电路与方法,尤其是关于可以减少对系统存储器的存取次数的时间解交错的电路与方法。 [0001] The present invention relates to a circuit and method for time deinterleaving, in particular about the time the system can reduce the number of accesses to the memory circuit and the deinterleave method.

背景技术 Background technique

[0002] 一般而言,地面数位视讯广播(digital video broadcasting-Second Generation terrestrial, DVB-T2)的广播信号在发送之前会先将数据经过单元交错(Cell-interleaving, CI)运算及时间交错(Time-interleaving, TI)运算以尽可能降低传输过程中各种干扰对传输数据的影响,接收端才可以取得正确的传输数据,而信号接收端在接收信号后必须先经过时间解交错(Time de-interleaving)运算及单元解交错(Cell de-interleaving)运算才能将数据正确解码。 [0002] In general, terrestrial digital video broadcast (digital video broadcasting-Second Generation terrestrial, DVB-T2) before transmitting the broadcast signal via data will first interleaved unit (Cell-interleaving, CI) and the time-interleaved operation (Time -interleaving, TI) operation to minimize the interference during the transmission of various data transmission, the receiving end can obtain accurate transmission of data, and the signal receiving side must be elapsed time after deinterleaving the received signal (time de- interleaving) and the arithmetic unit deinterleaver (cell de-interleaving) to the arithmetic data correctly decoded. 请参阅图1,其是已知信号接收端的功能方块图。 Please refer to FIG. 1, which is a known signal functional block diagram of the receiving end. 信号接收端100包含调制解调电路(demodulator) 110、频率解交错(frequency de-interleaving)电路120、时间解交错电路130、单元解交错电路140、去映射(de-mapping)电路150以及解码电路160。 Signal receiving end 100 includes a modulation and demodulation circuit (demodulator) 110, a frequency deinterleaver (frequency de-interleaving) circuit 120, a time deinterleave circuit 130, a deinterleave circuit unit 140, demapper (de-mapping) circuit 150 and a decoder circuit 160. 输入信号为调制过后的信号(例如基于正交分频多工(orthogonal frequency division multiplexing, 0FDM)的正交振幅调制(quadrature amplitude modulation, QAM)信号),经过调制解调电路110处理后所得到的交错信号包含两个正交的分量(I、Q)及信号杂讯比(signal to noise ratio, SNR)等资讯, 之后经由频率解交错电路120、时间解交错电路130、单元解交错电路140的解交错运算后, 使该些资讯以正确的顺序重新排列,再经过去映射电路150的运算后还原成位元资讯,最后经由解码电路160的运算后(例如低密度奇偶检查(Low-density parity-check, LDPC) 及BCH解码)得到传输数据。 After the input signal is a modulated signal (e.g., quadrature amplitude modulation (quadrature amplitude modulation, QAM) signal based on an orthogonal frequency division multiplexing (orthogonal frequency division multiplexing, 0FDM)), the modulation and demodulation circuit 110 after treating the resulting interlace signal comprises two orthogonal components (I, Q) and the signal to noise ratio (signal to noise ratio, SNR) and other information, then via the frequency deinterleaving circuit 120, the time deinterleaving circuit 130, circuit 140 deinterleave unit after deinterleaving operation, so that the plurality of information rearranged in the correct order, then after reduction of the arithmetic circuit 150 to map information bits, and finally decoded by the arithmetic circuit 160 (e.g., a low density parity check (Low-density parity -check, LDPC) and BCH decoding) to obtain the transmission data.

[0003] 时间交错的运算是以一个TI区块为单位,每一个TI区块包含NFK个向前错误校正(forward error correction,以下简称FEC)区块,而每个FEC区块包含Neell个单元(cell)。 [0003] Time interleaving operation is a TI units of blocks, each block comprises a TI NFK a forward error correction (forward error correction, hereinafter FEC) blocks, and each block comprises FEC units Neell (cell). 假设一个TI区块包含4个FEC区块(N FEe= 4),每个FEC区块包含40个单元(1^=40),在传送端执行时间交错运算时,其动态随机存取存储器(dynamic random access memory, DRAM)的大小设定为Nr列及Nc栏,其中Nr为Ncell/5(此例中等于8),Nc 为NFECX5(此例中等于20)。 Suppose a TI FEC block comprises four blocks (N FEe = 4), each FEC block comprises 40 units (= 40 ^ 1), when the execution time of the transmitter staggered operation, which dynamic random access memory ( dynamic random access memory, DRAM) is set to the size of Nr and the column Nc columns, wherein Nr is Ncell / 5 (equal in this embodiment. 8), Nc is NFECX5 (equal to 20 in this example). 请参阅图2a及图2b,其是已知用于时间交错运算的存储器的配置图。 See Figures 2a and 2b, a memory which is a configuration diagram of a known time-interleaved operation. 存储器的大小为NrXNc个单元,每一格的数字代表所写入/读出(图2a为写入的顺序,图2b为读出的顺序)的存储器位置的顺序。 NrXNc size of the memory cells is, each cell numbers represent the write / read sequence (FIG. 2a is a sequential write, 2b is sequentially read out) memory location. 在此例中,存储器每次写入/读出的字组(word)大小等于一个单元的大小(例如都为32bits),在图2a的写入程序中,从左上角开始直向依序写入单元,写满一栏后再换至下一栏,而在图2b的读出程序中,从左上角开始横向依序读出单元,读完一列后再换下一列,若图2a中写入的地址顺序亦代表写入的单元的编号,则写入的单元的编号顺序为:〇、1、2、3、"·、79、80、"·、158、159,而读出的单元的编号顺序为:〇、8、16、24、"·、155、4、"·、151、159,因此达到将单元分散的效果。 In this embodiment, each memory block write / read (word) size equal to the size of a cell (e.g., are 32bits), the program is written in FIG. 2a, sequentially from the upper left corner writing portrait into the unit, and then change to a column filled with the next column, and read out the program of FIG. 2b, sequentially from the upper left corner transversely reading unit, a read after a replaced, if in FIG. 2a write number order unit number of the unit's address also represents the written order, write to: square, 1,2,3, "·, 79, 80," *, 158, 159, and readout unit the numbering sequence is: square, 8,16,24, "., 155,4,"., 151,159, thus achieving the effect of dispersing the cell.

[0004] 请参阅图3,其是已知信号接收端的时间解交错电路及单元解交错电路的功能方块图。 [0004] Referring to FIG 3, which is a functional block diagram of a known signal receiving end time deinterleaving means deinterleave circuit and the circuit. 时间解交错电路130包含DRAM 132、写入地址产生器134及读取地址产生器136。 Time deinterleaving circuit 130 comprises a DRAM 132, a write address generator 134 and read address generator 136. 藉由写入地址产生器134及读取地址产生器136的控制,写入ΤΙ区块的每个单元时从DRAM 132的左上角开始直向依序写入,满一栏后再换至下一栏,而读取时从DRAM 132的左上角开始横向依序读出,读完一列后再换下一列,以完成时间解交错运算,然而其栏与列的个数分别等于传送端的列与栏的个数,因此DRAM132的大小设计为NcXNr (如果以横向的顺序写入DRAM 132,而以直向的顺序读出,则DRAM 132的大小为NrXNc)。 When the read address generator 134 and by controlling the write address generator 136, written in each cell block beginning from the upper left ΤΙ DRAM 132 is sequentially written straight, and then change over to the next column a column, is started from the upper left lateral DRAM 132 is read out sequentially read, after reading a replaced one to complete the TDI operation, the column number of the column which is equal to the transmitting end, however columns the number of columns, is so sized DRAM132 NcXNr (if a write DRAM 132 in order transverse, and vertical readout order, the size of the DRAM 132 is NrXNc). 请参阅图4a及图4b, 其是已知用于时间解交错运算且存储器频宽与单元大小相同时的存储器读写位置的顺序。 See Figures 4a and 4b, which are known for time deinterleaving order of operations and the memory cell size with the bandwidth and the position of the read-write memory simultaneously. 同样的,每一格的数字代表所写入/读出(图4a为写入的顺序,图4b为读出的顺序)的存储器地址的顺序,而且DRAM 132每次写入/读出的字组大小同样等于一个单元的大小。 Similarly, each cell numbers represent the write / read sequence (FIG. 4a is a sequential write, 4b is sequentially read out) memory address, DRAM 132 and each write word / read Also a group size equal to the size of the unit. 因此在图4a的写入程序中,从左上角开始直向依序写入单元,写满一栏后再换至下一栏, 而在图4b的读出程序中,从左上角开始横向依序读出单元,读完一列后再换下一列。 Therefore, in FIG. 4a write procedure, sequentially from the upper left corner vertical writing unit, a column filled before shifting to the next column, and reads the program in FIG. 4b, by laterally from the upper left corner sequence reading unit, reading a replaced one after. DRAM 132所收到的单元编号的顺序即为单元交错后的顺序:0、8、16、24、"·、155、4、"·、151、159, 以图4a的顺序写入DRAM 132后,单元编号在DRAM 132中的排列正好与图4b所示的读取顺序的号码相同,因此从DRAM 132所读出的单元的编号顺序为:0、1、2、3、"·、79、80、…、 158、159,而完成时间解交错的运算(共需对DRAM 132写入/读取160+160 = 320次)。之后单元解交错电路140再以FEC区块为单位(单元编号0~39为第0个FEC区块、单元编号40~79为第1个FEC区块,以此类推),利用⑶I (Cell De-interleaving,单元解交错) 暂存器142 ( -般以SRAM实作)依据交换函数(permutation function)进行单元解交错的运算。 After 0,8,16,24, "., 155,4,"., 151,159, 132 in order to write DRAM of Figure 4a: the sequence is the sequence number of the unit DRAM cell 132 received interlace , cell number in the DRAM 132 are arranged in exactly the same order number reading shown in FIG. 4b, numbered sequentially from the DRAM 132 and therefore the read-out unit is: 0,1,2,3, "., 79, 80, ..., 158, 159, and the operation completion time deinterleaver (total of DRAM 132 on the writing / reading times 160 + 160 = 320). after deinterleaving circuit unit 140 and then to block FEC units (unit number 0 ~ 39 0 for the first FEC blocks, numbers 40 to 79 units of a first FEC block, and so on), using ⑶I (cell De-interleaving, deinterleaving means) 142 registers (- generally in SRAM implementation) means for deinterleaving operation according to the swap function (permutation function).

[0005] 为了适应系统单芯片(system on chip, SoC)设计的潮流,时间解交错电路130所使用的DRAM 132必须与系统的其他电路共用,然而因为DRAM 132的频宽有限,因此每个电路皆必须尽可能减少对DRAM 132的存取次数,才不致于拖累系统的效能。 [0005] In order to adapt the system on chip (system on chip, SoC) design flow, time deinterleaving DRAM 132 must be shared with other circuits and systems used by circuit 130, however, because of the limited bandwidth of DRAM 132, so each circuit all must minimize the number of accesses to the DRAM 132, and avoid dragging down system performance. 减少DRAM 132 存取次数的方法之一,便是增加其频宽,使每次读写的字组增大。 One way to reduce the number of accesses DRAM 132 methods, it is to increase the bandwidth of the reading and writing of each word increases. 假设DRAM 132的频宽变为原来的4倍(字组变为128bits,每次读写4个单元),存储器的配置虽不变(同样为20 X 8),但其写入/读出的地址顺序则会改变。 Suppose the bandwidth of DRAM 132 becomes 4 times the original (block becomes 128bits, 4 units each read and write), although the same configuration memory (for the same 20 X 8), but the writing / reading of the address the order will change. 请参阅图5a及图5b,其是已知用于时间解交错处理且存储器频宽为单元大小的4倍时存储器中单元的储存地址及读写顺序的一示意图。 See 5a and 5b, which is known for the de-interleave processing time and memory bandwidth is four times the size of the unit addresses stored in the read-write memory cell and a sequence of a schematic diagram. 直向的数字(0~159)代表单元的编号,横向的数字(图5a为0~39,图5b为0~ 159)代表写入/读取的顺序。 Straight numbers (0 to 159) represents the cell number, digital lateral (0 to 39 in FIG. 5a, FIG. 5b is 0 to 159) representative of sequential write / read. 图5a为写入DRAM 132的顺序,写入时同样从左上角开始直向依序写入字组,第0次写入时写入包含单元编号〇、8、16、24的字组,第1次写入时写入包含单元编号32、40、48、56的字组,以此类推,因此160个单元总共需要对DRAM 132进行40 次的写入操作;图5b为读取DRAM 132的顺序,读取时从左上角开始横向依序读取字组,但需以单元编号为〇、1、2、3、…的顺序读出单元,所以第0次读取包含单元编号0、8、16、24 的字组,但只取单元编号0使用,第1次读取包含单元编号1、9、17、25的字组,但只取单元编号1使用,以此类推,所以写入时的每个字组于读取时皆要被读取4次,40个字组共需读取160次,因此,以此方法对160个单元进行解交错处理共需对DRAM 132进行的写入/读取次数为40+160 = 200次。 Figure 5a is sequentially written in the DRAM 132, the same is written sequentially from the upper left corner vertical writing block, writing means comprising first writing 0:00 number 0, 8,16,24 word, the first 1 comprising a write-once block number writing unit 32,40,48,56, and so on, and therefore a total of 160 units to 40 times of the DRAM 132 for the write operation; FIG. 5b is a read of DRAM 132 sequence, beginning from the upper left lateral block read sequentially read, but the need to square unit number 2, 3, ... are sequentially read out of the unit, the unit comprising a reading zeroth number 0,8 , 16, 24 of the block, but only using the access unit number 0, the cell number read word group comprises a first sub-1,9,17,25, but only use one access unit number, and so on, the writing each block in the time to be read are read four times, total of 40 read word 160 times, thus, in this method for de-interleaving unit 160 of the total of the processing performed to write DRAM 132 / read frequency is 40 + 160 = 200 times. 请参阅图6a及图6b,其是已知用于时间解交错处理且存储器频宽为单元大小的4倍时存储器中单元的储存地址及读写顺序的另一示意图。 See Figures 6a and 6b, which are known for the de-interleave processing time and memory bandwidth is a schematic view of a further four times the size of the unit addresses stored in the read-write memory and a sequence of cells. 图6a为写入DRAM 132的顺序,在这个操作方法中,虽然每次传送4个单元的数据给DRAM 132,但只写入一个单元,也就是包含单元编号〇、8、16、24的字组分4次写入(对应写入次数第0次、 第1次、第2次、第3次),包含单元编号32、40、48、56的字组分4次写入(对应写入次数第4次、第5次、第6次、第7次),以此类推,所以40个字组分160次写入;图6b为读取DRAM 132的顺序,读取时则依所需的单元编号的顺序进行读取,因此第0次读取包含单元编号0、 1、2、3的字组,第1次读取包含单元编号4、5、6、7的字组,以此类推,160个单元共需读取40 次。 6a is sequentially written in the DRAM 132, in this method of operation, although the data of each transmission unit 4 to the DRAM 132, but only one cell is written, i.e. square comprising cell number, word 8,16,24 component 4 is written (the write count corresponding to the 0th, 1st, 2nd, 3rd), comprising a cell number four components 32,40,48,56 word write (writing the corresponding number 4th, 5th, 6th, 7th), and so on, so the word component 40 writes 160; Figure 6b is a sequential read of the DRAM 132, by reading the desired order number reading unit, thus comprises zeroth reading unit number 0, block 1, 2, 1st reading unit comprising 4,5,6,7 block number, in order analogy, unit 160 reads the total of 40 times. 因此以此方法对160个单元进行解交错处理共需对DRAM 132进行的写入/读取次数为160+40 = 200 次。 Thus in this method 160 for de-interleave processing units write to DRAM 132 for a total of / reading times 160 + 40 = 200 times.

[0006] 虽然提高DRAM的频宽(图5a/5b及图6a/6b的方法)可以减少对DRAM 132的写入或读取次数,但对于存储器使用频率高的系统,若能进一步减少进行时间解交错处理时对存储器的读写次数,有助提升系统的整体效能。 [0006] While increasing the bandwidth of the DRAM (and methods 6a / 6b of FIG. 5a / 5b FIG) can reduce the number of reads or writes to DRAM 132, but the memory system using a high frequency, if further reduce the time when deinterleave processing memory read and write times, help to enhance the overall system performance.

发明内容 SUMMARY

[0007] 鉴于先前技术的不足,本发明的一目的在于提供一种时间解交错电路及时间解交错的方法,以减少时间解交错程序对存储器的读写次数。 [0007] In view of the lack of prior art, an object of the present invention is to provide a method of time deinterleaving the time deinterleaving circuit and to reduce the time deinterleaver program memory read and write times.

[0008] 本发明揭示了一种时间解交错电路,位于一通信系统的信号接收端,用来对一交错信号进行时间解交错处理,该交错信号包含多个单元,该时间解交错电路包含:一存储器模块,用来储存该些单元,该些单元以多个单元为单位形成多个单元组,该存储器模块的读写是以一单元组为单位;以及一暂存存储器模块,自该存储器模块暂存该些单元的部分,以安排该些单兀的输出顺序。 [0008] The present invention discloses a signal receiving end of a time-deinterleaver circuit, is located in a communication system, an interlace signal used to time de-interleave processing, the interlace signal includes a plurality of units, the time deinterleaving circuit comprising: a memory module for storing the plurality of unit cells of the unit in a plurality of units forming a plurality of cell groups, the read-write memory module is based on a group of cell units; and a temporary memory module from the memory temporary storing section of the unit module, in order to arrange the output order of the plurality of single Wu.

[0009] 本发明另揭示了一种时间解交错电路,位于一通信系统的信号接收端,用来对一交错信号进行时间解交错处理,该交错信号包含多个单元,该时间解交错电路包含:一存储器模块,用来储存该些单元,该些单元以多个单元为单位形成多个单元组,该存储器模块的读写是以一单元组为单位;以及一暂存存储器模块,用来暂存欲写入至该存储器模块的该些单元的部分,以安排该些单元写入至该存储器模块的顺序。 [0009] The present invention also discloses a time deinterleaving circuit, located at the signal receiving end of a communications system, an interlace signal used to time de-interleave processing, the interlace signal includes a plurality of units, the time deinterleaving circuit comprising : a memory module for storing the plurality of unit cells of the unit in a plurality of units forming a plurality of cell groups, the read-write memory module is based on a group of cell units; and a temporary memory module, for temporary storing section of the unit is to be written to the memory module, to arrange the order of the unit is written to the memory module.

[0010] 本发明另揭示了一种时间解交错的方法,应用于一通信系统的一时间解交错电路,用来对一交错信号进行时间解交错处理,该交错信号包含多个单元,该时间解交错电路包含一存储器模块,该存储器模块的读写是以一单元组为单位,每一单元组包含多个单元, 该方法包含:将该交错信号的该些单元写入该存储器模块;以及自该存储器模块读取该些单元之后,选择性地暂存该些单元;其中,在该时间解交错处理的过程中,对同一单元组而言,对该存储器模块的写入操作及读取操作各为一次。 [0010] The present invention also discloses a method of time deinterleaving, applied to a communication system, a time deinterleaving circuit for time interlace signal to a de-interleave processing, the interlace signal includes a plurality of units, the time deinterleaving circuit comprises a memory module, the memory module is read a unit of cell groups, each cell group comprising a plurality of cells, the method comprising: interleaving the signals of the unit into the memory module; and since the read memory module of the unit, selectively temporary storage of the unit; wherein, during the time deinterleaving process, for the same cell group, the writing operation of the memory module and reading operation each time.

[0011] 本发明另揭示了一种时间解交错的方法,应用于一通信系统的一时间解交错电路,用来对一交错信号进行时间解交错处理,该交错信号包含多个单元,该时间解交错电路包含一存储器模块,该存储器模块的读写是以一单元组为单位,每一单元组包含多个单元, 该方法包含:于接收该交错信号的该些单元之后及将该些单元写入该存储器模块之前,选择性地暂存该些单元;选取该些暂存单元的部分以组成一单元组;将该单元组写入该存储器模块;以及自该存储器模块读取该单元组;其中,在该时间解交错处理的过程中,对该单元组而言,对该存储器模块的写入操作及读取操作各为一次。 [0011] The present invention also discloses a method of time deinterleaving, applied to a communication system, a time deinterleaving circuit for time interlace signal to a de-interleave processing, the interlace signal includes a plurality of units, the time deinterleaving circuit comprises a memory module, the memory module is read a unit of cell groups, each cell group comprising a plurality of cells, the method comprising: in the plurality of unit after receiving the signal and the interlace these units before writing to the memory module, selectively temporary storage of the unit; selecting the plurality of temporary storage units to form a portion of the cell group; the module into the memory cell group; and reading the memory cell group from the module ; wherein the de-interleave processing in the course of time, in terms of the cell group, the writing operation and the reading operation of the memory module each time.

[0012] 本发明的时间解交错电路及执行时间解交错运算的方法利用额外的暂存存储器来减少时间解交错程序对系统的主存储器的读写次数。 [0012] Time deinterleaver method of the present invention performs time deinterleaving circuit and operation with an additional temporary memory to reduce the number of times a program to read and write the time deinterleaving on the main memory system. 相较于已知技术,本发明中由同样单元所组成的单元组对主存储器的写入及读取次数各为一次,因此可以更有效地减少对系统的主存储器的读写次数,使系统效能获得提升。 Compared to the prior art, the present invention cell group composed of the same units of the number of reads and writes to main memory each time, it is possible to more effectively reduce the number of read and write main memory of the system, the system performance promoted.

[0013] 有关本发明的特征、实作与功效,兹配合附图作较佳实施例详细说明如下。 [0013] For feature of the present invention, implementation and efficacy, preferred embodiments accompanied with figures are hereby embodiment described in detail below.

附图说明 BRIEF DESCRIPTION

[0014] 图1为已知信号接收端的功能方块图; [0014] 1 signal receiving end is known a functional block diagram of FIG;

[0015] 图2a及图2b为已知用于时间交错处理的存储器的配置图; [0015] Figures 2a and 2b is a configuration diagram of a known time interleaving of memory;

[0016] 图3为已知信号接收端的时间解交错电路及单元解交错电路的功能方块图; [0016] FIG. 3 is a known signal receiving end functional block diagram of the time deinterleaver deinterleaving circuit and circuit means;

[0017] 图4a及图4b为已知用于时间解交错处理当存储器频宽与单元大小相同时的存储器读写位置的顺序; [0017] Figures 4a and 4b are known for time deinterleaving the sequence processing unit when the memory bandwidth and the same size of the memory reader position;

[0018] 图5a及图5b为已知用于时间解交错处理当存储器频宽为单元大小的4倍时存储器中单元的储存地址及读写顺序的一示意图; [0018] 5a and 5b are known for the time deinterleaving process when the memory is a schematic diagram of a bandwidth of four times the size of the storage units and write the memory address in a sequence of cells;

[0019] 图6a及图6b为已知用于时间解交错处理当存储器频宽为单元大小的4倍时存储器中单元的储存地址及读写顺序的另一示意图; [0019] Figures 6a and 6b are known for the time deinterleaving process when the memory bandwidth is a schematic view of another store address and read 4 times the unit size of the order of cells in the memory;

[0020] 图7为本发明时间解交错电路的一实施例的功能方块图; A functional block diagram of an embodiment of the [0020] present invention. FIG. 7 is the time deinterleaving circuit;

[0021] 图8a及图8b为本发明用于时间解交错处理当存储器频宽为单元大小的4倍时存储器714及存储器721中的单元编号及读写顺序的示意图。 [0021] FIG. 8a and FIG. 8b present invention for processing time deinterleaver memory bandwidth is four times the size of the unit number and the read-write memory unit 714 and a memory 721 as a sequence of schematic.

[0022] 图9a~图9d为本发明用于时间解交错处理当存储器频宽为单元大小的4倍时存储器714及存储器721中的存储器地址、单元编号及读写顺序的另一示意图; [0022] FIGS. 9a ~ 9d of the present invention FIG time for de-interleave processing and the memory 714 in the address memory 721, the memory cell number and the other a schematic diagram of the memory read bandwidth of the order of 4 times the cell size when;

[0023] 图10a~图10d为本发明用于时间解交错处理当存储器频宽为单元大小的2倍时存储器714及存储器721中的存储器地址、单元编号及读写顺序的示意图; [0023] FIGS. 10a ~ 10d of the present invention, FIG time for de-interleave processing when the memory bandwidth is twice the size of the memory cell address memory 714 and the memory 721, the order of cell number, and a schematic view when reading and writing;

[0024] 图11a~图lid为本发明用于时间解交错处理当存储器频宽为单元大小的8倍时存储器714及存储器721中的存储器地址、单元编号及读写顺序的示意图; [0024] FIGS. 11a ~ FIG lid present time deinterleaving process when the memory address of the memory bandwidth is 8 times the cell size of memory 714 and a memory 721, and the unit number of sequential read and write a schematic invention;

[0025] 图12a及图12b为本发明在不同LDPC区块长度及不同调制模式下的存储器的使用量及存储器的读写次数; [0025] FIG. 12a and FIG. 12b read and write times in the present invention is used in an amount different LDPC block length and different modulation modes of the memory and a memory;

[0026] 图13为本发明时间解交错电路的另一实施例的功能方块图; A functional block diagram of another [0026] 13 of the present invention, FIG time deinterleaving circuit embodiment;

[0027] 图14a及图14b为其本发明用于时间解交错处理当存储器频宽为单元大小的4倍时存储器1314及存储器1321中的单元编号及读写顺序的一示意图。 [0027] FIGS. 14a and 14b according to the present invention for processing a time when the memory bandwidth is four times the size of the unit number and the read-write memory unit 1314 and the memory 1321 in the order of a schematic deinterleaver.

[0028] 图15a~图15d为本发明用于时间解交错处理当存储器频宽为单元大小的4倍时存储器1314及存储器1321中的存储器地址、单元编号及读写顺序的另一示意图; [0028] FIGS. 15a ~ 15d of the present invention, FIG time for de-interleave processing and a memory address 1314 of the memory 1321, the memory cell number and the other a schematic diagram of the memory read bandwidth of the order of 4 times the cell size when;

[0029] 图16a~图16d为本发明用于时间解交错处理当存储器频宽为单元大小的2倍时存储器1314及存储器1321中的存储器地址、单元编号及读写顺序的示意图; [0029] FIGS. 16a ~ 16d of the present invention, FIG time for de-interleave processing when the memory bandwidth is twice the size of the memory address of the memory unit 1314 and the memory 1321, the order of cell number, and a schematic view when reading and writing;

[0030] 图17a~图17d为本发明用于时间解交错处理当存储器频宽为单元大小的8倍时存储器1314及存储器1321中的存储器地址、单元编号及读写顺序的示意图; [0030] FIGS. 17a ~ 17d of the present invention, FIG time for de-interleave processing bandwidth of the memory address of the memory cell size is 8 times the memory 1314 and the memory 1321, the order of cell number, and a schematic view when reading and writing;

[0031] 图18a及图18b为本发明在不同LDPC区块长度及不同调制模式下的存储器的使用量及存储器的读写次数; [0031] FIG. 18a and FIG. 18b read and write times in the present invention is used in an amount different LDPC block length and different modulation modes of the memory and a memory;

[0032] 图19为本发明的时间解交错的方法的一实施例的流程图;以及 A flowchart of an embodiment [0032] FIG. 19 of the present invention the time deinterleaving process; and

[0033] 图20为本发明的时间解交错的方法的另一实施例的流程图。 A flowchart of another embodiment of Time [0033] FIG. 20 of the present invention a method of de-interleaving embodiment.

[0034] 符号说明 [0034] Description of Symbols

[0035] 100 :信号接收端 [0035] 100: signal receiving end

[0036] 110:调制解调电路 [0036] 110: modulation and demodulation circuit

[0037] 120 :频率解交错电路 [0037] 120: frequency deinterleaving circuit

[0038] 130 :时间解交错电路 [0038] 130: time deinterleaving circuit

[0039] 140 :单元解交错电路 [0039] 140: deinterleave unit circuit

[0040] 150 :去映射电路 [0040] 150: demapping circuit

[0041] 160:解码电路 [0041] 160: decoding circuit

[0042] 132 :动态随机存取存储器 [0042] 132: a dynamic random access memory

[0043] 134、713、1313 :写入地址产生器 [0043] 134,713,1313: a write address generator

[0044] 136、715、1315 :读取地址产生器 [0044] 136,715,1315: read address generator

[0045] 142 :CDI 暂存器 [0045] 142: CDI register

[0046] 700、1300 :时间解交错电路 [0046] 700,1300: time deinterleaving circuit

[0047] 710、1310 :储存电路 [0047] 710,1310: Storage circuit

[0048] 711、716、1311 :缓存单元 [0048] 711,716,1311: buffer unit

[0049] 712、1312 :存储器模块 [0049] 712,1312: a memory module

[0050] 714、721、1314、1321 :存储器 [0050] 714,721,1314,1321: a memory

[0051] 720、1320 :暂存存储器模块 [0051] 720,1320: temporary memory module

[0052] 722、1322 :地址产生器 [0052] 722,1322: Address generator

[0053] 73〇、133〇:选择单元 [0053] 73〇, 133〇: selection means

[0054] S1910 ~S1930、S2010 ~S2050 :步骤 [0054] S1910 ~ S1930, S2010 ~ S2050: step

具体实施方式 Detailed ways

[0055] 以下说明内容的技术用语是参照本技术领域的习惯用语,如本说明书对部分用语有加以说明或定义,该部分用语的解释是以本说明书的说明或定义为准。 [0055] The following description with reference to the contents of technical terms idiom in the art, as will be described in this specification or with a portion defined terms, term explanation is based on the portion of this specification, illustrate subject or definition.

[0056] 本发明揭露内容包含时间解交错电路及时间解交错的方法,能够减少时间解交错程序对存储器的读写次数。 [0056] SUMMARY The present invention discloses a method comprising a time deinterleaver deinterleaving circuit and time, it is possible to reduce the time deinterleaver program memory read and write times. 在实施为可能的前提下,本技术领域具有通常知识者能够依本说明书的揭示内容来选择等效的元件或步骤来实现本发明,亦即本发明的实施并不限于后叙的实施例。 In a possible embodiment as a premise, in the art having ordinary knowledge disclosure under this specification can be selected to equivalent elements or steps to implement the invention, i.e. the embodiment of the present invention is not limited to the embodiments after the classification. 由于本发明的时间解交错电路所包含的部分元件单独而言可能为已知元件, 因此在不影响该装置发明的充分揭示露及可实施性的前提下,以下说明对于已知元件的细节将予以节略。 Due to the time deinterleaver of the present invention some of the elements included in the circuit may be known in terms of a single element, and therefore does not affect the invention so fully reveal the device is exposed and may be the premise of the embodiment, the following description will detail the known elements be abridged. 此外,本发明的时间解交错的方法可藉由本发明的时间解交错电路或其等效装置来执行,在不影响该方法发明的充分揭示及可实施性的前提下,以下方法发明的说明将着重于步骤内容而非硬件。 Further, the time deinterleaver of the present invention by the method of the present invention, the time deinterleaving apparatus to perform a circuit or its equivalent, without affecting the process of the invention may be fully disclosed and embodiments of the premise, the following method of the invention will be described focus on the steps of the content rather than hardware.

[0057] 请参阅图7,其是本发明时间解交错电路的一实施例的功能方块图。 [0057] Referring to FIG 7, which is a functional block diagram of an embodiment of the present invention, the time deinterleaving circuit. 时间解交错电路700包含储存电路710、暂存存储器模块720以及选择单元730。 Time deinterleaving circuit 700 comprises a storage circuit 710, temporary memory module 720 and a selection unit 730. 储存电路710包含缓存单元711、存储器模块712以及缓存单元716。 Circuit 710 comprises a buffer storage unit 711, a memory module 712 and a buffer unit 716. 在此实施例中,存储器模块712的频宽为w个位元(bit)(亦即每次读写的字组为w个位元),而一个单元的大小为c个位元,当缓存单元711(例如是先进先出暂存器)储存w/c个单元(w个元位)后,再一并写入存储器模块712的存储器714 ;同理,从存储器模块712读出的字组也先暂存至缓存单元716 (例如是先进先出暂存器),之后再以单元为单位输出至暂存存储器模块720及选择单元730。 Embodiment, the memory module 712 to the bandwidth of w bits (bit) in this embodiment (i.e., each block is read w bytes), and the size of a cell is c bytes, when the cache after the unit 711 (e.g., a FIFO register) to store w / c cells (w meta position), and then collectively written into the memory module 712 of memory 714; Likewise, the module 712 is read from the memory block temporary storage unit 716 to the first while the cache (e.g., a first in first out register), then a unit basis and then outputted to the temporary memory module 720 and the selection unit 730. 存储器模块712包含写入地址产生器713及读取地址产生器715,分别用来对存储器714的写入及读取操作时产生目标存储器地址;同理,暂存存储器模块720包含地址产生器722, 用来产生存储器721的读写地址。 The memory module 712 includes a write address generator 713 and read address generator 715, respectively, for generating a target memory address for the memory 714 of the write and read operations; Similarly, memory module 720 contains the temporary address generator 722 for generating the read address memory 721. 在一个较佳的实施例中,存储器714为DRAM,存储器721 为静态随机存取存储器(static random access memory, SRAM)。 In a preferred embodiment, the memory 714 is a DRAM, the memory 721 is a static random access memory (static random access memory, SRAM). 选择单元730选择性地以储存电路710的直接输出或是以暂存存储器模块720的暂存数据作为时间解交错电路700 的输出。 The selection unit 730 to selectively direct the output of the storage circuit 710 or to temporary memory module 720 temporarily stores data as a time deinterleaving circuit 700 output.

[0058] 请参阅图8a,其是本发明用于时间解交错处理且存储器频宽为单元大小的4倍时存储器714中的单元编号及写入顺序的一示意图。 [0058] Referring to FIG 8a, the time for which the present invention is a de-interleave processing and the memory bandwidth is a schematic view of a cell number and write the memory 714 in the order of 4 times the cell size. 同样的,直向的号码代表单元编号(0~ 159),横向的数字(0~39)为写入存储器714的顺序。 Similarly, the number represents the vertical unit number (0 to 159), transverse numbers (0 to 39) is sequentially written into the memory 714. 160个单元分布在20列及8栏,写入时以一个单元组为单位,从左上角开始直向依序写入单元组,写满一栏后再换至下一栏。 160 units distributed in columns 8 and 20, to a group of cell units when writing starts sequentially from the upper left vertical writing unit group, a filled column before shifting to the next column. 此实施例中一个单元组(即一个字组)包含4个单元,160个单元共被分为40个单元组,所以总共需要40次的写入操作。 Embodiment a cell group (i.e., a block) in this embodiment comprises four units, totaling 160 units 40 units into groups, so a total of 40 write operation. 请参阅图8b,其是本发明用于时间解交错处理且存储器频宽为单元大小的4倍时存储器714及存储器721中的单元编号及读取顺序的一示意图。 See FIG. 8b, the time for which the present invention is a de-interleave processing and the memory bandwidth is a schematic view of a memory 714, and reading order, and the cell number memory 721 is 4 times the cell size. 单元自存储器714读出时同样以一个单元组为单位,因此160个单元需要40次的读取操作, 但读取的顺序为从左上角开始横向依序读取单元组,读完一列后再换至下一列。 From the memory unit to the same cell group is a readout unit 714, so 160 units require 40 read operations, but the sequential read is sequentially read unit starts laterally from upper left group, and then read a change to the next column. 第0次读取的单元编号为〇、8、16、24(如图中斜线区块所示的单元组),此单元组先暂存在缓存单元716 (未绘示),缓存单元716以一个单元大小为单位输出数据,输出的单元部分进到暂存存储器模块720的存储器721,部分直接输出给选择单元730。 Cell number is read 0th billion, 8,16,24 (cell group depicted by the hatched blocks in FIG.), The first cell group 716 is temporarily stored in the cache unit (not shown), the buffer unit 716 to a unit cell size of the output data, the output unit portion 721 into the temporary memory to the memory module 720, the part 730 directly outputs to the selection unit. 由图可见,在第0次的读取, 编号为〇的单元直接输出给选择单元730,其他编号的单元则写入存储器721的第一列;同理,在第1次的读取中,编号为1的单元直接输出给选择单元730,其他编号的单元(9、17、 25)则写入存储器721的第2列;以此类推。 Seen, the 0th reading, number of square unit 730 directly outputs to the selection unit, the other unit number is written in the memory 721 of the first column; Similarly, in the reading of the first time, No. 1 unit is directly outputted to the selection unit 730, a number of other units (9, 17, 25) is written into the memory of the second column 721; and so on. 待第7次读取后(此时编号为7的单元已直接输出给选择单元730,其他编号的单元(15、23、31)则写入存储器721的第8列),选择单元130选择从存储器721输出暂存的单元(输出的顺序为单元编号8、9、10、11、…、15、16、 17…、30、31),并且连续输出24个后(即输出存储器721中的所有暂存单元),于接下来的对存储器714的读取操作中,再继续选择以缓存单元716的部分输出直接作为时间解交错电路700的输出,而其他未直接输出的部分则暂存至存储器721。 After reading the seventh (case No. 7 has direct output means to the selection unit 730, a number of other units (15,23,31) is written to the first memory 8 721), the selection unit 130 selects from after all buffered output of the memory unit 721 (cell number is sequentially output 8,9,10,11, ..., 15, 16, ... 17, 30, 31), and continuous output 24 (i.e., the output of the memory 721 temporary storage unit), the next read operation in the memory 714, and then continue to select the portion of the output buffer unit 716 as a time deinterleaving circuit 700 directly outputs, while the other part is not directly output to the temporary memory 721. 上述的操作将一直重复直到将存储器714中的所有单元读取完毕,时间解交错电路700所输出的单元顺序即为解交错处理后的结果。 The above operation will be repeated until all of the memory unit 714 has been read, the result of the time deinterleaving unit sequentially output circuit 700 is the deinterleave process. 综上所述,在本实施例中,藉由存储器721的辅助,可安排或改变该些单元的输出顺序,对同一个单元组而言,只需对存储器714进行各一次的写入操作及读取操作,即可完成解交错处理。 As described above, in the present embodiment, by secondary memory 721, or may be arranged to change the order of the plurality of output units, for a same cell group, the memory 714 only once each write operation and a read operation to complete the de-interleave processing. 所以本实施例的时间解交错电路700只需对存储器714总共进行40+40 = 80次的读写操作,相较于已知技术大幅减少对存储器714的读写次数。 Therefore, the present embodiment is time deinterleaver circuit 700 to memory 714 for only 40 + 40 = 80 times in total read and write operations, compared with the prior art greatly reducing the number of read-write memory 714.

[0059] 以下将进一步以不同的单元个数(64个)及频宽与单元大小的比值(w/c)来说明本发明对存储器714及721进行读写操作的细节。 [0059] The following further different number of cells (64) and the ratio of the bandwidth and unit size (w / c) of the present invention will be described on the details of memory 714 and 721 for read and write operations. 请参阅图9a、图%、图9c及图9d,其是本发明用于时间解交错处理且存储器频宽为单元大小的4倍时存储器714及存储器721中的存储器地址、单元编号及读写顺序的另一示意图。 Please refer to FIG. 9a,%, FIG. 9c and FIG. 9D, the present invention which is the time for de-interleave processing and the memory bandwidth is four times the size of the memory cell address memory 714 and the memory 721, and read-write unit number another procedure of FIG. 图9a为存储器714的地址编号,共有16个(0~15)地址,每个地址可以写入一个单元组(包含4个单元)。 9a is a memory address number 714, a total of 16 (0 to 15) addresses, each address can be written to a cell group (containing 4 units). 图9b为写入存储器714的顺序,从左上角开始横向依序写入单元组,写满一列后再换至下一列,写入地址产生器713遵循以下的规则产生地址: Figure 9b is a sequential write memory 714, beginning from the upper left lateral writing unit group sequentially, and then filled a change to the next column, write address generator 713 generates addresses follow the following rules:

[0060] [0060]

Figure CN106162318AD00091

[0063] WR^ C.XN.+RJ [0063] WR ^ C.XN. + RJ

Figure CN106162318AD00101

Figure CN106162318AD00102

[0064] 其中i代表缓存单元711依序输出的单元组的编号, 个单元组(除数4代表一个字组包含4个单元),mod为取余数的运算子,div为取商的运算子,1民为写入的地址,因此写入地址及写入的内容如下: [0064] wherein the numbering unit group i represents the buffer unit 711 sequentially output cell groups (divisor 4 represents a block contains 4 units), MOD to take the remainder of the operator, div is taken's operator, 1 Min address written, writing content and address written as follows:

[0065] 第0次在存储器地址0写入包含编号{0、8、16、24}等单元的单元组; [0065] including a writing zeroth {0,8,16,24} No other set of cells in a memory cell address 0;

[0066] 第1次在存储器地址8写入包含编号{32、40、48、56}等单元的单元组; [0066] The first number comprises a cell group like {32,40,48,56} unit 8 writes the address in the memory;

[0067] 第2次在存储器地址1写入包含编号{1、9、17、25}等单元的单元组; [0067] The second number comprises a cell group {1,9,17,25}, etc. in the memory cell 1 write address;

[0068] … [0068] ...

[0069] 第14次在存储器地址7写入包含编号{7、15、23、31}等单元的单元组; [0069] The 14th {7,15,23,31} contains the number of cells in the cell group like the memory write address 7;

[0070] 第15次在存储器地址15写入包含编号{39、47、55、63}等单元的单元组。 [0070] 15 {39,47,55,63} contains the number of times other set of cells in the memory cell 15 to write address.

[0071] 图9c为读取存储器714的顺序,从左上角开始直向依序读取单元组,读完一栏后再换至下一栏,读取地址产生器715遵循以下的规则产生地址: [0071] Figure 9c is a sequence of reading the memory 714, sequentially read straight from the upper left corner cell group, and then for reading a column to the next column, the read address generator 715 generates addresses follow the following rules :

[0072] [0072]

Figure CN106162318AD00103

[0073] 0;= i div Nr [0073] 0; = i div Nr

[0074] Rx= i mod Nr [0074] Rx = i mod Nr

[0075] RD,= C.XN.+R^ i} [0075] RD, = C.XN. + R ^ i}

[0076] 为读取的地址,因此读取地址及读取的内容如下: [0076] The read address, the read address and the contents thus read as follows:

[0077] 第0次在存储器地址0读取包含编号{0、8、16、24}的单元组,编号为0的单元直接输出,编号8、16、24的单元暂存至存储器721 ; Cell group [0077] 0th number contained in the memory address reading 0 {0,8,16,24}, the number of the unit directly outputs 0, 8,16,24 number to the memory unit 721 temporarily stores;

[0078] 第1次在存储器地址1读取包含编号{1、9、17、25}的单元组,编号为1的单元直接输出,编号9、17、25的单元暂存至存储器721 ; [0078] The first memory read address contained in a number of cell group {1,9,17,25}, direct output unit number 1, 9,17,25 number to the memory unit 721 temporarily stores;

[0079] 第2次在存储器地址2读取包含编号{2、10、18、26}的单元组,编号为2的单元直接输出,编号10、18、26的单元暂存至存储器721 ; Cell group [0079] The second number contained in the read memory address {2,10,18,26} 2, the direct output unit number 2, number 10,18,26 to the memory unit 721 temporarily stores;

[0080] … [0080] ...

[0081] 第14次在存储器地址14读取包含编号{38、46、54、62}的单元组,编号为38的单元直接输出,编号46、54、62的单元暂存至存储器721 ; Cell group [0081] 14 comprises a number of memory addresses in the read {38,46,54,62} 14, the number of unit 38 is directly output, the units 46,54,62 temporary number to the memory 721;

[0082] 第15次在存储器地址15读取包含编号{39、47、55、63}的单元组,编号为39的单元直接输出,编号47、55、63的单元暂存至存储器721。 [0082] The 15th memory address contained in the read ID 15} {39,47,55,63 cell group, numbered direct output unit 39, temporary numbers 47,55,63 to the memory unit 721.

[0083] 存储器721可以同时储存 [0083] The memory 721 may store at the same time

Figure CN106162318AD00104

个单元(w代表一个字组的数据量,c代表一个单元的数据量),本实施例w/c = 4,因此存储器721可同时储存NrX3( = 24)个单元。 Units (w indicates the amount of data of a block, the amount of data C representative of a unit), the present embodiment Example w / c = 4, so the memory 721 may be stored simultaneously NrX3 (= 24) cells. 图9d为存储器721的地址编号,共有24个(0~23)地址,写入时地址产生器722是遵循以下的规则产生地址: Figure 9d is a memory address number 721, a total of 24 (0 to 23) address, the write address generator 722 is address generation rules to follow:

[0084] for(i = 0 ;i < 3Nr;i = i+1) { [0084] for (i = 0; i <3Nr; i = i + 1) {

[0085] BufffR^ i [0085] BufffR ^ i

[0086] } [0086]}

[0087] 读取存储器721时地址产生器722遵循以下的规则产生地址: [0087] The memory 721 when the read address generator 722 generates addresses follow the following rules:

[0088] for(i = 0 ;i < 3Nr;i = i+1) { [0088] for (i = 0; i <3Nr; i = i + 1) {

Figure CN106162318AD00111

[0090] } [0090]}

[0091] 在此实施中,选择单元730每次选择从缓存单元716连续输出Nr ( = 8)个单元后, 便接着从存储器721连续输出(w/c-1) XNr个单元,也就是输出所有暂存于存储器721中的单元。 After [0091] In this embodiment, the selection unit 730 are sequentially output from each selected buffer unit 716 Nr (= 8) cells, and then they are sequentially output from the memory 721 (w / c-1) XNr units, i.e. the output all temporarily stored in the memory unit 721.

[0092] 请参阅图10a、图10b、图10c及图10d,其是本发明用于时间解交错处理当存储器频宽为单元大小的2倍时存储器714及存储器721中的存储器地址、单元编号及读写顺序的示意图。 [0092] Referring to FIG. 10a, FIG. 10b, FIG. 10c and FIG. 1Od, the time for which the present invention is a de-interleave processing when the memory bandwidth of the memory address size twice the unit memory 714 and a memory 721, cell number and a schematic diagram of the write sequence. 图l〇a为存储器714的地址编号,共有32个(0~31)地址,每个地址可以写入一个单元组(包含2个单元)。 FIG l〇a address number memory 714, a total of 32 (0 to 31) addresses, each address can be written to a cell group (containing 2 units). 图10b为写入存储器714的顺序,从左上角开始横向依序写入单元组,写满一列后再换至下一列,写入地址产生器713遵循以下的规则产生地址: 10b is a memory write sequence 714, is written sequentially from the upper left corner unit set laterally, a filled and then shifting to the next column, write address generator 713 generates addresses follow the following rules:

Figure CN106162318AD00112

[0097] } [0097]}

[0098] 其中i代表缓存单元711依序输出的单元组的编号, [0098] where i represents the cell group outputted from the buffer unit 711 sequentially numbered,

Figure CN106162318AD00113

个单元组(除数2代表一个字组包含2个单元)。 Cell groups (divisor represents a block comprising two units).

[0099] 图10c为读取存储器714的顺序,从左上角开始直向依序读取单元组,读完一栏后再换至下一栏,读取地址产生器715是遵循以下的规则产生地址: [0099] FIG 10c is a sequential read of the memory 714, sequentially from the upper left corner straight reading unit group, and then for reading a column to the next column, the read address generator 715 is to follow the rules produced address:

[0100] [0100]

Figure CN106162318AD00114

[0101] Ci = i div Nr [0101] Ci = i div Nr

[0102] R;= i mod N r [0102] R; = i mod N r

[0103] RD,= C.XN.+R^ i [0103] RD, = C.XN. + R ^ i

Figure CN106162318AD00115

[0104] } [0104]}

[0105] 存储器721可以同时储存个单元,本实施例w/c = 2,因此存储器721可同时储存Nr ( = 8)个单元。 [0105] The memory 721 may store units simultaneously, according to the present embodiment, w / c = 2, so the memory 721 may simultaneously store Nr (= 8) cells. 图10d为存储器721的地址编号,共有8个(0~7)地址,写入时地址产生器722遵循以下的规则产生地址: Figure 10d is a memory address number 721, a total of 8 (0 to 7) address, the write address generator 722 generates addresses follow the following rules:

[0106] for(i = 0 ;i < Nr;i = i+1) { [0106] for (i = 0; i <Nr; i = i + 1) {

[0107] BufffR^ i [0107] BufffR ^ i

[0108] } [0108]}

[0109] 读取存储器721时地址产生器722遵循以下的规则产生地址: [0109] The memory 721 when the read address generator 722 generates addresses follow the following rules:

[0110] for(i = 0 ;i < Nr;i = i+1) { [0110] for (i = 0; i <Nr; i = i + 1) {

[0111] BufRD^ i [0111] BufRD ^ i

[0112] } [0112]}

[0113] 在此实施中,选择单元730每次选择从缓存单元716连续输出Nr ( = 8)个单元后, 便接着从存储器721连续输出(w/c-1) X Nr个单元。 [0113] In this embodiment, the selection unit 730 are sequentially output from each selection after the buffer unit 716 Nr (= 8) cells, and then they are sequentially output from the memory 721 (w / c-1) X Nr cells.

[0114] 请参阅图11a、图11b、图11c及图lld,其本发明用于时间解交错处理且当存储器频宽为单元大小的8倍时存储器714及存储器721中的存储器地址、单元编号及读写顺序的示意图。 [0114] Referring to FIG. 11a, FIG. 11b, FIG. 11c and FIG LLD, which the present invention is the time for de-interleave processing and when the memory bandwidth is 8 times the size of the memory cell address memory 714 and the memory 721, cell number and a schematic diagram of the write sequence. 图11a为存储器714的地址编号,共有8个(0~7)地址,每个地址可以写入一个单元组(包含8个单元)。 Figure 11a is a memory address number 714, a total of 8 (0 to 7) addresses, each address can be written to a cell group (comprising eight units). 图lib为写入存储器714的顺序,写入地址产生器713遵循以下的规则产生地址: FIG lib sequence generator 714 is written into the memory, a write address 713 generates an address following rules:

Figure CN106162318AD00121

[0119] } [0119]}

[0120] 其中i代表缓存单元711依序输出的单元组的编号 [0120] where i represents the cell group outputted from the buffer unit 711 sequentially numbers

Figure CN106162318AD00122

个单元组(除数8代表一个字组包含8个单元)。 Cell groups (divisor 8 represents a block comprising 8 units).

[0121] 图11c为读取存储器714的顺序,读取地址产生器715遵循以下的规则产生地址: [0121] Figure 11c is a sequential access memory 714, read address generator 715 generates addresses follow the following rules:

[0122] [0122]

Figure CN106162318AD00123

[0123] C,= i div Nr [0123] C, = i div Nr

[0124] R;= i mod Nr [0124] R; = i mod Nr

[0125] RD,= C.XN.+R^ i [0125] RD, = C.XN. + R ^ i

[0126] } [0126]}

[0127] 存储器721可以同时储存 [0127] The memory 721 may store at the same time

Figure CN106162318AD00124

I个单元,本实施例w/c = 8,因此存储器721可同时储存NrX7( = 56)个单元。 I units, embodiments of the present embodiment w / c = 8, and therefore the memory 721 may be stored simultaneously NrX7 (= 56) cells. 图lid为存储器721的地址编号,共有56个(0~ 55)地址,写入时地址产生器722遵循以下的规则产生地址: FIG lid for the memory address number 721, a total of 56 (0 to 55) address, the write address generator 722 generates addresses follow the following rules:

[0128] f〇r(i = 0 ;i < 7Nr;i = i+1) { [0128] f〇r (i = 0; i <7Nr; i = i + 1) {

[0129] BufffR^ i [0129] BufffR ^ i

[0130] } [0130]}

[0131] 读取存储器721时地址产生器722遵循以下的规则产生地址: [0131] The memory 721 when the read address generator 722 generates addresses follow the following rules:

[0132] for(i = 0 ;i < 7Nr;i = i+1) { [0132] for (i = 0; i <7Nr; i = i + 1) {

Figure CN106162318AD00131

[0134] } [0134]}

[0135] 在此实施中,选择单元730选择从缓存单元716连续输出完Nr ( = 8)个单元后, 便接着从存储器721连续输出(w/c-1) X Nr个单元。 After [0135] In this embodiment, the selection unit 730 to select the output from the buffer unit continuously Ends 716 Nr (= 8) cells, and then they are sequentially output from the memory 721 (w / c-1) X Nr cells.

[0136] 请参阅图12a及图12b,其是本发明在不同LDPC区块长度及不同调制模式下的存储器的使用量及存储器的读写次数。 [0136] Referring to FIG 12a and FIG 12b, which is read at different times and different modulation LDPC block length patterns of memory usage and the memory of the present invention. 图12a显示不同的LDPC区块长度及不同的调制模式下存储器714与存储器721所需的大小,其中存储器721又细分为上面所讨论的三种态样(频宽大小为单元大小的2倍、4倍及8倍)。 LDPC blocks of different lengths and different modulation mode memory 714 and the memory 721 the desired size, wherein the memory 721 is subdivided into three aspects (bandwidth size unit size discussed above twice Figure 12a shows , 4-fold and 8-fold). 图12b显示不同的LDPC区块长度及不同的调制模式下存储器714的读写次数(同样细分为上述的三种态样),以及与已知存储器读写次数的比值。 Figure 12b shows different LDPC block length and the number of read-write memory 714 in different modulation modes (also subdivided into three aspects described above), and the ratio of the number of memory read and known. 结果显示,在同一种LDPC区块长度及同一种调制模式下,不论频宽大小与单元大小的倍数(w/c)为何,相较于习知的方法,皆能有效降低存储器的读写次数,尤其当w/ C愈大时,效果愈显著。 The results showed that, at the same LDPC block length and the same modulation mode, regardless of the size of a multiple of the bandwidth unit size (w / c) why the method compared to conventional, able to effectively reduce the number of read-write memory , especially when w / C greater, more remarkable effect.

[0137] 请参阅图13,其是本发明时间解交错电路的另一实施例的功能方块图。 [0137] Please refer to FIG. 13, which is a functional block diagram of the present invention, another time deinterleaver circuit embodiment. 时间解交错电路1300包含储存电路1310、暂存存储器模块1320以及选择单元1330。 Time deinterleaving circuit 1300 comprises a storage circuit 1310, and a temporary memory module 1320 selecting unit 1330. 储存电路1310 包含缓存单元1311以及存储器模块1312。 Storage circuit 1310 comprises a buffer module 1312 and a memory unit 1311. 当交错信号的各单元输入时间解交错电路1300 时,一部分会直接传送至选择单元1330,而一部分则储存至暂存存储器模块1320,选择单元1330用以决定选取直接输入的单元或是暂存的单元传送给储存电路1310的缓存单元1311。 When the input signal is interlace each unit time deinterleaving circuit 1300, a portion will be sent directly to the selection unit 1330, and a portion is stored to the temporary memory module 1320, selecting unit 1330 select means for determining a direct input or buffered unit to the buffer unit 1311 transmits the storage circuit 1310. 当缓存单元1311(例如是先进先出暂存器)储存w/c个单元(即一个单元组)后, 再一并写入存储器模块1312的存储器714。 When the buffer unit 1311 (e.g., a FIFO register) to store w / c cells (i.e. a cell group), and then written into the memory module memory 714 together 1312. 存储器模块1312包含写入地址产生器1313及读取地址产生器1315,分别用来对存储器1314的写入及读取操作时产生目标存储器地址; 同理,暂存存储器模块1320包含地址产生器1322,用来产生存储器1321的读写地址。 The memory module 1312 includes a write address generator 1313 and the read address generator 1315, respectively, for generating a target memory address during memory write and read operations 1314; Similarly, the memory module 1320 comprises a temporary address generator 1322 for generating the read address of the memory 1321. 在一个较佳的实施例中,存储器1314为DRAM,存储器1321为SRAM。 In a preferred embodiment, the memory 1314 is a DRAM, the memory 1321 is a SRAM.

[0138] 请参阅图14a,其是本发明用于时间解交错处理且当存储器频宽为单元大小的4 倍时存储器1314及存储器1321中的单元编号及写入顺序的一示意图。 [0138] Referring to FIG 14a, which is used in the present invention, the time when the de-interleave processing and the memory bandwidth is a schematic diagram of the write sequence unit number and 4 times the size of the memory unit 1314 and a memory 1321. 同样的,直向的数字(0~159)代表单元编号,横向的数字(0~39)为写入存储器1314的顺序。 Similarly, vertical numbers (0 to 159) represents the cell number, transverse numbers (0 to 39) is sequentially written in the memory 1314. 单元进入时间解交错电路1300的编号顺序为0、8、16、24、~、152、1、9、153、2、10、"*、154,依序暂存至存储器1321,待单元编号3进入时间解交错电路1300后,选择单元1330从存储器读取编号0、1、2的单元,并且连同编号3的单元传送给缓存单元1311 (未绘示),该4个单元在缓存单元1311构成一个单元组,之后写入存储器1314 ;同理,当单元编号11进入时间解交错电路1300后,选择单元1330从存储器读取编号8、9、10的单元,该4个单元在缓存单元1311构成一个单元组,之后写入存储器1314 ;其余类推。因此160个单元以每4个为一单元组的形式写入,共对存储器1314进行40次的写入操作。请参阅图14b,其是本发明用于时间解交错处理当存储器频宽为单元大小的4倍时存储器1314中单元编号及读取顺序的一示意图。读取的顺序如图中横向的数字所示,读取时同样以一个单元组为单 Unit 1300 enters the time deinterleaving circuit 0,8,16,24 numbered order, ~, 152,1,9,153,2,10, "*, 154, to the temporary memory 1321 sequentially until the unit number 3 after entering the time deinterleaving circuit 1300, selection unit 1330 reads the number from the memory unit 0,1,2 and together with the unit 3 transmits the number to the buffer unit 1311 (not shown), the four units in the buffer unit 1311 a cell group, then written into the memory 1314; Similarly, when the cell number 11 to enter time deinterleaving circuit 1300, selection unit 1330 reads the number from the memory unit 8, 9, the four units in the buffer unit 1311 a cell group, then written into the memory 1314; 160 units, the rest on thus written as every 4 to a unit group, a total of 1314 memory 40 write operation, please refer to FIG. 14b, which is present. time deinterleaver invention for processing when the memory bandwidth is a schematic view of a cell number and a reading order of 4 times the size of the memory unit 1314. as shown in numerical order transverse read, the reading at the same time a group is a single unit ,160个单元共需读取40次,而输出单元的编号依序为0、1、2、~、79、80、81、~158、159,达到时间解交错处理的效果。综上所述,在本实施例中,藉由存储器1321的辅助,对同一个单元组而言,只需对存储器1314进行各一次的写入操作及读取操作,即可完成解交错处理。所以本实施例的时间解交错电路1300只需对存储器1314进行40+40 = 80次的读写操作,相较于已知技术大幅减少对存储器1314的读写次数。 , Unit 160 reads the total of 40 times, the output unit sequentially numbered 0, 1, ~, 79,80,81, 158, 159 ~, de-interleave processing time to achieve the effect of conclusion in the present embodiment, by secondary memory 1321, a unit for the same group, only the memory 1314 of each write operation and a read operation to complete the de-interleave processing. Therefore, the present embodiment time deinterleaving circuit 1300 of the memory 1314 only 40 + 40 = 80 times the read and write operations, compared with the prior art to significantly reduce the number of read and write memory 1314.

[0139] 以下将进一步以不同的单元个数(64个)及频宽与单元大小的比值(w/c)来说明本发明对存储器1314及1321读写的操作细节。 [0139] The following further different number of cells (64) and the ratio of the bandwidth and unit size (w / c) to illustrate the operation details of a memory write 1314 and 1321 of the present invention. 请参阅图15a、图15b、图15c及图15d, 其是本发明用于时间解交错处理当存储器频宽为单元大小的4倍时存储器1314及存储器1321中的存储器地址、单元编号及读写顺序的另一示意图。 Referring to FIG. 15a, FIG. 15b, FIG. 15c and FIG. 15d, the time for which the present invention is a de-interleave processing when the memory bandwidth is four times the size of the memory unit 1314 and the memory 1321 is a memory address, read and write unit number another procedure of FIG. 图15a为将输入的单元暂存于存储器1321及将单元组写入存储器1314的顺序。 Figure 15a is temporarily stored in the input unit and sequentially written in the memory cell group 1314 in memory 1321. 图15b为存储器1321的地址编号,存储器1321可以同时储存 FIG 15b is a memory address number 1321, a memory 1321 can store simultaneously

Figure CN106162318AD00141

个单元,所以共有24个(0~23)地址,写入存储器1321时地址产生器1322是遵循以下的规则产生地址: Units, the total of 24 (0 to 23) addresses, written in the memory 1321 address generator 1322 generates addresses follow the following rules:

[0140] for(i = 0 ;i < 3Nc;i = i+1) { [0140] for (i = 0; i <3Nc; i = i + 1) {

[0141] BufER^ i [0141] BufER ^ i

[0142] } [0142]}

[0143] 读取存储器1321时地址产生器1322遵循以下的规则产生地址: [0143] The memory 1321 read address generator 1322 generates addresses follow the following rules:

[0144] for(i = 0 ;i < 3Nc;i = i+1) { [0144] for (i = 0; i <3Nc; i = i + 1) {

Figure CN106162318AD00142

[0146] } [0146]}

[0147] 图15c为存储器1314的地址编号,共有16个(0~15)地址,每个地址可以写入一个单元组(包含4个单元)。 [0147] Figure 15c is a memory address number 1314, a total of 16 (0 to 15) addresses, each address can be written to a cell group (containing 4 units). 写入存储器1314时(请参阅图15a)从左上角开始横向依序写入单元组,写满一列后再换至下一列,写入地址产生器1313遵循以下的规则产生地址: Writing the memory 1314 (see FIG. 15a) laterally from the upper left corner writing unit group sequentially, and then for a filled column to the next, following the write address generator 1313 generates addresses rules:

[0148] [0148]

Figure CN106162318AD00143

[0149] 0;= i mod Nc [0149] 0; = i mod Nc

[0150] Rx= i div Nc [0150] Rx = i div Nc

Figure CN106162318AD00144

[0152] } [0152]}

[0153] [0153]

Figure CN106162318AD00145

i个单元组(除数4代表一个字组包含4个单元),写入地址及写入的内容如下: i-th element groups (divisor 4 represents a block contains 4 units), the write address and write the contents as follows:

[0154] 第0次从存储器1321读取编号0、1、2的单元,连同直接输入的编号3的单元写入存储器1314的地址0 ; [0154] 1321 zeroth numbered 0,1,2 read from the memory cell, the write address of the memory unit 1314 is directly inputted together with the 0 number 3;

[0155] 第1次从存储器1321读取编号8、9、10的单元,连同直接输入的编号11的单元写入存储器1314的地址2 ; [0155] The first number 1321 read from the memory cell 8,9, 10, together with the number input unit 11 is directly written in the memory 1314 an address 2;

[0156] 第2次从存储器1321读取编号16、17、18的单元,连同直接输入的编号19的单元写入存储器1314的地址4 ; [0156] The second unit 1321 reads the number from the memory 16, 17, the memory write address 1314 together with the unit 4 is directly input number of 19;

[0157] … [0157] ...

[0158] 第14次从存储器1321读取编号52、53、54的单元,连同直接输入的编号55的单元写入存储器1314的地址13 ; [0158] The 14th number 1321 read from the memory unit 52, 53, together with the direct input unit 55 of the ID write address 13 of the memory 1314;

[0159] 第15次从存储器1321读取编号60、61、62的单元,连同直接输入的编号63的单元写入存储器1314的地址15。 [0159] The 15th numbered 60, 61 read from the memory unit 1321, together with the input unit is directly written in the memory address number 63 1314. 15.

[0160] 图15d为读取存储器1314的顺序,从左上角开始直向依序读取单元组,读完一栏后再换至下一栏,读取地址产生器1315遵循以下的规则产生地址: [0160] FIG. 15d is sequentially read from the memory 1314 are sequentially read from the upper left corner cell group portrait, and then for reading a column to the next column, the read address generator 1315 generates addresses follow the following rules :

Figure CN106162318AD00151

[0165] } [0165]}

[0166] 读取地址及读取的内容如下: [0166] The read address and read as follows:

[0167] 第0次在存储器地址0读取包含单元编号{0、1、2、3}的单元组; Cell group [0167] 0-th unit number contained in the memory read address 0 of {0,1,2,3};

[0168] 第1次在存储器地址1读取包含单元编号{4、5、6、7}的单元组; [0168] The first unit comprises a number of cell groups {4,5,6,7} in the read memory address 1;

[0169] 第2次在存储器地址2读取包含单元编号{8、9、10、11}的单元组; [0169] The second unit comprises a number of cell groups {8,9,10,11} in the read memory address 2;

[0170] ... [0170] ...

[0171] 第14次在存储器地址14读取包含单元编号{56、57、58、59}的单元组; [0171] The 14th comprises units 56,57, 58,59} {number of cell groups in the memory read address 14;

[0172] 第15次在存储器地址15读取包含单元编号{60、61、62、63}的单元组。 [0172] The 15th unit ID contained in the read address memory 15} {62, 63 of the cell group.

[0173] 请参阅图16a、图16b、图16c及图16d,其是本发明用于时间解交错处理当存储器频宽为单元大小的2倍时存储器1314及存储器1321中的存储器地址、单元编号及读写顺序的示意图。 [0173] Referring to FIG. 16a, FIG. 16b, Fig. 16c and 16d of FIG., The time for which the present invention is a de-interleave processing when the memory bandwidth of the memory address twice the size of the memory unit 1314 and a memory 1321, cell number and a schematic diagram of the write sequence. 图16a为将输入的单元暂存于存储器1321及将单元组写入存储器1314的顺序。 FIG 16a is temporarily stored in the input unit and sequentially written in the memory cell group 1314 in memory 1321. 图16b为存储器1321的地址编号,存储器1321可以同时储存iVc X ($_ 1)个单元, 共有8个(0~7)地址,写入存储器1321时地址产生器1322遵循以下的规则产生地址: FIG 16b is a memory address number 1321, a memory 1321 can store simultaneously iVc X ($ _ 1) units, a total of 8 (0 to 7) address, written in the memory 1321 address generator 1322 generates addresses follow the following rules:

[0174] for(i = 0 ;i < Nc;i = i+1) { [0174] for (i = 0; i <Nc; i = i + 1) {

[0175] BufffR^ i [0175] BufffR ^ i

[0176] } [0176]}

[0177] 读取存储器1321时地址产生器1322遵循以下的规则产生地址: [0177] The memory 1321 read address generator 1322 generates addresses follow the following rules:

[0178] for(i = 0 ;i < Nc;i = i+1) { [0178] for (i = 0; i <Nc; i = i + 1) {

[0179] BufRD^ i [0179] BufRD ^ i

[0180] } [0180]}

[0181] 图16c为存储器1314的地址编号,共有32个(0~31)地址,每个地址可以写入一个单元组(包含2个单元)。 [0181] FIG 16c is a memory address number 1314, a total of 32 (0 to 31) addresses, each address can be written to a cell group (containing 2 units). 写入存储器1314时(请参阅图16a)写入地址产生器1313 遵循以下的规则产生地址: Written in the memory 1314 (see FIG. 16a) the write address generator 1313 generates addresses follow the following rules:

[0182] [0182]

Figure CN106162318AD00152

[0183] 0;= i mod N c [0183] 0; = i mod N c

[0184] R;= i div Nc [0184] R; = i div Nc

Figure CN106162318AD00161

[0186] } [0186]}

[0187] [0187]

Figure CN106162318AD00162

个单元组(除数2代表一个字组包含2个单元)。 Cell groups (divisor represents a block comprising two units).

[0188] 图16d为读取存储器1314的顺序,从左上角开始直向依序读取单元组,读完一栏后再换至下一栏,读取地址产生器1315遵循以下的规则产生地址: [0188] Figure 16d is sequentially read from the memory 1314 are sequentially read from the upper left corner cell group portrait, and then for reading a column to the next column, the read address generator 1315 generates addresses follow the following rules :

Figure CN106162318AD00163

[0193] } [0193]}

[0194] 请参阅图17a、图17b、图17c及图17d,其是本发明用于时间解交错处理当存储器频宽为单元大小的8倍时存储器1314及存储器1321中的存储器地址、单元编号及读写顺序的示意图。 [0194] Referring to FIG. 17a, FIG. 17b, FIG. 17c and FIG. 17d, the time for which the present invention is a de-interleave processing when the memory address of the memory bandwidth is 8 times the cell size of the memory 1314 and the memory 1321, cell number and a schematic diagram of the write sequence. 图17a为将输入的单元暂存于存储器1321及将单元组写入存储器1314的顺序。 Figure 17a is temporarily stored in the input unit and sequentially written in the memory cell group 1314 in memory 1321. 图17b为存储器1321的地址编号,存储器1321可以同时储存 FIG 17b is a memory address number 1321, a memory 1321 can store simultaneously

Figure CN106162318AD00164

个单元, 共有56个(0~55)地址,写入存储器1321时地址产生器1322遵循以下的规则产生地址: Units, a total of 56 (0 to 55) addresses, written in the memory 1321 address generator 1322 generates addresses follow the following rules:

[0195] for(i = 0 ;i < 7Nc;i = i+1) { [0195] for (i = 0; i <7Nc; i = i + 1) {

[0196] BufffR^ i [0196] BufffR ^ i

[0197] } [0197]}

[0198] 读取存储器1321时地址产生器1322遵循以下的规则产生地址: [0198] The memory 1321 read address generator 1322 generates addresses follow the following rules:

[0199] for(i = 0 ;i < 7Nc;i = i+1) { [0199] for (i = 0; i <7Nc; i = i + 1) {

[0200] BufRD^ (i mod 7)XNc+(i div 7) [0200] BufRD ^ (i mod 7) XNc + (i div 7)

[0201] } [0201]}

[0202] 图17c为存储器1314的地址编号,共有8个(0~7)地址,每个地址可以写入一个单元组(包含8个单元)。 [0202] FIG 17c is a memory address number 1314, a total of 8 (0 to 7) addresses, each address can be written to a cell group (comprising eight units). 写入存储器1314时(请参阅图17a)写入地址产生器1313遵循以下的规则产生地址: Written in the memory 1314 (see Figure 17a) write address generator 1313 generates address the following rules:

Figure CN106162318AD00165

[0208] [0208]

Figure CN106162318AD00171

个单元组(除数8代表一个字组包含8个单元) Cell groups (divisor 8 represents a block comprising 8 units)

[0209] 图17d为读取存储器1314的顺序,读取地址产生器1315遵循以下的规则产生地址: [0209] Figure 17d is a sequential access memory 1314, read address generator 1315 generates addresses follow the following rules:

Figure CN106162318AD00172

[0214] } [0214]}

[0215] 请参阅图18a及图18b,其是本发明在不同LDPC区块长度及不同调制模式下的存储器的使用量及存储器的读写次数。 [0215] Referring to FIG 18a and FIG 18b, which is read at different times and different modulation LDPC block length patterns of memory usage and the memory of the present invention. 图18a显示不同的LDPC区块长度及不同的调制模式下存储器1314与存储器1321所需的大小,其中存储器1321又细分为上面所讨论的三种态样(频宽大小为单元大小的2倍、4倍及8倍)。 Figure 18a show the size of the required memory 1314 and memory 1321 at different LDPC block length and different modulation modes, wherein the memory 1321 is subdivided into three kinds twice aspect discussed above (the size of the bandwidth size unit , 4-fold and 8-fold). 图18b显示不同的LDPC区块长度及不同的调制模式下存储器1314的读写次数(同样细分为上述的三种态样),以及与已知存储器读写次数的比值。 Figure 18b show different LDPC block length is 1314 and the number of memory read and write different modulation modes (also subdivided into three aspects described above), and the ratio of the number of memory read and known. 结果显示,在同一种LDPC区块长度及同一种调制模式下,不论频宽大小与单元大小的倍数(w/c)为何,相较于已知的方法,皆能有效降低存储器的读写次数,尤其当w/c愈大时,效果愈显著。 The results showed that, at the same LDPC block length and the same modulation mode, regardless of the size of the cell bandwidth multiplied by the size (w / c) why, compared to the known method, able to effectively reduce the number of read-write memory especially when the w / c greater, more remarkable effect.

[0216] 请参阅图19,其是本发明的时间解交错的方法的一实施例的流程图。 [0216] Referring to FIG. 19, which is a flowchart of an embodiment of the present invention, the time deinterleaving method. 除前述的时间解交错电路外,本发明亦相对应地揭示了一种时间解交错的方法,应用于通信系统的信号接收端。 In addition to the time deinterleaving circuit, the present invention also discloses a method corresponding to a time-deinterleaving, applied to a signal receiving end of the communication system. 本方法由前揭时间解交错电路700或其等效电路来执行。 The method of the present time by the above-mentioned technical deinterleave circuit 700, or equivalent circuits. 如图19所示,本发明执行时间解交错的方法之一实施例包含下列步骤: , The execution time of one of the present invention is a method embodiment deinterleaver 19 embodiments include the steps of:

[0217] 步骤S1910 :提供一储存电路,该储存电路包含一存储器模块。 [0217] Step S1910: providing a storage circuit, the storage circuit comprises a memory module. 该存储器模块的读写操作以一个字组为单位,一个字组包含K个单元,K为大于1的正整数,例如是前述实施例的2、4、8,但不以此为限; Read and write operations to the memory module units of a block, a block comprising units K, K is a positive integer greater than 1, for example, the aforementioned embodiment 4, 8, but not limited to;

[0218] 步骤S1920 :将多个单元写入该储存电路,每次写入一个单元组。 [0218] Step S1920: a plurality of cells written into the storage circuit, each write a cell group. 一个单元组的大小即为一个字组的大小,以图8a为例,每次写入的单元组包含4个单元;以及 A cell size of a group is the block size to Figure 8a, for example, each group write unit comprises four units; and

[0219] 步骤S1930 :于自该储存电路读取该些单元之后及将该些单元输出之前,选择性地暂存该些单元。 [0219] Step S1930: After reading in from the storage circuit prior to the some of the unit and the output unit, temporarily storing the memory cells selectively. 每次读取一个单元组的数据量,为了使单元以时间解交错后的顺序输出, 每次从储存电路读出的数个单元其中有些不会立即输出,而是先暂存以待稍后使用,以减少对存储器模块的读取次数。 A read data amount per unit group, to the cell in the order of the time deinterleaver output, each read out from the storage circuit units wherein some of a plurality of outputs not immediately, but the first staging pending later used to reduce the number of the reading of the memory module.

[0220] 步骤S1930中暂存该单元组的单元时可以选择输出其中一个,而暂存其他的(K-1)个,如图8b的示意图所示。 May select [0220] Step S1930 cell in the cell group storing the output of one of them, and other temporary (K-1) th, a schematic diagram is shown in Figure 8b. 而且如图8b、图9c、图10c、图11c所示,当从该储存电路连续输出Nr个单元后,接下来连续输出NrX (K-1)个暂存的单元。 Further in FIG. 8B, FIG 9c, FIG 1OC, as shown in Figure 11c, when the continuously output from the storage units Nr circuit, the output of the next successive NrX (K-1) th temporary storage unit. 事实上,在不同的实施方式中,步骤S1930可以于每次读取一个单元组后,暂存全部的单元,而不立即输出,待暂存Nr个单元组后(对应图8a、图9c、图10c及图11c的存储器721的大小分别调整为8X4、 8X4、8X2及8X8个),再连续输出所有的暂存的单元。 In fact, in various embodiments, the step S1930 may be a cell group in each reading, all of the temporary storage means does not output immediately, until Nr temporary cell groups (corresponding to Figures 8a, 9c, FIGS. 10c and 11c of the memory 721 of FIG size were adjusted to 8X4, 8X4,8X2 and a 8X8), then all the buffered continuous output unit.

[0221] 请参阅图20,其是本发明的时间解交错的方法的另一实施例的流程图。 [0221] Please refer to FIG. 20, which is a flowchart showing another time deinterleaver of the present invention a method embodiment. 本方法由前揭时间解交错电路1300或其等效电路来执行。 The method of the present time by the above-mentioned technical deinterleaving circuit 1300 or its equivalent circuits. 如图20所示,本发明时间解交错的方法的一实施例包含下列步骤: One embodiment, the present invention is the time deinterleaver of the method shown in Figure 20 comprising the steps of:

[0222] 步骤S2010 :提供一储存电路,该储存电路包含一存储器模块。 [0222] Step S2010: providing a storage circuit, the storage circuit comprises a memory module. 该存储器模块的读写操作以一个字组为单位,一个字组包含K个单元,K为大于1的正整数,例如是前述实施例的2、4、8,但不以此为限; Read and write operations to the memory module units of a block, a block comprising units K, K is a positive integer greater than 1, for example, the aforementioned embodiment 4, 8, but not limited to;

[0223] 步骤S2020 :于接收单元之后及将单元写入该储存电路之前,选择性地暂存单元。 [0223] Step S2020: After receiving means and prior to writing the cell to the storage circuit, selectively temporary storage unit. 为了在之后的读取流程中每次读取的单元组的单元符合时间解交错的顺序,在将接收到的单元写入储存电路前,必须先将部分的单元暂存,以调整单元写入储存电路的顺序。 For unit cell group in the read process after the reading of each line with the order of the time deinterleaving, before the storing unit writes the received circuit unit must first staging section, to adjust the write means the sequence storage circuit. 如图14a、图15a、图16a及图17a所示,共有连续NcX (K-1)个单元被暂存; FIG. 14a, FIG. 15a, FIG. 16a and FIG. 17a, a total of continuous NcX (K-1) th unit is temporarily stored;

[0224] 步骤S2030 :选取该些暂存单元的部分以组成一单元组。 [0224] Step S2030: selecting the plurality of temporary storage unit section to form a cell group. 连续暂存NcX (K-1)个单元之后,每当有新接收的单元,即从暂存的单元中选取(K-ι)个来跟新接收的单元组成一个单元组; After the continuous staging NcX (K-1) units, whenever a new unit is received, i.e., selected from the temporary storage unit in the (K-ι) th to the newly received cell with a cell group consisting of;

[0225] 步骤S2040 :将该单元组写入该储存电路。 [0225] Step S2040: The written into the storage circuit unit group. 一个单元组的大小即为存储器模块的一个字组的大小,以图14a为例,每次写入的单元组包含4个单元;以及 Size is the size of a cell group of a block of memory modules, as an example in Figure 14a, each group write unit comprises four units; and

[0226] 步骤S2050 :自该储存电路读取该单元组。 [0226] Step S2050: the circuit reads from the storage unit group. 读取时每次读取一个单元组,因为每个单元组的单元顺序于写入该储存电路之前已经过调整,所以读出的单元组的单元顺序即是时间解交错后的单元顺序。 Each time a reading unit reading group, because the cell sequence for each cell group in the storage circuit before writing has been adjusted, the unit cell group sequentially read out, i.e., after the order is a unit of time deinterleaver.

[0227] 步骤S2020暂存该单元组的单元时可以连续暂存NcX (K-1)个,如图14a的示意图所示。 Continuous scratch NcX (K-1) th time [0227] Step S2020 the temporary storage unit of the unit group, a schematic diagram is shown in Figure 14a. 而且如图14a、图15a、图16a及图17a所示,当连续暂存NcX (K-1)个单元后,每接收一个新单元,便输出(K-1)个暂存的单元,来与新接收的单元组成一个单元组。 Further in FIG. 14a, FIG. 15a, FIG. 16a and, when the continuous staging NcX (K-1) units, each receiving a new cell, then the output of FIG. 17a (K-1) th temporary storage unit that the unit composed of a newly received cell group. 事实上, 在不同的实施方式中,步骤S2020可以连续暂存NcXK个单元(对应图14a、图15a、图16a 及图17a的存储器1321的大小分别调整为20X4、8X4、8X2及8X8个),之后再连续输出Nc个单元组至该储存电路。 In fact, in various embodiments, the step S2020 may be continuously NcXK temporary storage units (corresponding to FIG. 14a, FIG. 15a, FIG. 16a and FIG memory size 1321 17a 20X4,8X4,8X2 and were adjusted to a 8X8), after further continuous output Nc cell groups to the storage circuit.

[0228] 虽然本发明的实施例如上所述,然而该些实施例并非用来限定本发明,本技术领域具有通常知识者可依据本发明的明示或隐含的内容对本发明的技术特征施以变化,凡此种种变化均可能属于本发明所寻求的专利保护范畴,换言之,本发明的专利保护范围须视本说明书的权利要求书界定为准。 [0228] Although embodiments of the present invention as described above, however, this is not intended to limit these embodiments of the present invention, the art has the express or implied content Keyijuben ordinary skills of the invention is applied features of the invention changes, may belong to all these variations are sought patent protection scope of the present invention, in other words, the scope of patented subject invention claimed in this specification book defines claims and their equivalents.

Claims (20)

1. 一种时间解交错电路,位于一通信系统的信号接收端,用来对一交错信号进行时间解交错处理,该交错信号包含多个单元,该时间解交错电路包含: 一存储器模块,用来储存该些单元,该些单元W多个单元为单位形成多个单元组,该存储器模块的读写W-单元组为单位;W及一暂存存储器模块,自该存储器模块暂存该些单元的部分,W安排该些单元的输出顺序。 A time deinterleaving circuit, located at the signal receiving end of a communications system, an interlace signal used to time de-interleave processing, the interlace signal includes a plurality of units, the time deinterleaving circuit comprising: a memory module, with to store the memory cells, a plurality of the unit cell in units of W are formed a plurality of cell groups, the read-write memory module W- cell group as a unit; W and a temporary memory module, the memory module from the plurality of temporary portion of the cell, W order to arrange the plurality of output units.
2. 如权利要求1所述的时间解交错电路,其特征在于,在该时间解交错处理的过程中, 对同一单元组而言,对该存储器模块的写入及读取操作次数各为一次。 2. the time deinterleaving circuit of claim 1, wherein the de-interleave processing in the course of time, for the same cell group, the number of write and read operation of the memory module each time .
3. 如权利要求1所述的时间解交错电路,其特征在于,该存储器模块为一动态随机存取存储器,而该暂存存储器模块为一静态随机存取存储器。 3. the time deinterleaver circuit claim 1, wherein the memory module is a dynamic random access memory, which is a temporary memory module static random access memory.
4. 如权利要求1所述的时间解交错电路,其特征在于,还包含: 一选择单元,用来选择该存储器模块及该暂存存储器模块二者之一的输出W作为该时间解交错电路的输出。 4. The time according to claim 1 deinterleaver circuit, characterized by further comprising: a selecting unit for selecting the output W of one of the memory modules and both memory module as the temporary time deinterleaving circuit Output.
5. 如权利要求4所述的时间解交错电路,其特征在于,运些单元组的每一者包含K个单元,K为大于1的正整数,当该存储器模块输出运些单元组之一时,该被输出的单元组的其中一个单元直接由该选择单元输出,其他(KI)个单元则存入该暂存存储器模块。 5. The time to claim 4, wherein the deinterleaver circuit, wherein each cell group comprises more transport units K, K is a positive integer greater than 1, the memory module when one of these cell groups output op , the cell group is outputted from a unit outputs wherein the selection means directly, the other (KI) cells are stored in the temporary memory module.
6. 如权利要求5所述的时间解交错电路,其特征在于,该交错信号包含多个向前错误校正区块,每一向前错误校正区块包含N个单元,N为大于1的正整数,该暂存存储器模块的大小与NX化-1)呈比例关系。 6. claim 5 time deinterleaver circuit, wherein the interlace signal including a plurality of forward error correction blocks, each forward error correction block comprises N elements, N being a positive integer greater than 1, the size of the temporary memory module of NX -1) proportional relationship.
7. 如权利要求6所述的时间解交错电路,其特征在于,该选择单元于自该存储器模块连续输出f个单元后,自该暂存存储器模块连续输出该个单元。 7. The time according to claim 6 deinterleaver circuit, wherein the selection means to the memory module from the continuous output f units, from the continuous output of the temporary memory module units.
8. -种时间解交错电路,位于一通信系统的信号接收端,用来对一交错信号进行时间解交错处理,该交错信号包含多个单元,该时间解交错电路包含: 一存储器模块,用来储存该些单元,该些单元W多个单元为单位形成多个单元组,该存储器模块的读写是W-单元组为单位;W及一暂存存储器模块,用来暂存欲写入至该存储器模块的该些单元的部分,W安排该些单元写入至该存储器模块的顺序。 8. - three time deinterleaving circuit, located at the signal receiving end of a communications system, an interlace signal used to time de-interleave processing, the interlace signal includes a plurality of units, the time deinterleaving circuit comprising: a memory module, with to store the memory cells, a plurality of the unit cell in units of W are formed a plurality of cell groups, the read-write memory module is W- cell units of groups; W and a temporary memory module for temporary storage to be written portion of the unit to the memory module, W arranged sequentially written to the memory cells of the memory module.
9. 如权利要求8所述的时间解交错电路,其特征在于,在该时间解交错处理的过程中, 对同一单元组而言,对该存储器模块的写入及读取操作次数各为一次。 9. The time according to claim 8 deinterleaver circuit, characterized in that the de-interleave processing in the course of time, for the same cell group, the number of write and read operation of the memory module each time .
10. 如权利要求8所述的时间解交错电路,其特征在于,该存储器模块为一动态随机存取存储器,而该暂存存储器模块为一静态随机存取存储器。 8, 10. The time deinterleaving circuit of claim, wherein the memory module is a dynamic random access memory, which is a temporary memory module static random access memory.
11. 如权利要求9所述的时间解交错电路,其特征在于,还包含: 一选择单元,用来选择将该交错信号的运些单元直接写入至该存储器模块及暂存于该暂存存储器模块二者其中之一。 9, 11. The time deinterleaving circuit of claim, wherein, further comprising: a selection unit for selecting those transport means the interlace signal is written directly to the memory module, and is temporarily stored in the temporary storage wherein one of the two memory modules.
12. 如权利要求9所述的时间解交错电路,其特征在于,运些单元组的每一者包含K个单元,K为大于1的正整数,当将运些单元组的一者输入至该存储器模块时,该被输入的单元组的其中一个单元是直接由该选择单元输出至该存储器模块,其他(KI)个单元则存入该暂存存储器模块。 9, 12. The time deinterleaving circuit of claim, wherein each cell group comprises more transport units K, K is a positive integer greater than 1, when one of these units will be shipped to the set input when the memory module, wherein the cell group of one unit is input directly from the output selection unit to the memory module, the other (KI) cells are stored in the temporary memory module.
13. -种时间解交错的方法,应用于一通信系统的一时间解交错电路,用来对一交错信号进行时间解交错处理,该交错信号包含多个单元,该时间解交错电路包含一存储器模块, 该存储器模块的读写是W-单元组为单位,每一单元组包含多个单元,该方法包含: 将该交错信号的该些单元写入该存储器模块;W及自该存储器模块读取该些单元之后,选择性地暂存该些单元; 其中,在该时间解交错处理的过程中,对同一单元组而言,对该存储器模块的写入操作及读取操作各为一次。 13. - three time deinterleaving method applied to a communication system, a time deinterleaving circuit for time interlace signal to a de-interleave processing, the interlace signal includes a plurality of units, the time deinterleaving circuit comprises a memory module, the memory module is read W- units of cell groups, each cell group comprising a plurality of cells, the method comprising: interleaving the signals of the unit into the memory module; W is read from the memory module and after taking the memory cells, selectively temporary storage of the unit; wherein the de-interleave processing in the course of time, for the same cell group, the writing operation and the reading operation of the memory module each time.
14. 如权利要求13所述的方法,其中每一单元组包含K个单元,K为大于1的正整数, 该选择性地暂存该些单元的步骤储存每一单元组的(KI)个单元。 14. The method according to claim 13, wherein each cell set comprises cells K, K is a positive integer greater than 1, of the unit is the step of selectively temporary storage of each cell group (KI) th unit.
15. 如权利要求14所述的方法,其特征在于,该交错信号包含多个向前错误校正区块, 每一向前错误校正区块包含N个单元,N为大于1的正整数,输出该些单元时自该存储器模块连续输出^个单元后,连续输出散。 15. The method according to claim 14, wherein the interlace signal including a plurality of forward error correction blocks, each forward error correction block comprises N elements, N being a positive integer greater than 1, the output these cells from the memory module after the continuous output ^ cells, bulk continuous output. 个该暂存的单元。 A unit of the temporarily stored.
16. 如权利要求13所述的方法,其特征在于,该存储器模块为一动态随机存取存储器, 而该些暂存单元暂存于一静态随机存取存储器。 16. The method according to claim 13, wherein the memory module is a dynamic random access memory, and the plurality of temporarily stored in a temporary storage unit is a static random access memory.
17. -种时间解交错的方法,应用于一通信系统的一时间解交错电路,用来对一交错信号进行时间解交错处理,该交错信号包含多个单元,该时间解交错电路包含一存储器模块, 该存储器模块的读写W-单元组为单位,每一单元组包含多个单元,该方法包含: 于接收该交错信号的该些单元之后及将该些单元写入该存储器模块之前,选择性地暂存该些单元; 选取该些暂存单元的部分W组成一单元组; 将该单元组写入该存储器模块;W及自该存储器模块读取该单元组; 其中,在该时间解交错处理的过程中,对该单元组而言,对该存储器模块的写入操作及读取操作各为一次。 17. - three time deinterleaving method applied to a communication system, a time deinterleaving circuit for time interlace signal to a de-interleave processing, the interlace signal includes a plurality of units, the time deinterleaving circuit comprises a memory module, the read-write memory module W- cell group as a unit, each group comprising a plurality of unit cells, the method comprising: after receiving the plurality of unit in the interlace signals of these units and the memory modules before the write, selectively temporary storage of the unit; selecting the plurality of temporary storage units form a part of the cell group W; the module into the memory cell group; and W read from the memory module unit group; wherein, at the time deinterleaving processing process, in terms of the cell group, the writing operation and the reading operation of the memory module each time.
18. 如权利要求17所述的方法,其特征在于,每一单元组包含K个单元,K为大于1的正整数,该交错信号包含多个时间交错区块,每一时间交错区块包含N个向前错误校正区块, N为大于1的正整数,该选择性地暂存该些单元的步骤所连续储存的单元个数与NX化-1) 呈比例关系。 18. The method according to claim 17, wherein each cell set comprises cells K, K is a positive integer greater than 1, which comprises a plurality of time interleaved interlace signal blocks, each block comprising a time interleave forward error correction blocks of N, N being a positive integer greater than 1, which is selective of the unit number of the temporary storage unit in step with the continuous storage of NX -1) proportional relationship.
19. 如权利要求18所述的时间解交错电路,其特征在于,当该选择性地暂存该些单元的步骤储存5XNX化-1)个单元之后,每当接收一新输入的单元,该选取该些暂存单元的部分W组成一单元组的步骤自暂存的单元中选取化-1)个单元。 19. The time deinterleaver claim 18 circuit, characterized in that, after the step of the plurality of units in the temporary storage 5XNX of selectively -1) units, each time receiving a new input cell, the selecting the plurality of unit portions W register unit cell composed of a set of steps from the staging of selected -1) cells.
20. 如权利要求17所述的方法,其特征在于,该存储器模块为一动态随机存取存储器, 而该些暂存单元暂存于一静态随机存取存储器。 20. The method according to claim 17, wherein the memory module is a dynamic random access memory, and the plurality of temporarily stored in a temporary storage unit is a static random access memory.
CN201510207854.1A 2015-04-28 2015-04-28 Time deinterleaving circuit and execution time deinterleaving processing method CN106162318A (en)

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CN101540856A (en) * 2005-11-26 2009-09-23 Lg电子株式会社 Digital television transmitter/receiver and method of processing data in digital television
CN101242190A (en) * 2007-02-09 2008-08-13 卓胜微电子(上海)有限公司 Time de-interweaving method
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