CN106158021B

CN106158021B - Three-dimensional NAND gate memory with decoder and local word line driver

Info

Publication number: CN106158021B
Application number: CN201510134558.3A
Authority: CN
Inventors: 陈士弘
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2015-03-26
Filing date: 2015-03-26
Publication date: 2020-02-18
Anticipated expiration: 2035-03-26
Also published as: CN106158021A

Abstract

The invention discloses a memory. The memory comprises a plurality of stacks, a plurality of conductive vertical structures, a plurality of storage elements, a plurality of wires and a control circuit. The stack is comprised of a plurality of conductive strips. The conductive vertical structure is orthogonal to the stack. The storage element is located in a neighboring region of the stack at an intersection with side surfaces of the conductive vertical structures. The stack includes a bottom layer, a plurality of intermediate layers, and a top layer. The plurality of first wires are electrically coupled to the top layer. The plurality of second wires and the plurality of third wires are electrically coupled to the middle layer. The control circuit is used for enabling the first conducting wire to select at least one first specific stack of the stacks, enabling the second conducting wire to select the at least one first specific stack, and enabling the third conducting wire to select at least one layer of the middle layer.

Description

Three-dimensional NAND gate memory with decoder and local word line driver

Technical Field

The present invention relates to a high density memory device, and more particularly, to a memory device having a plurality of layers of memory cells arranged in a three-dimensional array.

Background

Three-dimensional storage devices have been developed into various configurations including a vertical channel structure (vertical channel structure). In the vertical channel structure, memory cells (memory cells) including charge storage structures (charge storage structures) are disposed at the horizontal plane of conductive stripes and adjacent regions of vertical active stripes. The conductive strip acts as a word line (word line). The vertical active stripe includes a plurality of channels used by the memory cells.

The memory may include multiple planes of memory cells including multiple stacked arrangements of multiple horizontal conductive stripes (word lines). The trend to increase memory capacity has prompted an increase in the number of stacks of horizontal conductive strips. The horizontal stripe select line is selected by a row select line (string select line). Unfortunately, the increase in the number of stacks causes problems of capacitance, noise (noise), and power consumption.

One way to increase storage capacity without increasing the number of stacks of horizontal conductive strips is to increase the number of planes and the number of ladder contacts. The step contacts access an increased number of planes. However, this approach is related to the density of the conductive lines electrically coupled to the ladder contacts and the decoder. These increased densities result in additional process challenges.

There is a great need to develop a three-dimensional integrated circuit memory using a vertical channel structure to reduce the disadvantages caused by the increased memory capacity.

Disclosure of Invention

According to various aspects of the present invention, the plurality of conductive lines (conductive lines) are, for example, block select lines (block select lines), and the control switches (control switches) are, for example, transistors. Other wires, such as layer select lines, carry layer select signals to select particular layers of word lines in turn. The transistor control layer selects whether the lines are electrically coupled to different layers of the word lines. The layer select line alone will turn on all the word lines of the selected layer. The combination of the layer selection line and the block selection line can only open the word lines of the selected layer. The remaining conductors (e.g., the row select line) select a particular stack of conductive strips (conductive strip), such as by activating an access transistor (access transistor) at the end of a NAND row (NAND strip). The row select signal carried by the row select line and the block select signal carried by the block select line both select a particular stack of conductive strips. This arrangement of conductors enables an increase in memory capacity without the problems described above. Various aspects of the invention will be described hereinafter.

According to an aspect of the present invention, a memory device is provided. The memory device includes a stack (stack) composed of a plurality of conductive lines (conductive), a plurality of semiconductor vertical structures (semiconductor vertical structures), a plurality of memory elements (memory elements), a plurality of conductive lines, and a control circuit. The semiconductor vertical structure is orthogonal to the stack. The memory element is located in a region adjacent to an intersection of the stack and a side surface of the semiconductor vertical structure.

The stack of conductive strips is interleaved with the insulating strips. The stack includes a bottom layer of conductive strips (bottom layer), intermediate layers of conductive strips, and a top layer of conductive strips.

The plurality of first wires are electrically coupled to the top layer of the conductive strip. The plurality of second wires and the plurality of third wires are electrically coupled to the middle layer.

The control circuit is used for enabling the first conducting wire to select a first specific stack (first specific stack) of the stacks, enabling the second conducting wire to select the first specific stack of the stacks, and enabling the third conducting wire to select a specific layer (specific layer) of the middle layer.

According to another aspect of the invention, a decoder (decoder) is included for the wire.

According to another aspect of the present invention, a method is provided. The method comprises the following steps:

the first conductive lines are made to select at least one first specific stack (first partial stack) of the plurality of stacks. The stack is made up of a plurality of conductive strips (conductive strips). The conductive strips are interlaced with a plurality of insulating strips (insulating strips). The stack includes a bottom layer of the conductive strips, intermediate layers of the conductive strips, and a top layer of the conductive strips. The first lead is electrically coupled to the top layer of the strip.

A plurality of second conductive lines is caused to select a first particular one of the stacks. The second lead is electrically coupled to the middle layer.

The third conductive line is made to select a specific layer of the intermediate layers. The second lead is electrically coupled to the middle layer.

The first conductive line, the second conductive line, and the third conductive line assist in selection of at least one of the plurality of memory elements. The storage elements are located in a plurality of contiguous regions of the stack at a plurality of intersection points with side surfaces of a plurality of semiconductor vertical structures. The semiconductor vertical structure is orthogonal to the stack.

In one embodiment, the first conductive line is a string select line. The second conductive line is electrically coupled to a plurality of switches (switches). The switch is electrically coupled to the third conductive line and the conductive strip. The third conductive line is a layer select line (layer select line). In one embodiment, the switch is a transistor. The transistor has a plurality of lateral gates. The side gate is located over a plurality of side conductive channels. The side conductive vias are electrically coupled to the conductive strips and the third conductive lines. In one embodiment, the switch is a transistor. The transistor has a plurality of gates (gates) surrounding a vertical conductive channel (vertical conductive channel). The vertical conductive channel is electrically coupled to the conductive strip and the third conductive line.

In one embodiment, the third conductive line is electrically coupled to the intermediate layer through the second conductive line.

In one embodiment, different intermediate layers are electrically coupled to different step contacts (ladder contacts), and different third conductive lines are electrically coupled to different step contacts.

In one embodiment, the second conductive line includes a specific decoding line (decoding line). A particular coding line selects a plurality of the stacks. The selected stack is electrically coupled to a first set of the plurality of first conductive lines. Different first conductors of the first set select different stacks.

In one embodiment, a first conductive decode line of the second conductive line selects only one of the stacks.

In an embodiment, the control loop is configured to cause the first conductive line to select at least a first specific one of the stacks, to cause the second conductive line to select at least a first specific one of the stacks and not select other portions of the stacks, and to cause the third conductive line to select at least a specific one of the intermediate layers and not select other portions of the intermediate layers.

In one embodiment, a plurality of fourth conductive lines are further included. The fourth conductive line is electrically coupled to the semiconductor vertical structure. A control loop causes the fourth conductive line to select a subset of the semiconductor vertical structures. This subset is arranged in a row, which is orthogonal to the stack.

In one embodiment, the third conductive line is parallel to the fourth conductive line.

In one embodiment, the apparatus further comprises a first decoder, a second decoder and a third decoder. The first decoder is electrically coupled to the first wire. The second decoder is electrically coupled to the second wire. The first decoder and the second decoder are located on a first side and a second side of the stack opposite to each other, and the first conducting wire is parallel to the second conducting wire. The third decoder is electrically coupled to the third wire. The third decoder is located at a third side of the stack. The third side is different from the first side and the second side.

In order to better understand the above and other aspects of the present invention, the following detailed description of the preferred embodiments is made with reference to the accompanying drawings, in which:

drawings

FIG. 1 is a simplified circuit diagram of a two-dimensional memory array of an embodiment;

FIG. 2 is a simplified circuit diagram of a three-dimensional memory array employing a vertical channel structure;

FIG. 3 is a schematic diagram showing a three-dimensional memory array employing a vertical channel structure;

FIG. 4 is a top view of a three-dimensional memory array employing a vertical channel structure;

FIG. 5 is a top view of a high capacity three dimensional memory array employing a vertical channel structure;

FIG. 6 is a top view of another high capacity three dimensional memory array employing a vertical channel structure;

FIG. 7 is a top view of another high capacity three dimensional memory array employing a vertical channel structure;

FIG. 8 is a block diagram of a three-dimensional memory array employing a vertical channel structure;

FIG. 9 is a simplified circuit diagram of a pass transistor similar to the three-dimensional memory device of FIG. 8;

FIG. 10 is a top view of a three-dimensional memory device employing a vertical channel structure and having pass transistors;

FIG. 11 is a top view of another three-dimensional memory device employing a vertical channel structure and having pass transistors;

FIGS. 12-13 are top and cross-sectional views of another three-dimensional memory device with a pass transistor using a vertical channel structure;

FIGS. 14-15 are top and cross-sectional views of another three-dimensional memory device with a pass transistor using a vertical channel structure;

FIGS. 16-17 are top and cross-sectional views of another three-dimensional memory device with a pass transistor using a vertical channel structure;

FIG. 18 is a simplified block diagram of an integrated circuit memory according to an embodiment of the present invention.

[ description of reference ]

1. 2, 3: connecting piece ladder

10. 11: page buffer

20. 21: character line decoder

101: integrated circuit board

120: inter-stack vertical channel structure

130. 141, 142, 143: connecting element

151. 152, 153, 161, 162, 163, 164, 165, 166, 171, 172, 173, 174, 175, 176, 181, 182, 183, 184, 185, 186: interlayer connecting piece

160: reference conductor

167. 177, 187: conductive decoding line

170. 190: access transistor

180: meeting point

201: column select line decoder

203: three-dimensional NAND gate memory array

204: x decoder

205: step connecting piece

206: global word line

207: character line voltage generator

208: block decoder

209: local word line driver

231. 232, 233, 234, 235, 236: layers of

251: vertical channel structure

252: memory element

261: vertical channel structure

262: dielectric substance

263. 264, 301, 302: conductive plug

310: horizontal channel structure

312. 313: section line

1800: integrated circuit with a plurality of transistors

1802: sense amplifier and data input structure

1805: data input line

1810: controller

1820: bias arrangement device

1830: bus line

1840: stripe decoder

1845: column select and ground select layers

1850: layer decoder/block decoder/local word line driver

1860: three-dimensional memory array

1865: bit line

1870: bit line decoder

1875: data bus

1885: data output line

1890: output circuit

B1, B2, B3: block selection line

BL1, BL 112, BL 113, BL2, BL 214, BL 215, BL3, BL316, BL 317, BL4, BL 418, BL 419: bit line

B #: conductive decoding line

L1, L2, L3, L4: global word line

GND 34: grounding point

GSL, GSL 32; GSL 210: grounding selection line

SSL, SSL1, SSL2, SSL3, SSL 30, SSL 142, SSL 244, SSL346, SSL 550, SSL 652, SSL # 240: column select line

WL1 22、WL1 23、WL2 24、WL2 25、WL3 26、WL3 27、WL4 28、WL4 29、WL₀～WL_N-1: character line

Detailed Description

The embodiments of the invention are described in detail below with reference to the drawings. The present invention is not intended to be limited to the specific structures and methods disclosed in the specification. The invention may be embodied in other features, component methods, or other embodiments. The preferred embodiments are merely illustrative of the present invention and are not intended to limit the scope of the invention. The protection scope of the present invention is subject to the claims. Those skilled in the art will appreciate that the description includes variations and equivalents thereof. Also, in the various embodiments, like elements are described with like reference numerals.

FIG. 1 is a simplified circuit diagram of a two-dimensional memory array.

A plurality of NAND gate (NAND) rows connected to memory cells are accessed through bit lines (bit lines) BL 112, BL 214, BL316, and BL 418. The nand gate row has a first end. The first terminal is connected to a page buffer (pagebuffer)10 through a bit line. The nand gate row has a second terminal. The second end is at ground GND 34. A first end of the nand gate row connected to the page buffer 10 has a plurality of access transistors (access transistors) controlled by a row select line (SSL) 30. The second end of the nand gate row connected to the ground GND 34 has a plurality of access transistors controlled by a Ground Select Line (GSL) 32. Different memory cells along a nand gate row are accessed by word lines WL 122, WL 224, WL326, and WL 428. Word lines WL 122, WL 224, WL326, and WL 428 are controlled by a word line decoder (word line decoder) 20.

Fig. 2 is a simplified circuit diagram of a three-dimensional memory array employing a vertical channel structure.

The three-dimensional array is formed by combining a plurality of adjacent two-dimensional arrays. For ease of illustration, the simplified circuit diagram parallels multiple two-dimensional arrays together.

The nand columns are accessed by bitlines BL 113, BL 215, BL 317, and BL419, respectively. The same bit lines are shared by multiple two-dimensional arrays. The first end of the nand gate column is connected to the page buffer 11 through a bit line. The nand gate has a second terminal connected to the ground GND 34. A first end of the nand gate row connected to the page buffer 11 has an access transistor controlled by row select lines SSL 142, SSL 244, and SSL 346. The access transistors of a particular two-dimensional array are selected and controlled by corresponding row select lines SSL 142, SSL 244, and SSL 346. The second end of the nand gate row connected to the ground GND 34 has a plurality of access transistors controlled by the ground select line GSL 32. Different memory cells along a nand gate row are accessed by word lines WL123, WL 225, WL 327, WL 429. The word lines WL123, WL 225, WL 327, WL 429 are controlled by a word line decoder 21.

Fig. 3 is a schematic diagram of a three-dimensional memory array employing a vertical channel structure.

The memory device includes an array of memory cells of a nand gate row. The memory device may be a double-gate vertical channel memory array (DGVC). In fig. 3, the three-dimensional memory array includes an integrated circuit substrate (integrated circuit substrate)101 and a plurality of stacks of conductive strips. Each conductive strip is separated by insulating material and comprises a bottom surface (ground selection line GSL) of the conductive strip, multiple intermediate layers (character lines WL) of the conductive strip₀～WL_N-1) And the top surface of the conductive strip (row select line SSL).

The plurality of vertical channel structures are orthogonal over the stack and include inter-stack vertical channel structures (inter-stack vertical channel structures) 120 and connecting elements (linking elements) 130. The inter-stack vertical channel structure 120 is located between the stacks. A connecting element 130 is positioned over the stack and connects the inter-stack vertical channel structures 120. The material of the connecting element 130 in this example comprises a semiconductor, such as polysilicon, which has a relatively high doping concentration, so that the connecting element 130 has a higher conductivity than the inter-stack vertical channel structure 120. The inter-stack vertical channel structure 120 is used to provide a channel region for memory cells within the stack. In fig. 3, the material of the connection element 130 may include an N + doped semiconductor material. The material of the inter-stack vertical channel structure 120 may include a lightly doped semiconductor material. The memory element includes a patterned conductive layer (not shown) connected to a vertical channel structure, such as a patterned conductive layer including a plurality of global bit lines (global bit lines) connected to a sensing circuit (sensing circuit).

The memory device includes a charge storage structure. The charge storage structure is located in the middle layer (word line WL) of the stack₀～WL_N-1) And cross-point 1 of inter-stack vertical channel structure 12080. In the illustrated example, the memory cells at the intersection 180 are in a vertical configuration. The conductive strips on both sides of one inter-stack vertical channel structure 120 serve as dual-gates and can be read, erased or programmed. In other embodiments, a surrounding gate may also be employed. The vertical channel structure traverses the horizontal strips. The horizontal strips surround the storage layer perpendicular to the frustums (frustum) of the vertical channel structure. The reference conductor 160 is disposed between the bottom layer of the strip (ground select line GSL) and the integrated circuit substrate 101.

The memory device includes a row select switch (string select switch) and a reference select switch (reference select switch). The row select switch is, for example, an access transistor (access transistor)190 located at the top layer of the stripe. The reference select switch is, for example, an access transistor (access transistor)170 located at the bottom layer of the stripe (ground select line GSL). In some examples, the dielectric layer of the charge storage structure serves as a gate dielectric layer of the

access transistors

170, 190.

In one embodiment, to reduce the resistance of reference conductor 160, the memory device may include a bottom gate (bottom gate) adjacent to reference conductor 160. During a read process, the bottom gate may be activated to increase the conductivity of the reference conductor 160 by applying an appropriate pass voltage (pass voltage) to a doped well or well (well) or other patterned conductive structure in the substrate.

The storage device includes a connection element. The connection elements include landing areas (landing reas) of horizontal word lines and Ground Selection Lines (GSL) line structures to form a ladder contact (ladder contact) of the decoding circuit. The row select lines of the top layer of conductive strips are independently coupled and controlled by row select line decoding circuits (string selection decoding circuits).

Middle layer (character line WL)₀～WL_N-1) Are connected together with the conductive strips of the bottom layer (ground select lines GSL) to reduce the area of the decoder and the overall size of the memory device. The conductive strips of the top layer (row select lines SSL) are independently decoded to allow the bit lines to be decoded.

The memory cell may includeConnection elements (such as connection elements 141 and 142) and interlayer connectors (such as interlayer connectors 151 and 152). In the middle layer (word line WL)₀～WL_N-1) The

connection elements

141, 142 provide a landing area (landing area) for the word line. The

interlayer connectors

151, 152 are coupled to the landing areas of the connecting

elements

141, 142. The connecting element includes an opening for coupling the interlayer connector to the landing area at the lower interlayer extension through the opening. The landing areas are located adjacent to the bottom surface of the inter-layer connectors and the top surface of the connecting elements.

As shown in FIG. 3, connecting elements 141 provide connections to word lines WL_N-1The landing area of (a). The connecting elements 142 provide connections to the word lines WL₀The landing area of (a).

As shown in fig. 3, the interlayer connectors connecting the word lines at the intermediate layer are arranged in a ladder structure. For example, the interlayer connection 151 is connected to a landing area to connect the interlayer and the word line WL_N-1. The interlayer connection 152 is connected to another landing area to connect the interlayer and the word line WL₀. The staircase structure may be formed in a word line decoder disposed at the edges of the array of nand columns and the peripheral circuitry of the memory cells.

In the example of fig. 3, the memory device includes a connection element and an interlayer connection member. The connection element is for example a connection element 143 connected to a ground selection line GSL in the bottom layer of the conductive strip. The interlayer connection layer is, for example, an interlayer connection 153 coupled to the underlying landing area. The interlayer connection extends across the interlayer (word line WL)₀～WL_N-1) Opening in the connecting element. The landing areas are located adjacent to the bottom surface of an interlayer connector (e.g., the interlayer connector 153) and the top surface of a connecting element (e.g., the connecting element 143).

Several examples of three-dimensional nand Memory architectures employing vertical channels have been described in the co-pending U.S. patent application No. 14/284,306, the 3D Independent Double Gate Flash Memory (3D Independent Flash Memory), commonly owned U.S. patent application No. 2014, 5/21. This patent application is incorporated by reference. And U.S. patent No. 8,013,383, "nonvolatile Semiconductor Storage Device Including a Plurality of Memory stripes (nonvolatile Semiconductor Storage Device incorporating a Plurality of Memory stripes", issued on 6.9.2011, U.S. patent publication No. 2102/0299086, "Semiconductor Memory Devices", issued on 29.11.2012, and U.S. patent No. 8,363,476, "Memory Device, Manufacturing Method and Method of operation thereof (Memory Device, manual operating Method and Method of operating the Same)", issued on 20.1.2013, are incorporated herein by reference. As described in these cited documents, various word line designs for vertical channel memory structures have been developed and these may be employed in embodiments of the present invention.

Fig. 4 is a top view of a three-dimensional memory device employing a vertical channel structure.

A plurality of nand rows connected to the memory cells are accessed through bit lines BL 113, BL 215, BL 317, and BL 419. The NAND gate column has a first end and a second end. The first terminal is connected to a page buffer through a bit line. The second terminal is connected to ground (not shown). The first end of the nand row starts with an access transistor controlled by row select lines SSL 142, SSL 244, and SSL 346. The stacks located in a particular vertical plane are selected by corresponding row select lines SSL 142, SSL 244, and SSL 346. The row select lines SSL 142, SSL 244, and SSL346 control access transistors located in a particular vertical plane. The second end of the nand gate row is connected to ground GND 34 and has an access transistor controlled by ground select line GSL 32. Different memory cells along a nand gate row are accessed by word lines WL123, WL 225, WL 327, WL 429. The word lines WL123, WL 225, WL 327, WL 429 are controlled by a word line decoder 21.

The different intermediate layers of the word lines are selected by the

interlayer connectors

161, 162, and 163. The

interlayer connectors

161, 162, and 163 are electrically connected to the landing areas of the different intermediate layers. The memory cells in the array include vertical channel structures 251 and memory elements 252.

Fig. 5 is a schematic diagram of a large-capacity three-dimensional storage device employing a vertical channel structure.

The capacity of the three-dimensional memory device of fig. 5 is greater than that of the three-dimensional memory device of fig. 4 by increasing the number of row selection lines and by increasing the number of word line stacks. The word lines are disposed on an increased number of vertical planes. The increased number of row select lines includes row select lines SSL 142, SSL 244, SSL346, SSL 448, SSL 550, and SSL 652. The increased number of interlayer connectors includes

interlayer connectors

161, 162, 163, 164, 165, and 166. The number of intermediate layers of the word line is also increased corresponding to the number of interlayer connectors. The

interlayer connectors

161, 162, 163, 164, 165, and 166 are electrically connected between the word line decoder 21 and the landing areas of the different intermediate layers by conductive lines (e.g., conductive decoding lines) 167. these increased number of stacks increases capacity, noise, and power consumption relative to the smaller number of stacked three-dimensional memory devices of FIG. 4.

Fig. 6 is a schematic diagram of another large-capacity three-dimensional storage device employing a vertical channel structure.

By increasing the number of intermediate layers of the word line, the capacity of the three-dimensional memory device of FIG. 6 is increased relative to FIG. 4. The added interlayer connectors include interlayer connectors 171, 172, 173, 174, 175, and 176 corresponding to the number of interlayer connectors.

The number of interlayer connectors and the number of interlayer layers of the character line are equal in fig. 5 and 6. However, the number of row select lines (vertical planes of the stack of word lines) is reduced. Another case is where the arrangement of the landing areas changes from depth 1 and width N to depth N and width 1. In this context, depth refers to the direction of the length of the word line and width refers to the direction of the bit line. The inter-connections 161, 162, 163, 164, 165, and 166 are electrically coupled to the word line decoder 21 through conductive decode lines 177. The process complexity is much higher than that of fig. 5 due to the crowding of the wires in a small space.

Fig. 7 is a schematic diagram of another large-capacity three-dimensional storage device employing a vertical channel structure.

By increasing the number of intermediate layers of the word line relative to fig. 4, the capacity of the three-dimensional memory device of fig. 7 is increased. The interlayer connections are added as

interlayer connections

181, 182, 183, 184, 185, and 186. The number of intermediate layers of the character line is also increased corresponding to the number of interlayer connectors.

The number of interlayer connectors and the number of interlayer layers of the character line are the same in fig. 5, 6, and 7. However, the number of row select lines (the number of word lines stacked in a vertical plane) is between that of FIGS. 5 and 6. The landing areas are not arranged with a depth of 1 and a width of N, nor with a depth of N and a width of 1. Instead, the landing areas are arranged to have a depth of 2 and a width of N/2. In this context, depth refers to the direction of the length of the word line and width refers to the direction of the bit line. The

interlayer connectors

181, 182, 183, 184, 185, and 186 are electrically connected between the word line decoder 21 and the landing areas of the various intermediate layers by conductive lines, such as conductive decode lines 187. The wires are arranged in a larger space than in fig. 6. This space is still smaller than that of fig. 5 and the process is more complicated.

Fig. 8 is a block diagram of a three-dimensional memory device employing a vertical channel structure.

A three-dimensional NAND memory array (3D NAND memory array)203 includes a plurality of NAND gate rows. The NAND gate row is connected to the memory cells, and the memory cells are accessed by the bit lines. The nand gate column has a first end and a second end, the first end is connected to the page buffer 11 through a bit line, and the second end is located at the ground point. The first end of the nand gate row connected to the page buffer 11 has a plurality of access transistors controlled by row select lines. The row select lines are controlled by a row select line decoder 201. A three-dimensional nand gate array is a similar arrangement of multiple two-dimensional arrays. A particular two-dimensional array is selected by a corresponding row select line that controls the access transistors of the two-dimensional array. The different memory cells of the nand gate row are accessed via a word line, which is activated via a word line voltage generator 207. A layer decoder (layerdecoder) and a state machine circuit (not shown) are located in the word line voltage generator 207 to control the voltages of the different global word lines (global word lines) 206. For example, the word line voltage generator 207 can be used to control different global word lines 206 to have different voltages for erase, program and read processes. The word line voltage generator 207 is electrically coupled to the local word lines of the three-dimensional nand memory array 203 through a ladder connection 205 and a local word line driver 209. The local word line drivers may act as transistor-like switches to electrically connect and disconnect the global word lines 206 to the local word lines of the three-dimensional nand memory array 203. The combination of the page buffer 11 to bit line signals, the row select line decoder 201 to row select line signals, the word line voltage generator 207 to local word line signals via local word line driver 209 may fully indicate a memory cell in a three dimensional array.

The local word line driver 209 controls a plurality of switches that electrically couple the global word line 206 to the local word lines of the three-dimensional nand memory array 203 via ladder connections 205. A block decoder 208 performs block decoding to turn on or off a group of switches of the local word line drivers 209. The global word line driver 207 may provide voltages to a plurality of word lines of an intermediate layer and the local word line driver 209 may turn off a portion of the word lines of the intermediate layer that are enabled by the global word line 206.

The conductive global word line 206 from the word line voltage generator 207 is parallel to the conductive bit line from the page buffer 11. In this embodiment, the SSL decoder 201 and the X decoder (X-decoder)204 are located on two sides of the three-dimensional nand memory array 203. The X-decoder 204 may include a local word line driver 209 and a block decoder 208.

In the three-dimensional nand memory array and the ladder connector 205, the dashed lines represent different blocks electrically isolated from each other. Such electrical isolation allows for the activation of portions of local wordlines with different block select lines in a particular interlayer.

One block may be the smallest erase unit in a NAND gate flash (NAND flash). For a two-dimensional NAND gate, each block hasThere is one row select line SSL/ground select line GSL. In a three-dimensional nand gate, a plurality of row select lines SSL and a ground select line GSL may be located in a single block. Flash memory has a limited life cycle; for example, a flash memory cell will wear out after 1000 program/erase cycles. In order to increase the life cycle of the memory chip, the data read/write of each block must be balanced. In the case of a damaged block, a good block can still be used. The minimum unit of the present invention is a block. In a two-dimensional NAND gate, the block size is N_BL*N_WL. In a three-dimensional NAND gate, the block size is N_BL*N_WL*N_ssL。N_BLIs the number of bit lines of a block. N is a radical of_WLThe number of word lines for one block. N is a radical of_SSLThe number of row select lines SSL for one block.

Fig. 9 is a simplified circuit diagram of a pass transistor (passresistor) similar to the ladder connection of the three-dimensional memory device of fig. 8.

The word line voltage generator 207 controls different global word lines (e.g., the global word lines L1, L2, L3, and L4) to have different voltages for performing erase, program, and read processes.

Different global wordlines L1, L2, L3, and L4 turn on/off different levels of the wordline, respectively. The global word line L1 is electrically coupled to the first level (static step 1). The global word line L2 is electrically coupled to the second level (starcasecep 2). The global word line L3 is electrically coupled to the third level (cascade step 3). The global word line L4 is electrically coupled to the fourth level (static step 4). The different levels are electrically coupled to different intermediate layers of the word line. As described above, each level may be any set of ladder connections (cascade contacts) controlled by block select signals (block select signals).

The block decoder 208 controls the transistors to act as word line drivers to switch whether the global word line signal reaches the corresponding ladder connection and the corresponding word line middle layer. The signals generated by block decoder 208 are carried by conductive block select lines (block select lines) B1, B2, and B3. The block select lines B1, B2, and B3 enable and disable particular blocks of wordline drivers, respectively, to enable and disable local wordlines of particular intermediate layers. Each conductive block select line B1, B2, and B3 controls a column of wordline driver transistors connected to different connector ladders (cascades). The different connector steps are electrically insulated from each other. The block selection line B1 controls a row of word line driver transistors connected to a connection ladder (connection ladder) 1. The block selection line B2 controls a row of word line driver transistors connected to a connection ladder (connection ladder) 2. The block selection line B3 controls a row of word line driver transistors connected to a connection ladder (connection ladder) 3. The connector steps 1, 2, and 3 are electrically insulated from each other.

Fig. 10 is a top view of a three-dimensional memory device having a pass transistor (pass transistor) and employing a vertical channel structure. The pass transistor enables a particular word line associated with a row of select lines of the three-dimensional memory device.

The signals generated by the word line voltage generator 207 are carried by conductive global word lines L1, L2, L3, L4, L5, and L6. The global wordlines L1, L2, L3, L4, L5, and L6 enable and disable different levels of the wordlines. The global word line L1 is electrically coupled to the level 231. The global word line L2 is electrically coupled to the level 232. Global word line L3 is electrically coupled to level 233. The global word line L4 is electrically coupled to the level 234. The global word line L5 is electrically coupled to the level 235. The global word line L6 is electrically coupled to the level 236.

The block decoder 208 controls the word line driver transistors. The word line driver transistor switches whether the signal of the global word line reaches the corresponding interlayer connection member and the corresponding interlayer of the local word line. For example, the word line driver transistors at the intersection of the block select line B1 and the global word line L1 have a gate around structure (gate around structure) with a vertical channel structure 261 traversing a dielectric (dielectric) 262. The signals generated by the block decoder 209 are carried by block select lines B1, B2, and B3. The block select lines B1, B2, and B3 turn on and off particular word line driver transistors, respectively, and turn on and off the local word lines of particular blocks of the respective intermediate layers.

The memory cells within the array include vertical channel structures 251 and memory elements 252. The vertical channel structure may include a semiconductor material capable of serving as a channel of a memory device, such as silicon (Si), germanium (Ge), germanium silicide (SiGe), gallium arsenide (GaAs), carbon Silicide (SiC), and Graphene. The memory elements of a memory device may include charge storage structures such as multilayer dielectric charge trapping structures (mll) as are well known in the flash memory art. Multilayer dielectric charge trapping structures are, for example, ONO (oxide-nitride-oxide), SONOS (silicon-oxide-nitride-silicon), BE-SONOS (bonded silicon-oxide-nitride-silicon), TANOS (titanium oxide, silicon nitride, silicon oxide, silicon), and MA BE-SONOS (metal-high-k bonded silicon-oxide-silicon).

The nand column connecting the memory cells is accessed by bit lines BL1, BL2, BL3, and BL 4. Bit lines select memory cells at different locations along the local word lines. The same localized word lines located along different intermediate layers select memory cells. The nand gate row has a first end. The first terminal is connected to the page buffer 11 through a bit line. The nand gate row has a second terminal. The second end is located at the ground point. The first end of the nand gate row connected to the page buffer 11 has a plurality of access transistors controlled by row select lines SSL1, SSL2, and SSL 3. The second end of the nand gate row connected to the ground has a plurality of access transistors controlled by a ground select line GSL.

The first nand row is turned on and off by grounding SSL 1. The transistors in the local wordlines of the first nand row are controlled by ground B1. The second row of nand gates is turned on and off by row select line SSL 2. The transistors at the local word lines of the first nand column are controlled by block select line B2. The third row of nand gates is turned on and off by row select line SSL 3. The transistors at the local wordlines of the third nand column are controlled by block select line B3.

As such, even though the global word line voltage generated by the word line voltage generator 207 is coupled to a plurality of local word lines in the same middle layer, the block decoder 208 may only activate a selected portion of the local word line driver transistors. Thereby, only a selected portion of the local wordlines may be activated in the same middle layer. For example, the word line voltage generator 207 may employ a conductive global word line L1 to select a plurality of local word lines in the top middle layer through the level 231. From these local word lines, block select line B1 enables only the transistors associated with row select line SSL1, block select line B2 enables only the transistors associated with row select line SSL2, and block select line B3 enables only the transistors associated with row select line SSL 3.

The layer select line (layer select line) is parallel to the word line. The row select line SSL determines a vertical line width (vertical pitch). The word line and the layer selection line determine a horizontal line width (horizontal pitch). The number of block selection lines may be equal to or less than the number of row selection lines SSL.

Fig. 11 is a top view of a three-dimensional memory structure employing a vertical channel structure and having pass transistors. The pass transistor enables a particular word line associated with a plurality of row select lines.

Fig. 10 is similar to the arrangement of the three-dimensional memory device of fig. 11. However, in FIG. 11, the signals generated by block decoder 208 are carried by conductive decode lines B #. The conductive decode line B # enables and disables the particular word line transistors corresponding to the plurality of row select lines. In FIG. 11, all transistors of the NAND string are turned on and off by word line driver transistors controlled by conductive decode line B #. The nand row is turned on and off by row select lines SSL1, SSL2, and SSL 3. In contrast, in fig. 10, the signals generated by the block decoder 208 are carried by block select lines B1, B2, and B3, and respectively turn on and off the word line driver transistors of a particular block corresponding to one row select line. In other embodiments, the block select lines may enable and disable particular block-fast word line driver transistors corresponding to other numbers of row select lines.

Fig. 12 and 13 are top and side views of a three-dimensional memory device employing a vertical channel structure and having pass transistors. The pass transistor enables a word line associated with a particular portion of a column select line.

Some of the elements of the different three-dimensional memory devices of fig. 10 and 11 are described in more detail in fig. 12 and 13. Fig. 12 and 13 show the row select lines and block select lines of the three-dimensional memory device of fig. 10 in detail, such as the row select line SSL1 and the block select line B1, or the row select line SSL2 and the block select line B2, or the row select line SSL3 and the block select line B3. Fig. 12 and 13 also detail the column select lines and block select lines, such as the column select line SSL2 and the conductive decode line B #, of the three-dimensional memory device of fig. 11.

Conductive global wordlines L1, L2, L3, L4, L5, and L6 activate and deactivate

levels

231, 232, 233, 234, 235, and 236, respectively. The conductive global word lines L1, L2, L3, L4, L5, and L6 carry the signals generated by the word line voltage generator to the

stages

231, 232, 233, 234, 235, and 236, respectively.

The global word line L1 is electrically coupled to the level 231 of the inter-layer link through the word line driver transistors. The global word line L2 is electrically coupled to the level 232 of the inter-layer link through word line driver transistors. Global word line L3 is electrically coupled to level 233 of the inter-level connection through word line driver transistors. The global word line L4 is electrically coupled to the level 234 of the inter-layer link through word line driver transistors. The global word line L5 is electrically coupled to the level 235 of the inter-layer link through word line driver transistors. The global word line L6 is electrically coupled to the level 236 of the inter-layer link through word line driver transistors.

Block decode lines (e.g., conductive decode line B #) carry signals from the block decoder to control the word line driver transistors. The word line driver transistor switches whether the signal of the global word line reaches the corresponding interlayer connection member and the corresponding interlayer of the local word line. For example, the conductive word line driver transistors at the intersection of conductive decode line B # and global word line L1 have a gate all around structure. The surrounding gate structure has a vertical channel structure 261 that passes through a dielectric 262 surrounding the vertical channel structure 261. The vertical channel structure 261 of the word line driver transistor is electrically coupled to the global word line L1 and the local word line plane 231 via conductive plugs (conductive plugs) 263 and 264. The intersections of the conductive decode line B # and the other global word lines L2, L3, L4, L5, and L6 also have corresponding word line driver transistors with surrounding gate structures.

Conductive decode lines B # carry signals from the block decoder to turn on and off the word line driver transistors and the local word lines. Conductive decode line B # enables and disables word line driver transistors electrically coupled to global word line L1 and level 231, word line driver transistors electrically coupled to global word line L2 and level 232, word line driver transistors electrically coupled to global word line L3 and level 233, word line driver transistors electrically coupled to global word line L4 and level 234, word line driver transistors electrically coupled to global word line L5 and level 235, and word line driver transistors electrically coupled to global word line L6 and level 236.

The memory cells of the array include vertical channel structures 251 and memory elements 252 accessed by bit line BL 1. The remaining bit lines BL2, BL3, and BL4 also access similar memory cells including vertical channel structures and storage elements. The nand columns connected to the memory cells are accessed by bit lines BL1, BL2, BL3, and BL 4. The bit lines select memory cells at different locations along

levels

231, 232, 233, 234, 235, and 236.

The same bit line selects memory cells along different intermediate layers. The nand gate row has a first end. The first terminal is connected to the page buffer through bit lines BL1, BL2, BL3, and BL 4. The nand gate row has a second terminal. The second end is located at the ground point. The first end of the nand gate row connected to the page buffer has an access transistor controlled by a row select line SSL # 240. The second end of the nand string has access transistors controlled by a Ground Select Line (GSL) 210 for electrically connecting the nand string to ground.

The nand row is enabled and disabled via row select line SSL #. The transistors of the word lines in the nand gate row are turned on and off by conductive decode line B #.

As such, even if the global word line voltage generated by the word line voltage generator 207 is connected to a plurality of local word lines of the same middle layer, the block decoder 208 can activate only a portion of the local word line driver transistors, and thereby can activate only a portion of the local word lines of the same middle layer. For example, the word line voltage generator may select the top middle layer with the conductive global word line L1 passing through the level 231.

Fig. 14 and 15 are a top view and a cross-sectional view of a three-dimensional memory device employing a vertical channel structure and having a thin film pass transistor (tft). The pass transistor enables the word line with respect to the row select line.

Fig. 14 has section line 312, which is used to indicate the location of the section of fig. 15.

The three-dimensional memory device of FIG. 14 is similar to the three-dimensional memory device of FIG. 11 in that the memory cells of the word lines of the NAND row are turned on and off by conductive decode lines B #. The nand row is enabled or disabled by row select lines SSL1, SSL2, and SSL 3. However, the transistor controlled by the conductive decoding line B # in fig. 11 has a gate all around structure (gate all around structure), and the transistor controlled by the conductive decoding line B # in fig. 14 is a thin film transistor (thin film transistor).

The global word lines L1, L2, L3, L4, L5, and L6 carry signals generated by the word line voltage generator to the

stages

231, 232, 233, 234, 235, and 236. The global wordlines L1, L2, L3, L4, L5, and L6 are electrically coupled to a conductive plug (e.g., conductive plug 301). A conductive plug (e.g., conductive plug 301) is electrically coupled to a first end of a horizontal channel structure (horizontal channel structure) 310. In the top view of fig. 14, a column of conductive plugs including conductive plug 301 is shown in solid lines, the column being located above horizontal channel structure 310. The material of the horizontal channel structure 310 may be the same as the material of the vertical channel structure 251. Alternatively, the horizontal channel structure 310 and the vertical channel structure 251 may be made of different materials. A second end of the horizontal channel structure 310 is electrically coupled to a conductive plug (e.g., the conductive plug 302). In the top view of fig. 14, a column of conductive plugs including conductive plug 302 is shown in phantom lines, the column being located below horizontal channel structure 310.

Fig. 15 shows a conductive plug 301 located above a horizontal channel structure 310 and a conductive plug 302 located below the horizontal channel structure.

In a row of conductive plugs including conductive plugs 302, the conductive plug corresponding to global word line L1 is electrically coupled to the interlayer connectors of level 231, the conductive plug corresponding to global word line L2 is electrically coupled to the interlayer connectors of level 232, the conductive plug corresponding to global word line L3 is electrically coupled to the interlayer connectors of level 233, the conductive plug corresponding to global word line L4 is electrically coupled to the interlayer connectors of level 234, the conductive plug corresponding to global word line L5 is electrically coupled to the interlayer connectors of level 235, and the conductive plug corresponding to global word line L6 is electrically coupled to the interlayer connectors of level 236.

The interlayer connections of the levels 231 are not shown in fig. 15. Similarly, in the cross section of global word line L1, level 231 is above level 232, and the second end of the horizontal channel structure 310 is connected to level 231 by a shorter conductive plug 302. Similarly, in the cross section of global word line L3, level 233 is below level 232, and the second end of horizontal channel structure 310 is connected to level 233 by longer conductive plugs 302. Similarly, in the cross section of global word line L4, the level 234 is below the level 232, and the second end of the horizontal channel structure 310 is connected to the level 234 through the longer conductive plug 302. Similarly, in the cross section of global word line L5, the level 235 is located below the level 232, and the second end of the horizontal channel structure 310 is connected to the level 235 by a longer conductive plug 302. Similarly, in the cross section of global word line L6, the level 236 is below the level 232, and the second end of the horizontal channel structure 310 is connected to the level 236 by the longer conductive plug 302.

Fig. 16 and 17 are a top view and a cross-sectional view of another three-dimensional memory device having a thin film pass transistor (tft) with a vertical channel structure. The pass transistor enables the word line with respect to the row select line. Fig. 16 has section line 313, which is used to indicate the location of the section of fig. 17.

FIGS. 16-17 are similar to the three-dimensional memory devices of FIGS. 14-15. However, the horizontal channel structure 310 of FIGS. 14-15 does not extend above the conductive plug 302; in FIGS. 16-17, the horizontal channel structure 310 extends over the conductive plug 302.

In other embodiments, the word line driver transistors controlled by the block decoder have long channels with lengths greater than 1.5 μm.

FIG. 18 is a simplified block diagram of an integrated circuit memory according to one implementation of the present disclosure.

Integrated circuit 1800 includes a three-dimensional memory array 1860 on an integrated circuit board.

Stripe decoder 1840 is coupled to row select and ground select layers 1845 within memory array 1860. Bit line decoder 1870 is coupled to bit lines 1865 in memory array 1860 for reading and programming memory cells in memory array 1860. In the layer decoder/block decoder/local word line driver 1850, the block decoder is electrically coupled to a plurality of blocks of the word line driver. The word line driver, for example, is a transistor that may electrically couple or electrically decouple a global word line and a local word line in memory array 1860. And in layer decoder/block decoder/local wordline driver 1850, the layer decoder controls the programming, erasing, and reading voltages provided to the global wordlines. Addresses are supplied on bus 1830 to bit line decoder 1870, strip decoder 1840, and layer decoder/block decoder/local word line driver 1850. Sense amplifiers and data-in structures 1802 are coupled to the bit line decoder 1870 using a data bus 1875. The sense data from the sense amplifier is supplied to an output circuit (output circuit)1890 through a data output line 1885. The output circuit 1890 outputs the sensed data to a destination external to the integrated circuit 1800. Input data is input via a data-in line 1805 from an input/output port of the integrated circuit 1800 or from a data source internal or external to the integrated circuit 1800. The data source is, for example, a module having system-on-a-chip (system-on-a-chip) functionality supported by a general purpose processor, application specific circuits, and three-dimensional memory array 1860.

In the example of FIG. 18, the controller 1810 controls the read or program voltage provided by the bias arrangement 1820. The controller 1810 may include a multi-level cell (MLC) programming and reading mode. The controller 1810 may employ conventional application-specific logic (special-purpose logic). In another embodiment, the controller includes a general-purpose processor (general-purpose processor). In other embodiments, the controller may be a combination of a general purpose processor and application specific logic circuitry.

The integrated circuit 1800 may support word line driver switches, such as transistors. The transistors turn the word lines on and off through a block decoder. Memory array 1860 may include a first conductive line. A first conductive line is connected to a top layer of the conductive strip to select a first particular stack according to a row select line decoder. Memory array 1860 may include second conductors. The second conducting wire is electrically coupled to the plurality of middle layers so as to select the first specific stack according to the block decoder. Memory array 1860 may include a third conductive line. The third wire is electrically connected to the middle layer to select a specific layer according to the layer decoder.

In some embodiments, the row select lines are twisted (twisted) so that multiple sets of discrete row select lines can access the array. In some embodiments, the bit lines are twisted so that groups of bit lines can access the array.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory device, comprising:

a plurality of stacks (stack) of conductive strips (insulating strips) interleaved with insulating strips, the stacks comprising a bottom layer (bottom layer) of the conductive strips, intermediate layers (intermediate layers) of the conductive strips, and a top layer (top layer) of the conductive strips;

a plurality of semiconductor vertical structures (semiconductor vertical structures) orthogonal to the stack;

a plurality of memory elements (memory elements) located at a plurality of adjacent regions of the stack at a plurality of intersection points with side surfaces of the semiconductor vertical structure;

a plurality of first conductive lines for controlling a plurality of transistor switches (transistors) located at the top layer of the conductive strips;

multiple second wires for controlling multiple local word line driver switches (local word line drivers)

A plurality of third conductive lines including a plurality of global word lines (global word lines) electrically coupled to the middle layer through the local word line driver switches.

2. The storage device of claim 1, further comprising:

a control circuit (control circuit) for making the first conductive line select at least one first specific stack (first specific stack) of the stacks, for making the second conductive line select the at least one first specific stack of the stacks, and for making the third conductive line select a specific layer (specific layer) of the intermediate layer.

3. The memory device of claim 1, wherein the local word line driver switches are transistors (transistors) having side gates over side conductive channels electrically coupled to the conductive stripes and the third conductive lines.

4. The memory device of claim 1, wherein the local wordline driver switches are transistors having gates surrounding a vertical conductive channel (gate) electrically coupled to the conductive strip and the third conductive line.

5. The memory device of claim 1, wherein different ones of the intermediate layers are electrically coupled to different ones of a plurality of step contacts (staircase contacts), and different ones of the third conductive lines are electrically coupled to different ones of the step contacts.

6. The memory device of claim 1, wherein the second conductive line includes a specific decoding line (decoding line) that selects ones of the stacks, the selected stacks being electrically coupled to a first set of the plurality of first conductive lines, different ones of the first conductive lines of the first set selecting different ones of the stacks.

7. The memory device of claim 1, wherein a first conductive decode line of the second conductive line selects only one of the stacks.

8. The storage device of claim 1, further comprising:

a control loop for causing the first conductive line to select at least a first particular one of the stacks, causing the second conductive line to select the at least the first particular one of the stacks and not select other portions of the stacks, and causing the third conductive line to select at least a particular layer of the intermediate layer and not select other portions of the intermediate layer.

9. The storage device of claim 1, further comprising:

a plurality of fourth conductive lines including a plurality of bit lines electrically coupled to the semiconductor vertical structures,

wherein a control loop causes the fourth conductive line to select a subset of the semiconductor vertical structures arranged in a column orthogonal to the stack.

10. The memory device of claim 9, wherein the third conductive line is parallel to the fourth conductive line.

11. The storage device of claim 1, further comprising:

a first decoder electrically coupled to the first conductive line; and

a second decoder electrically coupled to the second conductive line, wherein the first decoder and the second decoder are located on a first side and a second side of the stack opposite to each other, and the first conductive line is parallel to the second conductive line.

12. A method of operating a memory device, comprising:

selecting a first conductive stack of a plurality of stacks from a plurality of first conductive stacks, the stack being composed of a plurality of conductive strips (conductive strips) interleaved with a plurality of insulating strips (insulating strips), wherein the stack comprises a bottom layer of the conductive strips, a plurality of intermediate layers of the conductive strips, and a top layer of the conductive strips, the first conductive lines controlling transistor switches (transistor switches) located at the top layer;

controlling a plurality of local word line driver switches (local word line drivers) by a plurality of second conductive lines to select the at least one first specific stack of the stacks; and

selecting at least one specific layer (a partial layer) of the middle layer by passing a plurality of third conductive lines through the local word line driver switch, the third conductive lines including a plurality of global word lines (global word lines),

wherein the first conductive line, the second conductive line, and the third conductive line assist in selection of at least one of a plurality of storage elements located in a plurality of contiguous regions of a plurality of intersections of the stack with side surfaces of a plurality of semiconductor vertical structures (semiconductor vertical structures) that are orthogonal to the stack.

13. The method of claim 12, wherein the local word line driver switches are transistors having side gates over side conductive channels electrically coupled to the conductive stripes and the third conductive lines.

14. The method of claim 12, wherein the local wordline driver switches are transistors having gates surrounding a vertical conductive channel (gate) electrically coupled to the conductive strip and the third conductive line.

15. The method of claim 12, wherein different ones of the intermediate layers are electrically coupled to different ones of a plurality of step contacts (staircase contacts), and different ones of the third conductive lines are electrically coupled to different ones of the step contacts.

16. The method of claim 12, wherein the second conductive line comprises a specific decoding line (decoding line) that selects the plurality of stacks, the selected stacks are electrically coupled to a first set of the plurality of first conductive lines, and different first conductive lines of the first set select different stacks.

17. The method of operating a memory device of claim 12, wherein a first conductive decode line of the second conductive line selects only one of the stacks.

18. The method of operating a storage device of claim 12, further comprising:

the first conductive line is caused to select at least a first particular stack of the stacks, the second conductive line is caused to select the at least the first particular stack of the stacks and not select other portions of the stacks, and the third conductive line is caused to select at least a particular layer of the intermediate layer and not select other portions of the intermediate layer.

19. The method of operating a storage device of claim 12, further comprising:

a plurality of fourth conductive lines are made to select a subset of the semiconductor vertical structures, the subset being arranged in a column, the column being orthogonal to the stack.

20. The method of operating a memory device according to claim 19, wherein the third conductive line is parallel to the fourth conductive line.