CN106098618A - Array substrate manufacturing method and array substrate - Google Patents

Array substrate manufacturing method and array substrate Download PDF

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Publication number
CN106098618A
CN106098618A CN201610740909.XA CN201610740909A CN106098618A CN 106098618 A CN106098618 A CN 106098618A CN 201610740909 A CN201610740909 A CN 201610740909A CN 106098618 A CN106098618 A CN 106098618A
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metal oxide
oxide layer
layer
array substrate
process
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CN201610740909.XA
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Chinese (zh)
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王凯
任文明
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to CN201610740909.XA priority Critical patent/CN106098618A/en
Publication of CN106098618A publication Critical patent/CN106098618A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Abstract

The invention provides an array substrate manufacturing method and an array substrate. The array substrate manufacturing method includes an active layer film forming process which includes the steps of forming a first metallic oxide layer on a gate insulation layer S10, conducting annealing process on the first metallic oxide layer S20, and forming a second metallic oxide layer on the first metallic oxide layer after the annealing process is completed S30. According to the array substrate manufacturing method, contact oxidation between a source-drain electrode and the active layer can be reduced, contact resistance between the two can be reduced, electron mobility is improved, and the product quality and performance are further increased.

Description

阵列基板制备方法及阵列基板 The method of preparing an array substrate and an array substrate

技术领域 FIELD

[0001] 本发明设及显示技术领域,具体地,设及一种阵列基板制备方法及阵列基板。 [0001] The present invention is provided and display technologies, and in particular, for fabricating an array substrate provided, and one method and the array substrate.

背景技术 Background technique

[0002] 近年来,随着液晶显示器尺寸的不断增大,驱动电路的频率不断提高,现有的非晶娃薄膜晶体管迁移率很难满足需求。 [0002] In recent years, with the increasing size of liquid crystal display, the frequency of the driving circuit continues to increase, the conventional amorphous thin film transistor baby mobility difficult to meet. 高迁移率的薄膜晶体管有多晶娃薄膜晶体管和金属氧化物薄膜晶体管,尽管对多晶娃薄膜晶体管的研究比较早,但是多晶娃薄膜晶体管的均一性差,制作工艺复杂。 The thin film transistor of high mobility thin film transistor and the polycrystalline baby metal oxide thin film transistor, although studies polycrystalline thin film transistor baby earlier, but the uniformity of a polycrystalline thin film transistor baby difference complex manufacturing process. 金属氧化物薄膜晶体管(IGZO TFT)具有工艺简单、大面积沉积均匀性好、响应速度快、可见光范围内透过率高等特点,可W更好地满足大尺寸液晶显示器和有源有机电致发光的需求,引起了学术界和工业界的广泛关注。 A metal oxide thin film transistor (IGZO TFT) having a simple process, large-area deposition uniformity is good, fast response, and high transmittance in the visible range, W can better meet the large-size liquid crystal display and an organic electroluminescent active demand, caused widespread concern in academia and industry.

[0003] 在金属氧化物薄膜晶体管中,氧空位是载流子的主要来源,然而过多的氧空位会导致有源层内部缺陷太多,进而影响器件性能。 [0003] In the metal oxide thin film transistor, the source of oxygen vacancies is the main carrier of the carrier, however, can lead to excessive oxygen vacancy defects in the active layer inside too, thereby affecting device performance. 因此,金属氧化物薄膜必须在大气或者氧气环境中,通过退火来消除过多的氧空位,同时减少有源层内部的缺陷。 Thus, the metal oxide thin film must be in the air or an oxygen atmosphere, by annealing to remove excessive oxygen vacancy, while reducing internal defects of the active layer. 退火后的金属氧化物薄膜内部和表面的氧含量将增大,进而其电阻率增大了2~3个数量级。 A metal oxide thin film and the inner surface of the oxygen content will increase after annealing, and thus its resistivity increases by 2-3 orders of magnitude.

[0004] 但是,在源漏电极的制备完成之后,源漏电极的金属原子很容易与有源层中的氧形成接触氧化。 [0004] However, after completion of the preparation of the source drain electrode, source and drain electrodes formed in contact with the metal atom is easily oxidized with oxygen in the active layer. 接触氧化将大大增加源漏电极与有源层之间的接触电阻,影响电子迁移率, 使得器件的性能降低。 Contact oxidation will greatly increase the contact resistance between the source and drain electrodes and the active layer, the electron mobility of impact, so that the performance of the device is reduced.

发明内容 SUMMARY

[0005] 本发明旨在至少解决现有技术中存在的技术问题之一,提出了一种阵列基板制备方法及阵列基板,其可W减少源漏电极与有源层之间的接触氧化,降低二者的接触电阻,从而可W提局电子迁移率,进而提局广品品质和性能。 [0005] The present invention is to solve at least one of the prior art technical problems, we propose a production method of an array substrate and an array substrate, which may reduce the W contact oxidation between the source and drain electrode and the active layer, reducing both the contact resistance, which can provide W Board electron mobility, and thus provide a wide product quality and performance Bureau.

[0006] 为实现本发明的目的而提供一种阵列基板制备方法,包括有源层成膜工艺,所述有源层成膜工艺包括W下步骤: [0006] In order to achieve the object of the present invention to provide a method for preparing an array substrate, an active layer comprising a film forming process, the active layer deposition process comprising the steps of W:

[0007] S10,在栅绝缘层上形成第一金属氧化层; [0007] S10, the first metal oxide layer is formed on the gate insulating layer;

[000引S20,对所述第一金属氧化层进行退火工艺; [000 cited S20, the first metal oxide layer annealing process;

[0009] S30,在完成所述退火工艺之后的所述第一金属氧化层上形成第二金属氧化层。 [0009] S30, the second metal oxide layer is formed on the annealing process after completion of the first metal oxide layer.

[0010] 优选的,在完成所述步骤S30之后,还包括半色调掩膜工艺,其包括W下步骤: After [0010] Preferably, in the completion of the step S30, the process further comprising a half-tone mask, which comprises the steps of W:

[0011] S31,在所述第二金属氧化层上涂布光刻胶; [0011] S31, a photoresist is coated on the second metal oxide layer;

[0012] S32,采用半色调掩膜版对所述第二金属氧化层进行图案化,在此过程中,使位于与形成源漏电极之间的沟道区相对应的区域保留部分厚度的所述光刻胶。 [0012] S32, using the halftone mask of the second metal oxide layer is patterned, in this process, the channel region located between the source and the drain electrode is formed corresponding to the region of the thickness of the remaining portion said photoresist.

[0013] 优选的,在完成所述步骤S20之后,且在进行所述步骤S30之前,还包括半色调掩膜工艺,其包括W下步骤: After [0013] Preferably, in the completion of the step S20, the previous and performing the step S30, the process further comprising a half-tone mask, which comprises the steps of W:

[0014] S21,在所述第一金属氧化层上涂布光刻胶; [0014] S21, a photoresist is coated on the first metal oxide layer;

[0015] S22,采用半色调掩膜版对所述第一金属氧化层进行图案化工艺,在此过程中,保留形成源漏电极之间的沟道区所对应区域的部分厚度的光刻胶。 [0015] S22, the thickness of the photoresist portion using a halftone mask the first metal oxide layer patterning process, in this process, to retain the channel region is formed between the corresponding source and drain regions .

[0016] 优选的,在完成所述步骤S30之后,还包括源漏电极制备工艺,其包括W下步骤: After [0016] Preferably, in the completion of the step S30, the source and drain electrodes further comprises a preparation process comprising the steps of W:

[0017] S40,在所述第二金属氧化层上制备源漏金属层; [0017] S40, the second metal oxide layer on said source-drain metal layer is prepared;

[0018] S50,同时对所述第二金属氧化层和所述源漏金属层进行图案化工艺,W形成所述沟道区,并去除所述沟道区所对应区域的所述部分厚度的光刻胶。 [0018] S50, while the second metal oxide layer and the source-drain metal layer patterning process, W the channel region is formed, and removing the portion corresponding to the thickness of the channel region of the region photoresist.

[0019] 优选的,在完成所述步骤S32之后,还包括源漏电极制备工艺,其包括W下步骤: [0019] Preferably, after completion of the step S32, the source and drain electrodes further comprises a preparation process comprising the steps of W:

[0020] S40,在所述第二金属氧化层上制备源漏金属层; [0020] S40, the second metal oxide layer on said source-drain metal layer is prepared;

[0021] S50,对所述源漏金属层进行图案化工艺,W形成所述沟道区,并去除所述沟道区所对应区域的所述部分厚度的光刻胶。 [0021] S50, the source-drain metal layer patterning process, W the channel region is formed, the photoresist is removed and the portion corresponding to the thickness of the region of the channel region.

[0022] 优选的,所述第一金属氧化层的厚度为400~々OOA。 [0022] Preferably, the thickness of the first metal oxide layer 400 to 々OOA.

[002引优选的,所述第二金属氧化层的厚度为30-50A。 [Cited Preferably, the second metal oxide layer 002 thickness of 30-50A.

[0024] 优选的,所述第一金属氧化层和第二金属氧化层采用相同的材料。 [0024] Preferably, the first metal oxide layer and the second metal oxide layer is made of the same material.

[0025] 优选的,所述第一金属氧化层和第二金属氧化层所采用的材料包括Zn0、InZn0、 ZnSnO 或者Zr InZnO。 [0025] Preferably, the material of the first metal oxide layer and the second metal oxide layer is employed comprising Zn0, InZn0, ZnSnO or Zr InZnO.

[0026] 作为另一个技术方案,本发明还提供一种阵列基板,包括设置在栅绝缘层上的有源层,所述有源层包括: [0026] As a further aspect, the present invention also provides an array substrate comprising an active layer disposed on the gate insulating layer, said active layer comprising:

[0027] 经过退火工艺的第一金属氧化层;W及 [0027] The first metal oxide layer is subjected to an annealing process; and W is

[0028] 设置在所述第一金属氧化层上,且未经退火工艺的第二金属氧化层。 [0028] disposed on the first metal oxide layer, a second metal oxide layer and without an annealing process.

[0029] 本发明具有W下有益效果: [0029] The present invention has the beneficial effects W:

[0030] 本发明提供的阵列基板制备方法及阵列基板的技术方案中,其在经过退火工艺的第一金属氧化层上设置未经退火工艺的第二金属氧化层。 [0030] The method of preparing an array substrate and an array substrate of the present aspect of the invention provides that the metal oxide layer of the second annealing process is not provided on the first metal oxide layer after the annealing process. 由于未经退火工艺的第二金属氧化层具有内部和表面氧含量少、导电性能好的特定,因此,W该第二金属氧化层作为缓冲层,可W避免源漏电极与氧含量较高的第一金属氧化层直接接触,从而可W减少源漏电极与有源层之间的接触氧化,降低二者的接触电阻,从而可W提高电子迁移率,进而提高产品品质和性能。 Since the oxide layer of the second metal without annealing process having less internal and surface oxygen content, good specific conductivity, and therefore, the second metal oxide layer W as the buffer layer, source and drain electrodes may be W avoid high oxygen content the first metal oxide layer in direct contact, thereby reducing the source-drain contact oxidation W between the electrode and the active layer, reducing the contact resistance between the two, thereby enhancing electron mobility W, thereby improving product quality and performance.

附图说明 BRIEF DESCRIPTION

[0031 ]图1为本发明第一实施例提供的阵列基板制备方法的流程框图; [0031] Figure 1 provides a block flow diagram of a method according to a first embodiment of an array substrate of the present invention was prepared;

[0032] 图2为本发明第二实施例提供的阵列基板制备方法的流程框图; [0032] FIG. 2 is a schematic flow diagram of a second method of fabricating an array substrate according to an embodiment of the present invention;

[0033] 图3为本发明第=实施例提供的阵列基板制备方法的流程框图; [0033] Figure 3 is a flow diagram of the invention of = the array substrate production method according to an embodiment;

[0034] 图4为本发明实施例提供的阵列基板的剖视图; [0034] FIG. 4 is a cross-sectional view of an array substrate according to an embodiment of the present invention;

[0035] 图5为本发明实施例采用的一种像素俯视图;W及 [0035] A pixel of FIG. 5 using the top view of the embodiment of the present invention; and W is

[0036] 图6为本发明实施例采用的另一种像素俯视图。 [0036] FIG 6 a plan view of another embodiment of the pixel of FIG employed in the present invention.

具体实施方式 Detailed ways

[0037] 为使本领域的技术人员更好地理解本发明的技术方案,下面结合附图来对本发明提供的阵列基板制备方法及阵列基板进行详细描述。 [0037] to enable those skilled in the art better understand the technical solution of the present invention, the following method for fabricating an array substrate and an array substrate of the present invention to provide the drawings will be described in detail with.

[0038] 请一并参阅图1~图6,阵列基板制备方法主要包括:依次在衬底1上形成栅极2、形成栅绝缘层3、形成有源层、形成源漏电极6、形成像素电极7、形成纯化层8和形成公共电极9。 [0038] Referring to FIG. 1 to FIG. 6, a method for fabricating an array substrate including: sequentially forming on a substrate a gate electrode 2, a gate insulating layer 3 is formed, an active layer, source and drain electrodes 6 are formed, the pixel electrodes 7, 8 and the passivation layer forming the common electrode 9 is formed. 本发明提供的阵列基板制备方法是针对形成有源层的工艺进行的改进,具体地,图1为本发明第一实施例提供的阵列基板制备方法的流程框图。 The method of fabricating an array substrate according to the present invention is to provide an improved process for forming the active layer is, in particular, Figure 1 provides a block flow diagram of a method according to a first embodiment of an array substrate of the present invention was prepared. 请参阅图I,阵列基板制备方法包括有源层成膜工艺。 Referring to FIG I, the method for fabricating an array substrate including an active layer deposition process. 该有源层成膜工艺包括W下步骤: The active layer deposition process comprising the steps of W:

[0039] SlOl,在栅绝缘层3上形成第一金属氧化层4。 [0039] SlOl, a first metal oxide layer 4 is formed on the gate insulating layer 3.

[0040] S102,对该第一金属氧化层4进行退火工艺。 [0040] S102, the first metal oxide layer 4 an annealing process.

[0041 ] S103,在完成退火工艺之后的第一金属氧化层4上形成第二金属氧化层5。 [0041] S103, a second metal oxide layer 5 is formed on the first metal oxide layer 4 after the annealing process is completed.

[0042] 由于未经退火工艺的第二金属氧化层5具有内部和表面氧含量少、导电性能好的特定,因此,W该第二金属氧化层5作为缓冲层,可W避免源漏电极6与氧含量较高的第一金属氧化层4直接接触,从而可W减少源漏电极6与有源层之间的接触氧化,降低二者的接触电阻,从而可W提高电子迁移率,进而提高产品品质和性能。 [0042] Since the second metal oxide layer 5 having a non-annealed process less internal and surface oxygen content, good specific conductivity, and therefore, W the second metal oxide layer 5 as the buffer layer, source-drain electrodes may be avoided W 6 higher oxygen content of the first metal oxide layer 4 in direct contact, thereby reducing the source-drain contact oxidation W between the electrode 6 and the active layer, reducing the contact resistance between the two, whereby W can improve the electron mobility, thereby increasing the product quality and performance.

[0043] 优选的,第一金属氧化层4的厚度为400~600A。 [0043] Preferably, the thickness of the first metal oxide layer 4 is 400 ~ 600A. 第二金属氧化层5的厚度为30~50A。 The second metal oxide layer 5 has a thickness of 30 ~ 50A. 经检测,采用本实施例提供的阵列基板制备方法获得的阵列基板,源漏电极6与有源层的接触电阻可由8.2千欧降低至7.6千欧,大约降低了500欧姆,电子迁移率提高了约10%,从而提局了广品品质和性能。 After testing, the present method of fabricating an array substrate, an array substrate provided by the embodiment is obtained, the contact resistance of the source and drain electrode 6 of the active layer may be lowered to 8.2 kilohms 7.6 kilohms reduction of approximately 500 ohms, increased electron mobility about 10%, thereby improving the quality and performance of the Bureau of wide goods.

[0044] 优选的,第一金属氧化层4和第二金属氧化层5采用相同的材料,运可W使二者相接触的界面接触紧密,从而可W有效阻止后续使用中水汽的侵入,进而可W提高阵列基板的寿命。 [0044] Preferably, the first metal oxide layer 4 and the second metal oxide layer using the same material 5, W may be transported so that the contact interface of close contact with both, whereby W can effectively prevent the intrusion of water vapor for subsequent use, and then W can increase the life of the array substrate. 在实际应用中,第一金属氧化层4和第二金属氧化层5所采用的材料包括ZnO、 InZnO、ZnSnO或者Zr InSiO等的金属氧化物。 In practical applications, the first metal oxide layer 4 and the second metal oxide layer 5 comprises a material employed ZnO, InZnO, ZnSnO, or metal oxide such as Zr InSiO.

[0045] 图2为本发明第二实施例提供的阵列基板制备方法的流程框图。 [0045] FIG. 2 is a schematic flow diagram of an array substrate production process of another embodiment of the present invention. 请参阅图2,在完成上述步骤S103之后,还包括半色调掩膜工艺,其包括W下步骤: Please refer to FIG. 2, after the completion of the above step S103, the process further comprising a half-tone mask, which comprises the steps of W:

[0046] S104,在第二金属氧化层5上涂布光刻胶。 [0046] S104, on the second metal oxide layer 5 is applied a photoresist.

[0047] S105,采用半色调掩膜版对第二金属氧化层5进行图案化,在此过程中,使位于与形成源漏电极6之间的沟道区相对应的区域保留部分厚度的光刻胶。 [0047] S105, using the halftone mask for the second metal oxide layer 5 is patterned, in this process, so that the source-drain channel formed located region between the source region 6 corresponding to the thickness of the light receiving portion reserved engraved plastic.

[004引在步骤S104中,光刻胶的厚度为200~.2000A。 [004 cited in the step S104, the photoresist having a thickness of 200 ~ .2000A.

[0049] 在步骤S105中,采用半色调掩膜版对第二金属氧化层5进行图案化,在图案化过程中,光刻胶在经过曝光、显影之后,形成光刻胶完全去除区、光刻胶部分保留区和光刻胶完全保留区。 [0049] In step S105, using the halftone mask of the second metal oxide layer 5 is patterned in the patterning process, photoresist after exposure and development to form a photoresist completely removed region, light engraved rubber portion and a photoresist is completely reserved area reserved area. 其中,光刻胶完全保留区对应待形成的源漏电极覆盖的区域;光刻胶完全去除区对应除有源层之外的其余区域,该光刻胶完全去除区内的有源层通过刻蚀工艺去除;之后, 采用一定光强的紫外线照射光刻胶部分保留区和光刻胶完全保留区内的光刻胶,使得光刻胶部分保留区内的光刻胶完全变性并显影去除,而光刻胶完全保留区内仍然保留有部分厚度的光刻胶。 Wherein the photoresist completely-retained region corresponding to the source and drain regions to be formed in the electrode cover; completely removed photoresist areas corresponding to the remaining regions other than the active layer, the active layer of the photoresist is completely removed by the engraved region removing the etch process; after using a certain intensity of UV irradiation of the photoresist and a photoresist portion reserved area fully retained photoresist region, portions of the photoresist such that the photoresist is completely denatured reserved areas removed and developed, the photoresist completely retained region still retains part of the photoresist thickness.

[0050] 在完成步骤S105之后,开始进行源漏电极制备工艺,其包括W下步骤: [0050] After completion of step S105, the source and drain electrodes start preparation process, which comprises the steps of W:

[0051] S106,在第二金属氧化层5上制备源漏金属层。 [0051] S106, the second metal oxide layer on the source-drain metal layer 5 was prepared.

[0052] S107,同时对第二金属氧化层5和源漏金属层进行图案化工艺,W形成沟道区,并去除该沟道区所对应区域的部分厚度的光刻胶。 [0052] S107, while the second metal oxide layer 5 and the source-drain metal layer patterning process, W to form a channel region, and removing portions of the photoresist corresponding to the thickness of the channel region of the region.

[0053] 在步骤S106中,可W通过瓣射工艺在第二金属氧化层5上沉积源漏(S/D,Source/ Drain,源/漏)金属层。 [0053] In step S106, the valve can exit through the process of depositing W source and drain (S / D, Source / Drain, source / drain) of the second metal layer on the metal oxide layer 5. 该源漏金属层的厚度为H)()0~6000 A。 The source-drain metal layer has a thickness H) () 0 ~ 6000 A.

[0054] 在步骤S107中,在源漏金属层上形成一层光刻胶,利用源漏电极掩膜版对光刻胶进行曝光、显影,使得待形成源漏电极的区域的光刻胶保留,其他区域的光刻胶完全去除; 然后,通过刻蚀工艺使源漏金属层图案化,形成源漏电极。 [0054] In step S107, a photoresist layer is formed on the source drain metal layer, source and drain electrodes using the photoresist mask is exposed and developed, such that the photoresist regions to be source and drain electrodes are formed retention , other regions of the photoresist is completely removed; then, by an etching process of the source-drain metal layer is patterned to form source and drain electrodes. 此时源电极和漏电极之间的沟道区出现,该沟道区内保留有在进行上述步骤S105时预留的部分厚度的光刻胶。 At this time, the channel region between the source and drain electrodes occurs, the reserved channel region of the photoresist S105 when performing the above-described step portion reserved thickness. 然后,将源漏电极上方的光刻胶及该沟道区所对应区域的部分厚度的光刻胶一起做剥离处理,从而在源漏电极与有源层接触的区域具有第二金属氧化层5,如图5所示。 Then, the photoresist above the source and drain electrodes and the channel region of the photoresist portions corresponding to the thickness of the region made with the release process, so as to have a second metal oxide layer 5 in the source and drain electrodes in contact with the active layer region , as shown in FIG.

[0055] 在本实施例中,通过在有源层形成的过程中使位于与形成源漏电极之间的沟道区相对应的区域保留部分厚度的光刻胶,不仅可W在源漏电极形成的过程中,避免刻蚀工艺对有源层的破坏,而且该光刻胶还可W代替传统的刻蚀阻挡层,从而省去刻蚀阻挡层的成膜及掩膜工艺,降低生产成本,简化工艺,进而提高产品良率和产品效益。 [0055] In the present embodiment, the channel region located between the active layer formed during the manipulation with the source and drain electrodes are formed corresponding to the thickness of the retained portion of the photoresist region, not only in the source-drain electrodes W in the process of forming, an etching process to avoid damage to the active layer, and the photoresist also W instead of the traditional etch stop layer, thereby eliminating the process of forming a mask and an etch stop layer, to reduce production costs , simplifying the process, thereby increasing product yield and product benefits.

[0056] 图3为本发明第=实施例提供的阵列基板制备方法的流程框图。 [0056] Figure 3 is a flow diagram of the invention of = the array substrate production method according to an embodiment. 请参阅图3,本实施例提供的阵列基板制备方法与上述第二实施例相比,其区别在于:在有源层成膜工艺中, 在对第一金属氧化层4完成退火工艺之后,且在形成第二金属氧化层5之前,进行上述半色调掩膜工艺。 Please refer to FIG. 3, the present embodiment of the method for fabricating an array substrate provided by the second embodiment as compared with the embodiment, except that: in the active layer deposition process, the annealing process after the completion of four first metal oxide layer, and before forming the second metal oxide layer 5, the above-described halftone mask process. 具体地,包括W下步骤: Specifically, W comprises the steps of:

[0化7] S201,在栅绝缘层上形成第一金属氧化层4。 [0 of 7] S201, a first metal oxide layer 4 is formed on the gate insulating layer.

[0化引S202,对该第一金属氧化层4进行退火工艺。 [0 of primers S202, the first metal oxide layer 4 an annealing process.

[0化9] S203,在第一金属氧化层4上涂布光刻胶。 [0 of 9] S203, photoresist is applied on a first metal oxide layer 4.

[0060] S204,采用半色调掩膜版对第一金属氧化层4进行图案化工艺,在此过程中,保留形成源漏电极之间的沟道区所对应区域的部分厚度的光刻胶。 [0060] S204, using the halftone mask the first metal oxide layer 4 patterned process, in this process, a photoresist is formed to retain the source-drain region corresponding to the channel region between the source of partial thickness.

[0061 ] S205,在完成退火工艺之后的第一金属氧化层4上形成第二金属氧化层5。 [0061] S205, a second metal oxide layer 5 is formed on the first metal oxide layer 4 after the annealing process is completed.

[0062] 步骤S203和步骤S204的具体过程与上述第二实施例中的步骤S104和步骤S105相类似,在此不再寶述。 [0062] The specific process steps S203 and S204 and steps S104 and step S105 in the second embodiment is similar, which is not described treasure.

[0063] 在完成步骤S205之后,开始进行源漏电极制备工艺,其包括W下步骤: [0063] After completion of step S205, the source and drain electrodes start preparation process, which W comprising the steps of:

[0064] S206,在第二金属氧化层5上沉积源漏金属层。 [0064] S206, the second metal oxide layer on the source-drain metal layer 5 is deposited.

[0065] S207,对源漏金属层进行图案化工艺,W形成沟道区,并去除沟道区所对应区域的部分厚度的光刻胶。 [0065] S207, the source-drain metal layer patterning process, W to form a channel region, and removing portions of the photoresist corresponding to the thickness of the region of the channel region.

[0066] 步骤S206和步骤S207的具体过程与上述第二实施例中的步骤S106和步骤S107相类似,在此不再寶述。 [0066] Step S206 and step S207 of specific process steps of the above-described second embodiment is similar to the step S107 and S106, which will not be described treasure.

[0067] 在本实施例中,一方面,通过在有源层形成的过程中使位于与形成源漏电极之间的沟道区相对应的区域保留部分厚度的光刻胶,不仅可W在源漏电极形成的过程中,避免刻蚀工艺对有源层的破坏,而且该光刻胶还可W代替传统的刻蚀阻挡层,从而省去刻蚀阻挡层的成膜及掩膜工艺,降低生产成本,简化工艺,进而提高产品良率和产品效益。 [0067] In the present embodiment, on the one hand, by the process of the active layer is located in the manipulation of the channel region formed between the source and drain electrodes corresponding to the region of the retained portion of the photoresist thickness is formed, not only in W source and drain electrode formation process, the etching process to avoid damage to the active layer, and the photoresist also W instead of the traditional etch stop layer, thereby eliminating the process of forming a mask and an etch stop layer, reduce production costs, simplify processes, and improve product yield and product benefits. 另一方面,通过在对第一金属氧化层完成退火工艺之后,且在形成第二金属氧化层之前,进行上述半色调掩膜工艺,除了在源漏电极与有源层接触的区域具有第二金属氧化层(如图6中示出的第二金属氧化层51)之外,在源漏电极的下方均具有第二金属氧化层(如图6中示出的第二金属氧化层52),从而不仅会降低源漏电极与有源层之间的接触电阻,而且还可W降低源漏电极的电阻,从而可W降低因该电阻导致的信号衰减,进一步提高产品品质。 On the other hand, by an annealing process after completion of the first metal oxide layer and before forming the second metal oxide layer, the above-described halftone mask process, in addition to the source and drain electrodes in contact with the active region layer having a second than the metal oxide layer (second metal oxide layer, as shown in the illustrated 516), below the source and drain electrodes each having a second metal oxide layer (second metal oxide layer, as shown in the illustrated 526), so that not only will reduce the contact resistance between the source and drain electrode and the active layer, and W also reduce the resistance of source and drain electrodes, thereby reducing signal attenuation W caused by the resistance, further improve product quality.

[0068] 作为另一个技术方案,本发明还提供一种阵列基板,其包括由下而上依次设置的衬底1、栅极2、栅绝缘层3、有源层、源漏电极6、像素电极7、纯化层8和公共电极9。 [0068] As a further aspect, the present invention also provides an array substrate, comprising a substrate which are sequentially disposed from bottom to top 1, the gate electrode 2, a gate insulating layer 3, an active layer, source and drain electrodes 6, the pixel electrode 7, the passivation layer 8 and the common electrode 9. 其中,有源层包括:经过退火工艺的第一金属氧化层5。 Wherein the active layer includes: a first metal oxide layer 5 through the annealing process. W及设置在第一金属氧化层4上,且未经退火工艺的第二金属氧化层5。 W and disposed on the first metal oxide layer 4, without the annealing process and a second metal oxide layer 5.

[0069] 由于未经退火工艺的第二金属氧化层5具有内部和表面氧含量少、导电性能好的特定,因此,W该第二金属氧化层5作为缓冲层,可W避免源漏电极6与氧含量较高的第一金属氧化层直接接触,从而可W减少源漏电极6与有源层之间的接触氧化,降低二者的接触电阻,从而可W提高电子迁移率,进而提高产品品质和性能。 [0069] Since the second metal oxide layer 5 having a non-annealed process less internal and surface oxygen content, good specific conductivity, and therefore, W the second metal oxide layer 5 as the buffer layer, source-drain electrodes may be avoided W 6 higher oxygen content of the first metal oxide layer in direct contact, thereby reducing the source-drain contact oxidation W between the electrode 6 and the active layer, reducing the contact resistance between the two, thereby enhancing electron mobility W, thereby improving the product quality and performance.

[0070]可W理解的是,W上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式,然而本发明并不局限于此。 [0070] W can be understood that the embodiments are merely illustrative embodiment W principles of the present invention. The exemplary embodiment of the exemplary embodiment, but the present invention is not limited thereto. 对于本领域内的普通技术人员而言,在不脱离本发明的精神和实质的情况下,可W做出各种变型和改进,运些变型和改进也视为本发明的保护范围。 For those of ordinary skill in the art, without departing from the spirit and substance of the invention can be W that various modifications and improvements, shipped some modifications and improvements into the protection scope of the invention.

Claims (10)

1. 一种阵列基板制备方法,包括有源层成膜工艺,其特征在于,所述有源层成膜工艺包括W下步骤: S10,在栅绝缘层上形成第一金属氧化层; S20,对所述第一金属氧化层进行退火工艺; S30,在完成所述退火工艺之后的所述第一金属氧化层上形成第二金属氧化层。 1. A method of fabricating an array substrate, an active layer comprising a film forming process, characterized in that the active layer deposition process comprising the steps of W: S10, a first metal oxide layer is formed on the gate insulating layer; S20, the first metal oxide layer annealing process; and a second metal oxide layer is formed on the S30, the annealing process after completion of the first metal oxide layer.
2. 根据权利要求1所述的阵列基板制备方法,其特征在于,在完成所述步骤S30之后,还包括半色调掩膜工艺,其包括W下步骤: S31,在所述第二金属氧化层上涂布光刻胶; S32,采用半色调掩膜版对所述第二金属氧化层进行图案化,在此过程中,使位于与形成源漏电极之间的沟道区相对应的区域保留部分厚度的所述光刻胶。 The method of fabricating an array substrate according to claim 1, wherein, after completion of the step S30, the process further comprising a half-tone mask, which comprises the step of W: S31, the second metal oxide layer coated photoresist; S32, using a half-tone mask of the second metal oxide layer is patterned, in this process, the channel region located between the source and the drain electrode is formed corresponding to the reserved area the thickness of the photoresist portion.
3. 根据权利要求1所述的阵列基板制备方法,其特征在于,在完成所述步骤S20之后,且在进行所述步骤S30之前,还包括半色调掩膜工艺,其包括W下步骤: S21,在所述第一金属氧化层上涂布光刻胶; S22,采用半色调掩膜版对所述第一金属氧化层进行图案化工艺,在此过程中,保留形成源漏电极之间的沟道区所对应区域的部分厚度的光刻胶。 The method of fabricating an array substrate according to claim 1, wherein, after completion of the step S20, the previous and performing the step S30, the process further comprising a half-tone mask, which comprises the step of W: S21 coating a photoresist on the first metal oxide layer; S22, using a half-tone mask for the first metal oxide layer patterning process, in this process, the source drain electrode is formed to retain the the thickness of the photoresist portions corresponding to the region of the channel region.
4. 根据权利要求3所述的阵列基板制备方法,其特征在于,在完成所述步骤S30之后,还包括源漏电极制备工艺,其包括W下步骤: S40,在所述第二金属氧化层上制备源漏金属层; S50,同时对所述第二金属氧化层和所述源漏金属层进行图案化工艺,W形成所述沟道区,并去除所述沟道区所对应区域的所述部分厚度的光刻胶。 4. After the array substrate production method according to claim 3, wherein, after completion of the step S30, the source and drain electrodes further comprises a preparation process comprising the steps of W: S40, the second metal oxide layer preparation of the source-drain metal layer; S50, while the second metal oxide layer and the source-drain metal layer patterning process, W forming the channel region, the channel region is removed and the corresponding region of said portion of the photoresist thickness.
5. 根据权利要求2所述的阵列基板制备方法,其特征在于,在完成所述步骤S32之后,还包括源漏电极制备工艺,其包括W下步骤: S40,在所述第二金属氧化层上制备源漏金属层; S50,对所述源漏金属层进行图案化工艺,W形成所述沟道区,并去除所述沟道区所对应区域的所述部分厚度的光刻胶。 The method of fabricating an array substrate according to claim 2, wherein, after completion of the step S32, the source and drain electrodes further comprises a preparation process comprising the steps of W: S40, the second metal oxide layer preparation of the source-drain metal layer; S50, the source-drain metal layer patterning process, W the channel region is formed, the photoresist is removed and the portion corresponding to the thickness of the region of the channel region.
6. 根据权利要求1-5任意一项所述的阵列基板制备方法,其特征在于,所述第一金属氧化层的厚度为400…600备。 The array substrate production method according to any one of claims 1-5, characterized in that the thickness of the first metal oxide layer is 400 ... 600 prepared.
7. 根据权利要求1-5任意一项所述的阵列基板制备方法,其特征在于,所述第二金属氧化层的厚度为30~50 A。 The array substrate production method according to any one of claims 1-5, characterized in that the thickness of the second metal oxide layer is 30 ~ 50 A.
8. 根据权利要求1-5任意一项所述的阵列基板制备方法,其特征在于,所述第一金属氧化层和第二金属氧化层采用相同的材料。 8. A method of fabricating an array substrate according to any one of claims 1 to 5, wherein the first metal oxide layer and the second metal oxide layer is made of the same material.
9. 根据权利要求8所述的阵列基板制备方法,其特征在于,所述第一金属氧化层和第二金属氧化层所采用的材料包括化〇、In化0、化SnO或者Zrin化0。 9. A method of fabricating an array substrate according to claim 8, characterized in that the material of the first metal oxide layer and the second metal oxide layer is employed comprising of square, In of 0, 0 of the SnO or Zrin.
10. -种阵列基板,包括设置在栅绝缘层上的有源层,其特征在于,所述有源层包括: 经过退火工艺的第一金属氧化层;W及设置在所述第一金属氧化层上,且未经退火工艺的第二金属氧化层。 10. - kind of array substrate, including an active layer disposed on the gate insulating layer, wherein the active layer comprises: a first metal oxide layer after the annealing process; and W is disposed in said first metal oxide upper layer without annealing the second metal oxide layer.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101800249A (en) * 2009-02-05 2010-08-11 株式会社半导体能源研究所 Transistor and method for manufacturing the transistor
CN104091784A (en) * 2014-07-11 2014-10-08 合肥鑫晟光电科技有限公司 Array substrate manufacturing method
CN105826250A (en) * 2016-05-17 2016-08-03 京东方科技集团股份有限公司 Thin film transistor, array substrate, display device, and thin film transistor making method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101800249A (en) * 2009-02-05 2010-08-11 株式会社半导体能源研究所 Transistor and method for manufacturing the transistor
CN104091784A (en) * 2014-07-11 2014-10-08 合肥鑫晟光电科技有限公司 Array substrate manufacturing method
CN105826250A (en) * 2016-05-17 2016-08-03 京东方科技集团股份有限公司 Thin film transistor, array substrate, display device, and thin film transistor making method

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