CN106026692A - 半导体模块、电力变换装置以及半导体模块的制造方法 - Google Patents
半导体模块、电力变换装置以及半导体模块的制造方法 Download PDFInfo
- Publication number
- CN106026692A CN106026692A CN201610172274.8A CN201610172274A CN106026692A CN 106026692 A CN106026692 A CN 106026692A CN 201610172274 A CN201610172274 A CN 201610172274A CN 106026692 A CN106026692 A CN 106026692A
- Authority
- CN
- China
- Prior art keywords
- electrode terminal
- terminal
- electrode
- semiconductor module
- anode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/045—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads having an insulating passage through the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/37124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/40139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/40227—Connecting the strap to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45599—Material
- H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45624—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45599—Material
- H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45644—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/842—Applying energy for connecting
- H01L2224/84201—Compression bonding
- H01L2224/84205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/115—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1027—IV
- H01L2924/10272—Silicon Carbide [SiC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/1033—Gallium nitride [GaN]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Inverter Devices (AREA)
- Ceramic Engineering (AREA)
Abstract
半导体模块(10)具有第1电极端子(1)、第2电极端子(2)、第3电极端子(3)、第4电极端子(4)、第5电极端子(5)以及第6电极端子(6)。第1电极端子及第2电极端子沿第1方向(A1)配置。第3电极端子、第4电极端子、第5电极端子以及第6电极端子沿与第1方向(A1)垂直的第2方向(A2)配置。第1电极端子(1)配置于第1方向(A1)和第2方向(A2)相交叉的位置。第4电极端子(4)、第5电极端子(5)及第6电极端子(6)是交流输出端子或交流输入端子。第1电极端子(1)是阳极端子及阴极端子中的一方。第2电极端子(2)及第3电极端子(3)中的至少任意一方是阳极端子及阴极端子中的另一方。
Description
技术领域
本发明涉及半导体模块、电力变换装置以及半导体模块的制造方法,特别地,涉及具有电极端子的半导体模块、电力变换装置以及半导体模块的制造方法。
背景技术
当前,已知将直流电力变换为三相(U相、V相、W相)的交流电力的半导体模块。该半导体模块具有与直流电源连接的阳极端子及阴极端子、与U相、V相及W相各相对应的交流输出端子(例如参照日本特开2008-029052号公报、日本特开2008-166421号公报以及日本特开2013-055739号公报)。根据日本特开2008-029052号公报中记载的半导体模块,阳极端子、阴极端子、与U相、V相及W相各相对应的交流输出端子配置于一条直线上(以下将该电极端子配置称为一列型配置)。根据日本特开2008-166421号公报中记载的半导体模块,设置端子的壳体的形状是大致长方形状。与U相、V相及W相各相对应的交流输出端子配置于大致长方形的形状的长边侧,阳极端子及阴极端子配置于短边侧(以下将该电极端子配置称为L字型配置)。
在一列型配置的情况下,阳极端子及阴极端子沿壳体的长边方向配置。另一方面,在L字型配置的情况下,阳极端子及阴极端子沿壳体的短边方向配置。即,在一列型配置及L字型配置中的任意者的情况下,阳极端子及阴极端子均仅配置于长边方向侧或短边方向侧。例如为了与外部设备连接,有时使电极(汇流条)与半导体模块的端子连接。考虑到半导体模块的阳极端子及阴极端子的配置而对汇流条进行设计。具体地说,如果将电源与阳极端子或阴极端子相连的汇流条变长,则电感增加。如果电感增加,则通断动作时的电压浪涌变大。因此,以使汇流条的全长变短的方式而对汇流条进行设计。但是,例如在使用汇流条而将一列型配置的半导体模块和L字型配置的半导体模块连接的情况下,在一列型配置和L字型配置中,阳极端子或阴极端子的配置不同。因此,为了使汇流条的全长变短,例如需要以使一列型配置的半导体模块的短边侧与L字型配置的半导体模块的长边侧相对的方式进行配置等。即,例如在使用汇流条而将不同端子排列的半导体模块电连接的情况下,各半导体模块的配置受到限制。
发明内容
本发明就是鉴于上述课题而提出的,其目的在于,提供能够提高半导体模块的配置的自由度的半导体模块、电力变换装置以及半导体模块的制造方法。
本发明所涉及的半导体模块具有第1电极端子、第2电极端子、第3电极端子、第4电极端子、第5电极端子以及第6电极端子。第1电极端子及第2电极端子沿第1方向配置。第3电极端子、第4电极端子、第5电极端子和第6电极端子沿与第1方向垂直的第2方向配置。第1电极端子配置于第1方向和第2方向相交叉的位置。第4电极端子、第5电极端子及第6电极端子是交流输出端子或交流输入端子。第1电极端子是阳极端子及阴极端子中的一方。第2电极端子及第3电极端子中的至少任意一方是阳极端子及阴极端子中的另一方。
本发明所涉及的半导体模块的制造方法具有以下工序。准备设置有第1电极端子、第2电极端子、第3电极端子、第4电极端子、第5电极端子、第6电极端子以及内部电路的台座部,该第1电极端子及第2电极端子沿第1方向配置,该第3电极端子、第4电极端子、第5电极端子和第6电极端子沿与第1方向垂直的第2方向配置。第1电极端子配置于第1方向和第2方向相交叉的位置。第4电极端子、第5电极端子及第6电极端子是交流输出端子或交流输入端子。第1电极端子是阳极端子及阴极端子中的一方。第2电极端子及第3电极端子中的至少任意一方是阳极端子及阴极端子中的另一方。第2电极端子与第3电极端子电绝缘。第2电极端子及第3电极端子中的至少任意一方与内部电路电连接。
根据与附图关联地进行理解的、关于本发明的以下详细说明,会使得本发明的上述以及其他目的、特征、方案以及优点变清楚。
附图说明
图1是概略地表示实施方式1~3所涉及的半导体模块的结构的斜视图。
图2是概略地表示实施方式1~3所涉及的半导体模块的结构的俯视图。
图3是概略地表示实施方式1~3所涉及的半导体模块的电路结构的电路图。
图4是概略地表示实施方式4所涉及的电力变换装置的结构的斜视图。
图5是概略地表示实施方式5所涉及的电力变换装置的第1例的电路图。
图6是概略地表示实施方式5所涉及的电力变换装置的第2例的电路图。
图7是概略地表示实施方式6所涉及的半导体模块的制造方法的流程图。
图8是概略地表示实施方式6所涉及的半导体模块的制造方法的第1工序的俯视图。
图9是概略地表示实施方式6所涉及的半导体模块的制造方法的第2工序的第1例的俯视图。
图10是概略地表示实施方式6所涉及的半导体模块的制造方法的第2工序的第2例的俯视图。
图11是概略地表示实施方式6所涉及的半导体模块的制造方法的第2工序的第3例的俯视图。
具体实施方式
下面,基于附图,说明本发明的实施方式。此外,在以下的附图中,对相同或者相当的部分标注相同的参照编号,不重复其说明。
(实施方式1)
参照图1~图3,说明本发明的实施方式1所涉及的半导体模块的结构。实施方式1所涉及的半导体模块10主要具有第1电极端子1、第2电极端子2、第3电极端子3、第4电极端子4、第5电极端子5、第6电极端子6、台座部7以及连接部8。如图2所示,第1电极端子1及第2电极端子2沿第1方向A1配置。第3电极端子3、第4电极端子4、第5电极端子5以及第6电极端子6沿与第1方向A1垂直的第2方向A2配置。第1电极端子1配置于第1方向A1和第2方向A2相交叉的位置。
如图2所示,在俯视观察时(从与由第1方向A1和第2方向A2所形成的平面垂直的方向进行观察的情况下),台座部7是细长形状,具体地说,是大致长方形的形状。第1方向A1是长方形的短边的方向。第2方向A2是长方形的长边的方向。如图1所示,第1电极端子1、第2电极端子2、第3电极端子3、第4电极端子4、第5电极端子5以及第6电极端子6设置于台座部7之上。第1电极端子1、第2电极端子2、第3电极端子3、第4电极端子4、第5电极端子5以及第6电极端子6设置于同一平面上。第1电极端子1、第2电极端子2、第3电极端子3、第4电极端子4、第5电极端子5以及第6电极端子6彼此在物理上分离。也可以是第1电极端子1和第2电极端子2之间的距离大于第1电极端子1和第3电极端子3之间的距离。
如图1及图2所示,第1电极端子1、第2电极端子2以及第6电极端子6设置于台座部7的表面的角部。详细地说,第1电极端子1及第2电极端子2分别设置于第1方向A1上的一侧及另一侧的角部。第1电极端子1及第6电极端子6分别设置于第2方向A2上的一侧及另一侧的角部。第3电极端子3、第4电极端子4以及第5电极端子5设置于第1电极端子1和第6电极端子6之间。第3电极端子3设置于第1电极端子1旁边,第5电极端子5设置于第6电极端子6旁边。第4电极端子4设置于第3电极端子3及第5电极端子5之间。在各电极端子1~6的中央附近,也可以设置有在俯视观察时为圆形的凹陷部。连接部8设置于台座部7之上。也可以沿穿过第2电极端子2、且与第2方向A2平行的方向设置有多个连接部8。连接部8与例如对栅极进行驱动的电路连接。此外,在图2及其后的附图中,为了简化,省略连接部8的记载。
参照图3,半导体模块10例如是逆变器。半导体模块10还具有晶体管及二极管等半导体元件。具体地说,半导体模块10例如具有开关元件S1~S6及二极管D1~D6。开关元件S1~S6例如是IGBT(Insulated Gate Bipolar Transistor)等。二极管D1~D6例如是续流二极管。优选半导体元件由与硅相比带隙较大的宽带隙半导体构成。作为宽带隙半导体,例如存在氮化镓或碳化硅等。如图3所示,IGBT等半导体元件例如与第1电极端子1及第2电极端子2各自电连接。
如图3所示,开关元件S1和二极管D1并联连接,构成第1桥臂开关部。同样地,开关元件S2和二极管D2并联连接,构成第2桥臂开关部。第1桥臂开关部及第2桥臂开关部的连接点与第6电极端子6连接。第6电极端子6例如是W相的输出端子。同样地,开关元件S3和二极管D3并联连接,构成第3桥臂开关部。同样地,开关元件S4和二极管D4并联连接,构成第4桥臂开关部。第3桥臂开关部及第4桥臂开关部的连接点与第5电极端子5连接。第5电极端子5例如是V相的输出端子。同样地,开关元件S5和二极管D5并联连接,构成第5桥臂开关部。同样地,开关元件S6和二极管D6并联连接,构成第6桥臂开关部。第5桥臂开关部及第6桥臂开关部的连接点与第4电极端子4连接。第4电极端子4例如是U相的输出端子。
在上述中,说明了第4电极端子4是U相的交流输出端子、第5电极端子5是V相的交流输出端子、第6电极端子6是W相的交流输出端子的情况,但各端子不限定于上述各相的结构。例如,第4电极端子4、第5电极端子5及第6电极端子6可以分别是V相、W相及U相的交流输出端子,可以分别是W相、U相及V相的交流输出端子,可以是U相、W相及V相的交流输出端子,可以是V相、U相及W相的交流输出端子,可以是W相、V相及U相的交流输出端子。第4电极端子4、第5电极端子5以及第6电极端子6能够与电动机等负载12连接。
第1电极端子1例如能够与直流电源11的阳极(P侧)连接。换言之,第1电极端子1是阳极输入端子。第1电极端子1与第1桥臂开关部、第3桥臂开关部以及第5桥臂开关部连接。同样地,第2电极端子2例如能够与直流电源11的阴极(N侧)连接。换言之,第2电极端子2是阴极输入端子。第2电极端子2与第2桥臂开关部、第4桥臂开关部以及第6桥臂开关部连接。
再次参照图2,也可以构成为,第1电极端子1能够与直流电源11的阳极(P侧)连接,第2电极端子2能够与直流电源11的阴极(N型)连接,且第3电极端子3是能够与制动电路(未图示)连接的输出端子。作为替代,也可以构成为,第1电极端子1能够与直流电源11的阴极(N侧)连接,第2电极端子2能够与直流电源11的阳极(P型)连接,且第3电极端子3是能够与制动电路连接的输出端子。作为替代,也可以构成为,第1电极端子1能够与直流电源11的阳极(P侧)连接,第3电极端子3能够与直流电源11的阴极(N型)连接,且第2电极端子2是能够与制动电路连接的输出端子。作为替代,也可以构成为,第1电极端子1能够与直流电源11的阴极(N侧)连接,第3电极端子3能够与直流电源11的阳极(P型)连接,且第2电极端子2是能够与制动电路连接的输出端子。即,第1电极端子1是直流阳极端子及直流阴极端子中的一方。第2电极端子2及第3电极端子3中的一方是直流阳极端子及直流阴极端子中的另一方。第2电极端子2及第3电极端子3中的另一方是制动输出端子等输出端子。也可以构成为,第2电极端子2及第3电极端子3中的至少任意一方和第1电极端子1是直流输入端子。
下面,说明本发明的实施方式1所涉及的半导体模块的作用效果。
根据实施方式1所涉及的半导体模块10,第1电极端子1及第2电极端子2沿第1方向A1配置。第3电极端子3、第4电极端子4、第5电极端子5以及第6电极端子6沿与第1方向A1垂直的第2方向A2配置。第1电极端子1配置于第1方向A1和第2方向A2相交叉的位置。第4电极端子4、第5电极端子5及第6电极端子6是交流输出端子。第1电极端子1是阳极端子及阴极端子中的一方。第2电极端子2及第3电极端子3中的至少任意一方是阳极端子及阴极端子中的另一方。由此,既能够沿第1方向A1配置阳极端子及阴极端子,也能够沿第2方向A2配置阳极端子及阴极端子。因此,能够提高半导体模块的配置的自由度。另外,能够提高汇流条的设计的自由度。由此,能够缩短半导体模块的设计期间。另外,能够实现半导体模块的标准化。
另外,根据实施方式1所涉及的半导体模块10,第4电极端子4、第5电极端子5及第6电极端子6是交流输出端子。第2电极端子2及第3电极端子3中的至少任意一方和第1电极端子1是直流输入端子。由此,能够提高例如逆变器等所利用的半导体模块10的配置的自由度。
并且,根据实施方式1所涉及的半导体模块10,第2电极端子2及第3电极端子3中的一方是阳极端子及阴极端子中的另一方。第2电极端子2及第3电极端子3的另一方是输出端子。由此,第2电极端子2及第3电极端子3中的另一方能够作为制动用端子等输出端子有效地进行利用。
并且,根据实施方式1所涉及的半导体模块10,还具有与第1电极端子电连接的半导体元件。半导体元件由与硅相比带隙较大的宽带隙半导体构成。SiC及GaN等宽带隙半导体与硅半导体相比,高速通断时的损耗低,高温耐受量优异。因此,大多以比硅半导体装置所使用的条件更高的频率(高速通断条件)使用。在以高速通断条件来使用的情况下,由于dV/dt变高,因此要求降低浪涌电压。通过利用上述半导体模块10的端子配置,从而半导体模块的配置的自由度变高。其结果,用于降低浪涌的缓冲器的配置的自由度变高。因此,实施方式1所涉及的半导体模块适用于半导体元件由宽带隙半导体构成的情况。
(实施方式2)
下面,说明本发明的实施方式2所涉及的半导体模块的结构。实施方式2所涉及的半导体模块主要在第2电极端子2及第3电极端子3这两者为直流阳极端子或直流阴极端子这一点上与实施方式1所涉及的半导体模块不同,其他结构与实施方式1所涉及的半导体模块大致相同。
参照图1及图2,也可以构成为,第1电极端子1、第2电极端子2以及第3电极端子3能够与直流电源11连接。具体地说,第1电极端子1能够与直流电源11的阳极(P侧)连接,第2电极端子2及第3电极端子3能够与直流电源11的阴极(N侧)连接。换言之,第1电极端子1是直流的阳极输入端子,且第2电极端子2及第3电极端子3是直流的阴极输入端子。作为替代,也可以构成为,第1电极端子1能够与直流电源11的阴极(N侧)连接,第2电极端子2及第3电极端子3能够与直流电源11的阳极(P侧)连接。换言之,也可以构成为,第1电极端子1是直流的阴极输入端子,且第2电极端子2及第3电极端子3是直流的阳极输入端子。第2电极端子2及第3电极端子3成为相同电位。
作为替代,也可以构成为,第1电极端子1是直流的阳极输出端子,且第2电极端子2及第3电极端子3是直流的阴极输出端子。作为替代,也可以构成为,第1电极端子1是直流的阴极输出端子,且第2电极端子2及第3电极端子3是直流的阳极输出端子。即,第1电极端子1是直流阳极端子及直流阴极端子中的一方,第2电极端子及第3电极端子这两者是直流阳极端子及直流阴极端子中的另一方。
根据实施方式2所涉及的半导体模块10,第2电极端子及第3电极端子这两者是阳极端子及阴极端子中的另一方。由此,例如与主电源连接的阳极端子及阴极端子配置于第1方向A1和第2方向A2这2个方向上。能够提高汇流条的设计的自由度。另外,能够提高半导体模块的配置的自由度。
(实施方式3)
下面,说明本发明的实施方式3所涉及的半导体模块的结构。实施方式3所涉及的半导体模块主要在第2电极端子2及第3电极端子3中的一方是非连接端子这一点上与实施方式1所涉及的半导体模块不同,其他结构与实施方式1所涉及的半导体模块大致相同。
参照图1及图2,也可以构成为,第2电极端子2及第3电极端子3中的一方是未与直流电源11连接的端子,且第2电极端子2及第3电极端子3中的另一方是与直流电源11连接的端子。例如,第1电极端子1能够与直流电源11的阳极(P侧)连接,第2电极端子2能够与直流电源11的阴极(N侧)连接,第3电极端子3未与直流电源11连接。换言之,第1电极端子1是直流的阳极输入端子,第2电极端子2是直流的阴极输入端子,第3电极端子3是非连接端子。非连接端子与除非连接端子以外的任何端子均不连接。即,非连接端子成为被相对于半导体模块内的电位绝缘的电位(浮动电位)。
作为替代,也可以构成为,第1电极端子1是直流的阴极输入端子,第2电极端子2是直流的阳极输入端子,第3电极端子3是非连接端子。作为替代,也可以构成为,第1电极端子1是直流的阴极输入端子,第3电极端子3是直流的阳极输入端子,第2电极端子2是非连接端子。作为替代,也可以构成为,第1电极端子1是直流的阳极输入端子,第3电极端子3是直流的阴极输入端子,第2电极端子2是非连接端子。
作为替代,也可以构成为,第1电极端子1是直流的阳极输出端子,第2电极端子2是直流的阴极输出端子,第3电极端子3是非连接端子。作为替代,也可以构成为,第1电极端子1是直流的阴极输出端子,第2电极端子2是直流的阳极输出端子,第3电极端子3是非连接端子。作为替代,也可以构成为,第1电极端子1是直流的阴极输出端子,第3电极端子3是直流的阳极输出端子,第2电极端子2是非连接端子。作为替代,也可以构成为,第1电极端子1是直流的阳极输出端子,第3电极端子3是直流的阴极输出端子,第2电极端子2是非连接端子。即,在实施方式3中,第1电极端子1是阳极端子及阴极端子中的一方。第2电极端子2及第3电极端子3中的一方是阳极端子及阴极端子中的另一方。第2电极端子2及第3电极端子3中的另一方是非连接端子。
根据实施方式3所涉及的半导体模块10,第2电极端子及第3电极端子中的一方是阳极端子及阴极端子中的另一方。第2电极端子及第3电极端子中的另一方是非连接端子。非连接端子与其他端子电绝缘。因此,非连接端子能够用作对半导体模块进行控制的电路基板或电子部件等的机械构造式支撑台。通过增加对框体构造进行支撑的部件,从而框体构造变得牢固。
(实施方式4)
下面,说明本发明的实施方式4所涉及的电力变换装置的结构。实施方式4所涉及的电力变换装置100具有至少1个例如实施方式1~3所记载的半导体模块10。
如图4所示,电力变换装置100例如主要具有第1半导体模块10a、第2半导体模块10b、第3半导体模块10c、第4半导体模块10d、第1汇流条14以及第2汇流条15。第1半导体模块10a、第2半导体模块10b以及第3半导体模块10c沿台座部7的长度方向配置。第4半导体模块10d以第4半导体模块10d的宽度方向与第1半导体模块10a的长度方向平行的方式配置。换言之,以与第1半导体模块10a的长边相对的方式设置。第4半导体模块10d以第4半导体模块10d的短边与第1半导体模块10a的长边相对的方式设置。
第1汇流条14及第2汇流条15是板状的电极配线。第1汇流条14及第2汇流条15例如构成为,能够将电力供给至第1电极端子1、第2电极端子2以及第3电极端子3。第1半导体模块10a的第1电极端子1、第2半导体模块10b的第1电极端子1、第3半导体模块10c的第1电极端子1以及第4半导体模块10d的第1电极端子1通过第1汇流条14而电连接。同样地,第1半导体模块10a的第3电极端子3、第2半导体模块10b的第3电极端子3、第3半导体模块10c的第3电极端子3以及第4半导体模块10d的第2电极端子2通过第2汇流条15而电连接。第1电极端子1例如是阳极端子。第2电极端子2及第3电极端子3例如是阴极端子。以上述方式,通过将第2汇流条15与第4半导体模块10d的第2电极端子2相连、而不与第4半导体模块10d的第3电极端子3相连,从而能够缩短第2汇流条15的全长。
(实施方式5)
下面,说明本发明的实施方式5所涉及的电力变换装置的结构。实施方式5所涉及的电力变换装置100具有至少1个例如实施方式1~3所记载的半导体模块10。电力变换装置100例如是逆变器装置、转换器装置、伺服放大器或电源单元。
如图5所示,所涉及的电力变换装置100例如主要具有第5半导体模块10e、第6半导体模块10f、A-D变换器16、集成电路17、绝缘电路18、集成电路19、第3汇流条24以及第4汇流条25。第5半导体模块10e例如是转换器。第5半导体模块10e具有二极管D8~D13。二极管D8和二极管D9的连接点与第6电极端子6连接。第6电极端子6例如是T相的输入端子。二极管D10和二极管D11的连接点与第5电极端子5连接。第5电极端子5例如是S相的输入端子。二极管D12和二极管D13的连接点与第4电极端子4连接。第4电极端子4例如是R相的输入端子。第4电极端子4、第5电极端子5以及第6电极端子6设置为能够与交流电源11连接。
在上述中,说明了第4电极端子4是R相的交流输入端子、第5电极端子5是S相的交流输入端子、第6电极端子6是T相的交流输入端子的情况,但各端子不限定于上述各相的结构。例如,第4电极端子4、第5电极端子5及第6电极端子6可以分别是S相、T相及R相的交流输入端子,可以分别是T相、R相及S相的交流输入端子,可以是R相、T相及S相的交流输入端子,可以是S相、R相及T相的交流输入端子,可以是T相、S相及R相的交流输入端子。
第1电极端子1及第2电极端子2构成为能够输出直流。第1电极端子1例如是阳极输出端子。第1电极端子1与二极管D8、二极管D10以及二极管D12连接。第2电极端子2例如是阴极输出端子。第2电极端子2与二极管D9、二极管D11以及二极管D13连接。也可以取代第2电极端子2而将第3电极端子3与二极管D9、二极管D11以及二极管D13连接,还可以将第2电极端子2及第3电极端子3这两者与二极管D9、二极管D11、二极管D13连接。即,也可以构成为,第2电极端子及第3电极端子中的至少任意一方和第1电极端子是直流输出端子。
如图5所示,第6半导体模块10f例如具有逆变器电路以及制动电路。逆变器电路与实施方式1中说明的结构大致相同。制动电路具有二极管D7以及开关元件S7。二极管D7与第1电极端子1连接。开关元件S7与第2电极端子2连接。在第6半导体模块10f中,也可以设置有制动电路的输出电极端子。电流传感器13构成为能够对交流电流进行检测。电流传感器13例如设置于将第6电极端子6和电动机等负载12相连的配线。电流传感器13例如也可以设置于将第5电极端子5和电动机等负载12相连的配线。电流传感器13所检测出的信号被发送至A-D变换器16。利用A-D变换器16,对电流传感器13所检测出的信号进行A-D变换。A-D变换后的信号被发送至集成电路17。集成电路17例如是微型计算机/DSP(DigitalSignal Processor)。集成电路17与绝缘电路18连接。绝缘电路18与集成电路19连接。集成电路19是驱动-保护电路。集成电路19例如对开关元件S1~S7的栅极进行控制。
如图5所示,第5半导体模块10e的第1电极端子1通过第3汇流条24而与第6半导体模块10f的第1电极端子1连接。同样地,第5半导体模块10e的第2电极端子2通过第4汇流条25而与第6半导体模块10f的第2电极端子2连接。如图5所示,第5半导体模块10e的第1电极端子1及第2电极端子2是直流输出端子,第4电极端子4、第5电极端子5及第6电极端子6是交流输入端子。另一方面,第6半导体模块10f的第1电极端子1及第2电极端子2是直流输入端子,第4电极端子4、第5电极端子5及第6电极端子6是交流输出端子。
在第4电极端子4、第5电极端子5及第6电极端子6是交流输入端子的情况下,第1电极端子1是阳极输出端子及阴极输出端子中的一方,第2电极端子2及第3电极端子3中的至少任意一方是阳极输出端子及阴极输出端子中的另一方。在第4电极端子4、第5电极端子5及第6电极端子6是交流输出端子的情况下,第1电极端子1是阳极输入端子及阴极输入端子中的一方,第2电极端子2及第3电极端子3中的至少任意一方是阳极输入端子及阴极输入端子中的另一方。
如图6所示,电力变换装置100也可以还具有第7半导体模块10g。由于第7半导体模块10g的结构与第6半导体模块10f的结构大致相同,因此省略详细的说明。第5半导体模块10e的第1电极端子1通过第3汇流条24而与第6半导体模块10f的第1电极端子1、第7半导体模块10g的第1电极端子1连接。同样地,第5半导体模块10e的第2电极端子2、第6半导体模块10f的第2电极端子2、第7半导体模块10g的第2电极端子2通过第4汇流条25而连接。
根据实施方式5中的第5半导体模块10e,第4电极端子4、第5电极端子5及第6电极端子6是交流输入端子。第2电极端子2及第3电极端子3中的至少任意一方和第1电极端子1是直流输出端子。由此,能够提高例如转换器等所利用的半导体模块10的配置的自由度。
另外,根据实施方式5所涉及的电力变换装置100,由于多个半导体模块10各自的配置的自由度高,因此能够将多个半导体模块10紧凑地配置。其结果,能够将电力变换装置100小型化。另外,通过将汇流条的配置最优化,从而能够抑制电感的增加。由此,由于不必追加用于对电压浪涌进行抑制的缓冲器,因此能够将电力变换装置100进一步小型化。
(实施方式6)
下面,说明半导体模块的制造方法的一个例子。
首先,实施台座部准备工序(S10:图7)。参照图8,准备设置有第1电极端子1、第2电极端子2、第3电极端子3、第4电极端子4、第5电极端子5、第6电极端子6以及内部电路40的台座部(壳体)。第1电极端子1及第2电极端子2沿第1方向A1配置。第3电极端子3、第4电极端子4、第5电极端子5以及第6电极端子6沿与第1方向A1垂直的第2方向A2配置。第1电极端子1配置于第1方向A1和第2方向A2相交叉的位置。
第4电极端子4、第5电极端子5及第6电极端子6例如是交流输出端子。第4电极端子4、第5电极端子5及第6电极端子6也可以是交流输入端子。第1电极端子1是阳极端子及阴极端子中的一方。第2电极端子2及第3电极端子3中的至少任意一方是阳极端子及阴极端子中的另一方。各电极端子1~6被电绝缘。具体地说,第2电极端子2与第3电极端子3电绝缘。同样地,第2电极端子2与第1电极端子1电绝缘。同样地,第1电极端子1与第3电极端子3电绝缘。
如图8所示,内部电路40例如主要具有配线20、21、22、开关元件S1、S2、二极管D1、D2以及基板39。配线20、21、22以彼此分离的方式配置于基板39之上。开关元件S1和二极管D1配置于配线21之上。开关元件S2和二极管D2配置于配线22之上。
然后,实施端子连接工序(S20:图7)。具体地说,如图9所记载,使各电极端子1~6与内部电路40连接。参照图9,使用导线32,使第1电极端子1与配线21连接。使用导线31,使第2电极端子2与配线20连接。第3电极端子3未与其他的任何电极端子连接。第3电极端子3未与内部电路40连接。换言之,第3电极端子3被用作非连接端子。使用导线37,使第4电极端子4与配线22连接。使用导线36,使配线22与二极管D1连接。使用导线35,使二极管D1与开关元件S1连接。使用导线33,使配线20与二极管D2连接。使用导线34,使二极管D2与开关元件S2连接。第1电极端子1及第2电极端子2被用作直流输入端子。第1电极端子1被用作阳极端子,第2电极端子2被用作阴极端子。第4电极端子4、第5电极端子5及第6电极端子6被用作交流输出端子。
在端子连接工序(S20:图7)中,也可以如图10所示使各电极端子1~6与内部电路40连接。参照图10,使用导线32,使第1电极端子1与配线21连接。使用导线38,使第3电极端子3与配线20连接。第2电极端子2未与其他的任何电极端子连接。第2电极端子2未与内部电路40连接。换言之,第2电极端子2被用作非连接端子。第1电极端子1及第3电极端子3被用作直流输入端子。第1电极端子1被用作阳极端子,第3电极端子3被用作阴极端子。第4电极端子4、第5电极端子5及第6电极端子6被用作交流输出端子。其他结构与图9中说明的结构相同。
在端子连接工序(S20:图7)中,也可以如图11所示使各电极端子1~6与内部电路40连接。参照图11,使用导线32,使第1电极端子1与配线21连接。使用导线38,使第3电极端子3与配线20连接。使用导线31,使第2电极端子2与配线20连接。第1电极端子1、第2电极端子2及第3电极端子3被用作直流输入端子。第1电极端子1被用作阳极端子,第2电极端子2及第3电极端子3被用作阴极端子。第4电极端子4、第5电极端子5及第6电极端子6被用作交流输出端子。其他结构与图9中说明的结构相同。
此外,将各电极端子1~6和内部电路40电连接的导线例如也可以由铝或金等材料构成。另外,也可以取代导线而使用金属板等。关于各部件的接合,既可以以上述方式通过导线键合进行,也可以通过焊料接合进行,还可以通过超声波接合进行。
如图9~图11所示,根据实施方式6所涉及的半导体模块10的制造方法,第2电极端子2及第3电极端子3中的至少任意一方与内部电路40电连接。即,既可以是仅第2电极端子2及第3电极端子3中的一方与内部电路40连接,也可以是这两者与内部电路40连接。换言之,选择性地进行第2电极端子2及第3电极端子3与内部电路40的连接。第2电极端子2及第3电极端子3各自以能够与内部电路40连接的方式设置于台座部7之上即可,既可以与内部电路40连接,也可以不连接。以上述方式,第2电极端子2及第3电极端子3在台座部7内被电绝缘。在半导体模块10的组装阶段,选择性地进行第2电极端子2及第3电极端子3与内部电路40的电连接或非连接。即,通过使用图8所示的一个构造体,在组装阶段对导线的连接进行变更,从而能够制作图9~图11所示的3种类型的半导体模块10。以上述方式,能够将组装阶段前的构造体共通化,从而能够简化半导体模块10的部件管理。另外,能够将半导体模块10的制造工序共通化。由此,能够缩短半导体模块10的制造的生产节拍。
对本发明的实施方式进行了说明,但应该理解为,本次公开的实施方式在所有方面均为例示,且非限制性文字。本发明的范围由权利要求书示出,旨在包含与权利要求书同等的含义以及范围内的所有变更。
Claims (9)
1.一种半导体模块,其具有:
第1电极端子及第2电极端子,它们沿第1方向配置;以及
第3电极端子、第4电极端子、第5电极端子和第6电极端子,它们沿与所述第1方向垂直的第2方向配置,
所述第1电极端子配置于所述第1方向和所述第2方向相交叉的位置,
所述第4电极端子、所述第5电极端子及所述第6电极端子是交流输出端子或交流输入端子,
所述第1电极端子是阳极端子及阴极端子中的一方,
所述第2电极端子及所述第3电极端子中的至少任意一方是所述阳极端子及所述阴极端子中的另一方。
2.根据权利要求1所述的半导体模块,其中,
所述第4电极端子、所述第5电极端子及所述第6电极端子是交流输出端子,
所述第2电极端子及所述第3电极端子中的至少任意一方和所述第1电极端子是直流输入端子。
3.根据权利要求1所述的半导体模块,其中,
所述第2电极端子及所述第3电极端子中的一方是所述阳极端子及所述阴极端子中的另一方,且所述第2电极端子及所述第3电极端子中的另一方是输出端子。
4.根据权利要求1所述的半导体模块,其中,
所述第2电极端子及所述第3电极端子这两者是所述阳极端子及所述阴极端子中的另一方。
5.根据权利要求1所述的半导体模块,其中,
所述第2电极端子及所述第3电极端子中的一方是所述阳极端子及所述阴极端子中的另一方,且所述第2电极端子及所述第3电极端子中的另一方是非连接端子。
6.根据权利要求1所述的半导体模块,其中,
还具有半导体元件,该半导体元件与所述第1电极端子电连接,
所述半导体元件由与硅相比带隙较大的宽带隙半导体构成。
7.根据权利要求1所述的半导体模块,其中,
所述第4电极端子、所述第5电极端子及所述第6电极端子是交流输入端子,
所述第2电极端子及所述第3电极端子中的至少任意一方和所述第1电极端子是直流输出端子。
8.一种电力变换装置,其具有至少1个权利要求1所述的半导体模块。
9.一种半导体模块的制造方法,其具有准备设置有第1电极端子、第2电极端子、第3电极端子、第4电极端子、第5电极端子、第6电极端子以及内部电路的台座部的工序,该第1电极端子及第2电极端子沿第1方向配置,该第3电极端子、第4电极端子、第5电极端子和第6电极端子沿与所述第1方向垂直的第2方向配置,
所述第1电极端子配置于所述第1方向和所述第2方向相交叉的位置,
所述第4电极端子、所述第5电极端子及所述第6电极端子是交流输出端子或交流输入端子,
所述第1电极端子是阳极端子及阴极端子中的一方,
所述第2电极端子及所述第3电极端子中的至少任意一方是所述阳极端子及所述阴极端子中的另一方,
所述第2电极端子与所述第3电极端子电绝缘,
该半导体模块的制造方法还具有下述工序,即,
将所述第2电极端子及所述第3电极端子中的至少任意一方与所述内部电路电连接。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015060348A JP6362560B2 (ja) | 2015-03-24 | 2015-03-24 | 半導体モジュール、電力変換装置および半導体モジュールの製造方法 |
JP2015-060348 | 2015-03-24 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN106026692A true CN106026692A (zh) | 2016-10-12 |
CN106026692B CN106026692B (zh) | 2018-11-16 |
Family
ID=56610797
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610172274.8A Active CN106026692B (zh) | 2015-03-24 | 2016-03-24 | 半导体模块、电力变换装置以及半导体模块的制造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9418975B1 (zh) |
JP (1) | JP6362560B2 (zh) |
CN (1) | CN106026692B (zh) |
DE (1) | DE102016204884A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020078082A1 (zh) * | 2018-10-14 | 2020-04-23 | 深圳市奕通功率电子有限公司 | 一种分边连接功率电极组合及功率模块 |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
USD814431S1 (en) * | 2015-05-15 | 2018-04-03 | Mitsubishi Electric Corporation | Power semiconductor device |
JP6326038B2 (ja) * | 2015-12-24 | 2018-05-16 | 太陽誘電株式会社 | 電気回路装置 |
USD864132S1 (en) | 2017-01-05 | 2019-10-22 | Rohm Co., Ltd. | Power semiconductor module |
JP1585831S (zh) | 2017-01-05 | 2017-09-11 | ||
JP1603980S (zh) * | 2017-09-07 | 2018-05-14 | ||
JP1603793S (zh) * | 2017-09-29 | 2018-05-14 | ||
USD864884S1 (en) * | 2017-10-23 | 2019-10-29 | Mitsubishi Electric Corporation | Semiconductor device |
JP1632173S (zh) * | 2018-06-01 | 2019-05-27 | ||
USD888673S1 (en) | 2018-06-26 | 2020-06-30 | Rohm Co., Ltd. | Semiconductor module |
JP1641098S (zh) | 2018-06-26 | 2019-09-09 | ||
JP1643025S (zh) * | 2019-03-15 | 2019-10-07 | ||
JP1644633S (zh) * | 2019-03-26 | 2019-11-05 | ||
USD903611S1 (en) * | 2019-03-29 | 2020-12-01 | Mitsubishi Electric Corporation | Semiconductor device |
JP1656709S (zh) * | 2019-05-31 | 2020-04-06 | ||
JP1659676S (zh) | 2019-08-29 | 2020-05-18 | ||
JP1659674S (zh) | 2019-08-29 | 2020-05-18 | ||
JP1659678S (zh) | 2019-08-29 | 2020-05-18 | ||
JP1659677S (zh) | 2019-08-29 | 2020-05-18 | ||
JP1659675S (zh) | 2019-08-29 | 2020-05-18 | ||
JP1659716S (zh) | 2019-08-29 | 2020-05-18 | ||
JP1659673S (zh) | 2019-08-29 | 2020-05-18 | ||
JP1659672S (zh) * | 2019-08-29 | 2020-05-18 | ||
USD916039S1 (en) * | 2020-03-20 | 2021-04-13 | Sansha Electric Manufacturing Co., Ltd. | Semiconductor device |
JP2022103562A (ja) * | 2020-12-28 | 2022-07-08 | 富士電機株式会社 | 半導体装置 |
US20230116532A1 (en) * | 2021-10-13 | 2023-04-13 | Eaton Intelligent Power Limited | Connector packages for fastenerless circuit coupling |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5512782A (en) * | 1993-10-13 | 1996-04-30 | Fuji Electric Co., Ltd. | Semiconductor device for DC/AC converter |
CN101110410A (zh) * | 2006-07-18 | 2008-01-23 | 三菱电机株式会社 | 功率半导体装置 |
CN101752321A (zh) * | 2008-12-17 | 2010-06-23 | 三菱电机株式会社 | 半导体装置 |
CN102067309A (zh) * | 2008-07-10 | 2011-05-18 | 三菱电机株式会社 | 电力用半导体模块 |
CN102446864A (zh) * | 2010-10-01 | 2012-05-09 | 三菱电机株式会社 | 功率模块及其制造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19522173C1 (de) * | 1995-06-19 | 1996-10-17 | Eupec Gmbh & Co Kg | Leistungs-Halbleitermodul |
JPH09219970A (ja) * | 1996-02-13 | 1997-08-19 | Fuji Electric Co Ltd | 半導体電力変換装置 |
JPH10116961A (ja) * | 1996-10-08 | 1998-05-06 | Nippon Inter Electronics Corp | 複合半導体装置及びそれに使用する絶縁ケース |
JP3747699B2 (ja) * | 1999-08-06 | 2006-02-22 | 富士電機デバイステクノロジー株式会社 | 半導体装置 |
JP4875977B2 (ja) * | 2006-12-27 | 2012-02-15 | 日本インター株式会社 | パワーモジュール |
JP5673449B2 (ja) | 2011-09-01 | 2015-02-18 | 三菱電機株式会社 | 半導体装置 |
JP2013125848A (ja) * | 2011-12-14 | 2013-06-24 | Rohm Co Ltd | パワーモジュール半導体装置およびその製造方法 |
JP6413553B2 (ja) * | 2014-09-26 | 2018-10-31 | 富士電機株式会社 | パワー半導体モジュール装置 |
-
2015
- 2015-03-24 JP JP2015060348A patent/JP6362560B2/ja active Active
- 2015-12-07 US US14/960,606 patent/US9418975B1/en active Active
-
2016
- 2016-03-23 DE DE102016204884.8A patent/DE102016204884A1/de active Pending
- 2016-03-24 CN CN201610172274.8A patent/CN106026692B/zh active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5512782A (en) * | 1993-10-13 | 1996-04-30 | Fuji Electric Co., Ltd. | Semiconductor device for DC/AC converter |
CN101110410A (zh) * | 2006-07-18 | 2008-01-23 | 三菱电机株式会社 | 功率半导体装置 |
CN102067309A (zh) * | 2008-07-10 | 2011-05-18 | 三菱电机株式会社 | 电力用半导体模块 |
CN101752321A (zh) * | 2008-12-17 | 2010-06-23 | 三菱电机株式会社 | 半导体装置 |
CN102446864A (zh) * | 2010-10-01 | 2012-05-09 | 三菱电机株式会社 | 功率模块及其制造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020078082A1 (zh) * | 2018-10-14 | 2020-04-23 | 深圳市奕通功率电子有限公司 | 一种分边连接功率电极组合及功率模块 |
Also Published As
Publication number | Publication date |
---|---|
CN106026692B (zh) | 2018-11-16 |
JP2016181576A (ja) | 2016-10-13 |
JP6362560B2 (ja) | 2018-07-25 |
DE102016204884A1 (de) | 2016-10-13 |
US9418975B1 (en) | 2016-08-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN106026692A (zh) | 半导体模块、电力变换装置以及半导体模块的制造方法 | |
JP6412612B2 (ja) | ハーフブリッジを設けるパワーモジュール、ならびにパワーモジュールおよびキャパシタの配置 | |
US10153708B2 (en) | Three-level power converter | |
CN105612690B (zh) | 半导体装置 | |
CN102683332B (zh) | 功率模块 | |
EP2884650A1 (en) | Power module comprising two elements, and three-level power conversion device using same | |
JP7393387B2 (ja) | 積層された端子を有する半導体デバイス | |
JP3941728B2 (ja) | 電力用半導体装置 | |
CN105742278A (zh) | 半导体装置 | |
CN103946978A (zh) | 半导体装置以及电子设备 | |
CN112543994B (zh) | 半导体装置 | |
CN106030796A (zh) | 功率用半导体模块 | |
US20230056722A1 (en) | Power module with improved electrical and thermal characteristics | |
CN110137160A (zh) | 半导体器件 | |
JP6647189B2 (ja) | 半導体モジュール、半導体装置および電力装置 | |
WO2023065602A1 (zh) | 功率模块及电机控制器 | |
US20150326221A1 (en) | Switching element unit | |
CN105514069B (zh) | 带功率半导体模块、直流电压汇流排和电容器器件的装置 | |
CN115440713A (zh) | 一种功率模块 | |
JP2016110993A (ja) | トランジスタリード線の溶接およびはんだ付け | |
CN105097738B (zh) | 半导体装置 | |
JP6425357B2 (ja) | 四端子スナバコンデンサ及びコンデンサモジュール | |
CN104518681B (zh) | 电力变换装置 | |
US10304770B2 (en) | Semiconductor device with stacked terminals | |
WO2021229859A1 (ja) | 半導体装置、バスバー及び電力変換装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |