CN106021041A - Finite state machine based multi-cycle non-flow line CPU debugging method - Google Patents
Finite state machine based multi-cycle non-flow line CPU debugging method Download PDFInfo
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- CN106021041A CN106021041A CN201610291250.4A CN201610291250A CN106021041A CN 106021041 A CN106021041 A CN 106021041A CN 201610291250 A CN201610291250 A CN 201610291250A CN 106021041 A CN106021041 A CN 106021041A
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- cpu
- depositor
- state machine
- finite state
- debugging
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
Abstract
The invention discloses a finite state machine based multi-cycle non-flow line CPU debugging method. The method can suspend a CPU in the condition that operation sites of a CPU register bank, a program counter, a state register and other CPUs are not changed; in this state, the state of the CPU can be read, and then a debugging purpose can be achieved; and in addition, the method induces few additional circuits, and cannot affect the operation state and efficiency of the CPU in a normal working mode.
Description
Technical field
The present invention relates to field of computer technology, particularly relate to a kind of multicycle nonpipeline CPU based on finite state machine
Adjustment method.
Background technology
In processor design process, often expend substantial amounts of manpower and materials and the correctness of CPU is verified, one
Denier goes wrong, then the reliable means that need carry out orientation problem.
But, in prior art, may require that when the CPU being currently running is debugged and introduce complex circuit, with
Time, running status and efficiency also for CPU produce certain impact.
Summary of the invention
It is an object of the invention to provide a kind of multicycle nonpipeline CPU adjustment method based on finite state machine, it introduces
Additional circuit is less, and does not interferes with running status and the efficiency of CPU under CPU normal mode of operation.
It is an object of the invention to be achieved through the following technical solutions:
A kind of multicycle nonpipeline CPU adjustment method based on finite state machine, including:
CPU process the step of every instruction be followed successively by fetching, decode, perform, memory access and write-back, redirecting between step
Realized by finite state machine；
Realizing CPU debugging by introducing depositor A and depositor B, described depositor A is used for arranging operational mode, institute
State depositor B for instruction count；The step realizing CPU debugging is as follows:
After original state or present instruction have performed write back step, described finite state machine judges according to the value of depositor A
Current operational mode；
If multistep debugging mode, then enter debugging mode, and judge the value of depositor B；When depositor B is not zero,
The value of depositor B is subtracted 1, and is skipped this debugging mode by described finite state machine, CPU continue with next and refer to
Order, so circulation are until after the value of depositor B is kept to zero, being blocked in debugging mode by described finite state machine by CPU；
If single-step debug pattern, described finite state machine CPU is blocked in debugging mode, until depositor B has new
Instruction count writes, and is left debugging mode by described finite states machine control, the value of depositor B is reset meanwhile.
Further, if judging currently as normal mode of operation, then to be continued with next by CPU according to the value of depositor A
Instruction.
As seen from the above technical solution provided by the invention, CPU Parasites Fauna, programmed counting can not changed
In the case of device, status register and other CPU operation scenes, CPU is worked " time-out ", in this condition can be by
The state of CPU reads, to reach the purpose of debugging；Additionally, the additional circuit that the program introduces is less, and this function exists
Running status and the efficiency of CPU is not interfered with under normal mode of operation.
Accompanying drawing explanation
In order to be illustrated more clearly that the technical scheme of the embodiment of the present invention, required use in embodiment being described below
Accompanying drawing is briefly described, it should be apparent that, the accompanying drawing in describing below is only some embodiments of the present invention, for
From the point of view of those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to obtain according to these accompanying drawings
Other accompanying drawings.
Fig. 1 processes the schematic diagram of every instruction for the CPU that the embodiment of the present invention provides；
The signal of the multicycle nonpipeline CPU adjustment method based on finite state machine that Fig. 2 provides for the embodiment of the present invention
Figure；
The flow chart realizing CPU debugging that Fig. 3 provides for the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly and completely
Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments.Based on
Embodiments of the invention, it is every other that those of ordinary skill in the art are obtained under not making creative work premise
Embodiment, broadly falls into protection scope of the present invention.
As it is shown in figure 1, CPU process the step of every instruction be followed successively by fetching, decode, perform, memory access and write-back；Step
Between redirect and realized by finite state machine；
In the embodiment of the present invention, realize CPU debugging, meanwhile, in finite state by introducing depositor A and depositor B
Machine inserts a decision state, as shown in Figure 2.
In the embodiment of the present invention, described depositor A is used for arranging operational mode, and described depositor B is used for instruction count.
Realizing shown in the block diagram 3 of CPU debugging, it specifically includes that
After original state or present instruction have performed write back step, described finite state machine judges according to the value of depositor A
Current operational mode；
If multistep debugging mode, then enter debugging mode, and judge the value of depositor B；When depositor B is not zero,
The value of depositor B is subtracted 1, and is skipped this debugging mode by described finite state machine, CPU continue with next and refer to
Order, so circulation are until after the value of depositor B is kept to zero, being blocked in debugging mode by described finite state machine by CPU；
If single-step debug pattern, described finite state machine CPU is blocked in debugging mode, until depositor B has new
Instruction count writes, and is left debugging mode by described finite states machine control, the value of depositor B is reset meanwhile.
After CPU is blocked in debugging mode by finite state machine, then the state of CPU can be read, to reach the mesh of debugging
's.
If additionally, judge current for normal mode of operation according to the value of depositor A, then being continued with next finger by CPU
Order.
From said process, operational mode specifically includes that normal mode of operation, multistep debugging mode, single-step debug mould
Formula, numerical value corresponding to each operational mode can preset and be stored in depositor A.
Exemplary, desirable 0,1,2 three values of depositor A, 0 is normal mode of operation (this pattern is default conditions),
1 is single-step debug pattern, and 2 is multistep debugging mode.
Single-step debug pattern uses process as follows:
1) depositor A being set to 1, enters single-step debug pattern, CPU will block after having performed present instruction.
2) write data (being indifferent to write value) to depositor B, perform next instruction.
3) CPU state (PC, status register, register file and data RAM etc.) is read by debugging interface.
4) 2,3 liang of steps are repeated, until debugging terminates.
5) depositor A being set to 0, returns normal mode of operation, CPU works on.
Multistep debugging mode uses process as follows:
1) depositor A being set to 2, enters multistep debugging mode, now the value of depositor B should be 0, and CPU has performed to work as
Will block after front instruction.
2) data are write to depositor B.
3) CPU continues executing with instruction, often performs an instruction, subtracts 1 by depositor B data, until the value of depositor B becomes
It is will to block after 0.
4) CPU state (PC, status register, register file and data RAM etc.) is read by debugging interface
5) as multistep debugging need to be continued, then perform 2,3,4 steps, otherwise perform 6 steps.
6) value of depositor A being set to 0, returns normal mode of operation, CPU works on.
In the such scheme of the embodiment of the present invention, CPU Parasites Fauna, program counter, Status register can not changed
In the case of device and other CPU operation scenes, CPU is worked " time-out ", the state of CPU can be read in this condition
Go out, to reach the purpose of debugging；Additionally, the additional circuit that the program introduces is less, and this function is in normal mode of operation
Under do not interfere with running status and the efficiency of CPU.
The above, the only present invention preferably detailed description of the invention, but protection scope of the present invention is not limited thereto,
Any those familiar with the art in the technical scope of present disclosure, the change that can readily occur in or replace
Change, all should contain within protection scope of the present invention.Therefore, protection scope of the present invention should be with claims
Protection domain is as the criterion.
Claims (2)
1. a multicycle nonpipeline CPU adjustment method based on finite state machine, it is characterised in that including:
CPU process the step of every instruction be followed successively by fetching, decode, perform, memory access and write-back, redirecting between step
Realized by finite state machine；
Realizing CPU debugging by introducing depositor A and depositor B, described depositor A is used for arranging operational mode, institute
State depositor B for instruction count；The step realizing CPU debugging is as follows:
After original state or present instruction have performed write back step, described finite state machine judges according to the value of depositor A
Current operational mode；
If multistep debugging mode, then enter debugging mode, and judge the value of depositor B；When depositor B is not zero,
The value of depositor B is subtracted 1, and is skipped this debugging mode by described finite state machine, CPU continue with next and refer to
Order, so circulation are until after the value of depositor B is kept to zero, being blocked in debugging mode by described finite state machine by CPU；
If single-step debug pattern, described finite state machine CPU is blocked in debugging mode, until depositor B has new
Instruction count writes, and is left debugging mode by described finite states machine control, the value of depositor B is reset meanwhile.
A kind of multicycle nonpipeline CPU adjustment method based on finite state machine the most according to claim 1, its
Being characterised by, if judging according to the value of depositor A current for normal mode of operation, then being continued with next finger by CPU
Order.
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| CN106021041B CN106021041B (en) | 2020-01-03 |
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| CN101339581A (en) * | 2008-08-29 | 2009-01-07 | 北京中星微电子有限公司 | Embedded system on-line debugging emulation method based on communication interruption |
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2016
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| US4674089A (en) * | 1985-04-16 | 1987-06-16 | Intel Corporation | In-circuit emulator |
| CN1904851A (en) * | 2005-07-29 | 2007-01-31 | 中国科学院计算技术研究所 | Method and apparatus of single step execution debugging function |
| CN101154178A (en) * | 2006-09-29 | 2008-04-02 | 松下电器产业株式会社 | Microcomputer debugging system |
| CN101178685A (en) * | 2007-09-27 | 2008-05-14 | 上海大学 | Enhancement type microprocessor piece on-chip dynamic state tracking method with special function register breakpoints |
| CN101339581A (en) * | 2008-08-29 | 2009-01-07 | 北京中星微电子有限公司 | Embedded system on-line debugging emulation method based on communication interruption |
| CN101814054A (en) * | 2010-03-23 | 2010-08-25 | 苏州国芯科技有限公司 | Instruction tracing controller for debugging microcontroller |
| CN103299282A (en) * | 2010-12-02 | 2013-09-11 | 超威半导体公司 | Debug state machine and processor including the same |
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