CN106019732B - FFS mode array substrate and preparation method thereof - Google Patents
FFS mode array substrate and preparation method thereof Download PDFInfo
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- CN106019732B CN106019732B CN201610594132.0A CN201610594132A CN106019732B CN 106019732 B CN106019732 B CN 106019732B CN 201610594132 A CN201610594132 A CN 201610594132A CN 106019732 B CN106019732 B CN 106019732B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
Abstract
The invention discloses an FFS mode array substrate and a preparation method thereof. The array substrate is defined with a pixel display area; the preparation method comprises the steps of forming a metal layer surrounding a pixel display area on the periphery of the pixel display area of the array substrate; forming a common electrode layer on the array substrate; conducting the metal layer and the common electrode layer at the periphery of the pixel display area; and a plurality of positions for conducting the metal layer and the common electrode layer are arranged, or adjacent boundaries between the metal layer and the common electrode layer are in continuous contact to realize conduction. The invention also discloses an array substrate. According to the invention, the common electrode layer is provided with the common voltage through the metal layer at the periphery of the pixel display area, a common electrode wire does not need to be manufactured in the pixel display area, the common voltage is provided for the common electrode layer, the aperture opening ratio of the liquid crystal display panel is not influenced, and the display quality is improved.
Description
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to an FFS-mode array substrate and a preparation method thereof.
Background
A Fringe Field Switching (FFS) is a Fringe Field liquid crystal display mode, which is a currently common wide viewing angle liquid crystal display technology, and an FFS liquid crystal display panel has the advantages of fast response time, high light transmittance, wide viewing angle, and the like. In the FFS mode, a fringe field is formed between a common electrode and a pixel electrode in a pixel display region of the array substrate to control the liquid crystal so as to achieve the purpose of displaying a picture, the common electrode is an integrated common electrode layer, the potential of the pixel electrode is independently controlled through a data line, and the potential of the common electrode is independently controlled by an external circuit. In the prior art, a common electrode wire is electrically connected with a common electrode through being formed in a pixel display area, common voltage is provided for the common electrode through the common electrode wire in the pixel display area, and the common electrode wire is arranged in the pixel display area, so that the area of an effective light transmission area of the pixel display area of an array substrate is occupied, the aperture opening ratio of the array substrate is reduced, and the display quality of a liquid crystal display panel is influenced.
Disclosure of Invention
In view of this, the present invention provides an FFS mode array substrate and a method for manufacturing the same, which can provide a common voltage to a common electrode layer without affecting an aperture ratio of a liquid crystal display panel, thereby improving display quality.
In order to solve the technical problems, the invention provides a technical scheme that: providing a preparation method of an FFS mode array substrate, wherein a pixel display area is defined on the array substrate;
the preparation method comprises the following steps:
forming a metal layer surrounding the pixel display area on the periphery of the pixel display area of the array substrate;
forming a common electrode layer on the array substrate;
conducting the metal layer and the common electrode layer at the periphery of the pixel display area;
and a plurality of positions for conducting the metal layer and the common electrode layer are arranged, or adjacent boundaries between the metal layer and the common electrode layer are in continuous contact to realize conduction.
The metal layer is formed together with a display pixel area metal layer which is used for forming a scanning line and/or a data line in the pixel display area;
the method further comprises the following steps after the metal layer surrounding the pixel display area is formed on the periphery of the pixel display area of the array substrate:
forming a first isolation layer on the metal layer, and forming a through hole on the first isolation layer through a photomask;
forming a flat layer on the first isolation layer, and forming a through hole on the flat layer through a photomask;
the forming of the common electrode layer on the array substrate specifically includes:
forming the common electrode layer on the planarization layer.
Wherein the forming of the metal layer surrounding the pixel display area on the periphery of the pixel display area of the array substrate comprises:
forming a first metal layer surrounding a pixel display area at the periphery of the pixel display area of the array substrate, wherein the first metal layer is formed together with a scan line metal layer for forming a scan line in the pixel display area;
forming a second isolation layer on the first metal layer, and forming a through hole on the second isolation layer through a photomask;
forming a second metal layer on the second isolation layer, wherein the second metal layer is formed together with a data line metal layer for forming a data line in the pixel display area;
after forming a second metal layer on the second isolation layer, the method further comprises:
forming a first isolation layer on the second metal layer, and forming a through hole on the first isolation layer through a photomask;
forming a flat layer on the first isolation layer, and forming a through hole on the flat layer through a photomask;
the forming of the common electrode layer on the array substrate specifically includes:
forming the common electrode layer on the planarization layer.
Wherein, after the forming the common electrode layer on the planarization layer, the method comprises:
forming a third isolation layer on the common electrode layer, and forming a through hole on the third isolation layer through a photomask;
and forming a pixel electrode layer on the third isolation layer, wherein the pixel electrode layer is arranged at the periphery of the pixel display area.
Another embodiment of the present invention provides an FFS mode array substrate, wherein the array substrate defines a pixel display area, and at least a common electrode layer is disposed on the pixel display area;
a metal layer surrounding the pixel display area is arranged on the periphery of the pixel display area, and the metal layer is electrically connected with the common electrode layer and provides common voltage for the common electrode layer;
and a plurality of positions where the metal layer is electrically connected with the common electrode layer are arranged, or adjacent boundaries between the metal layer and the common electrode layer are in continuous contact to realize the electrical connection.
The metal layer is connected with a PCB, and the PCB is connected with a common voltage source.
The step of electrically connecting the metal layer with the common electrode layer specifically comprises:
a first isolation layer and a flat layer are arranged between the metal layer and the common electrode layer; and at the edge of the pixel display area, the metal layer is electrically connected with the common electrode layer through holes formed in the first isolation layer and the flat layer.
The metal layers comprise a first metal layer and a second metal layer which are arranged from bottom to top, a second isolation layer is arranged between the first metal layer and the second metal layer, and the first metal layer and the second metal layer are electrically connected through a through hole in the second isolation layer;
the metal layer electrically connected with the common electrode layer specifically comprises:
a first isolation layer and a flat layer are arranged between the second metal layer and the common electrode layer, and the second metal layer is electrically connected with the common electrode layer through holes formed in the first isolation layer and the flat layer;
the metal layer is connected with the PCB specifically as follows:
the first metal layer is connected with a PCB.
The common electrode layer is provided with a third isolation layer and a pixel electrode layer, and the common electrode layer is electrically connected with the pixel electrode layer through a through hole formed in the third isolation layer;
the pixel electrode layer is arranged on the periphery of the pixel display area and is formed simultaneously with the pixel electrode in the pixel display area.
Wherein the position of the through hole on the first isolation layer is consistent with the position of the through hole on the flat layer;
and the positions of the through holes on the second isolation layer are consistent with the positions of the through holes on the third isolation layer.
Has the advantages that: different from the prior art, the metal layer surrounding the pixel display area is formed on the periphery of the pixel display area of the array substrate; forming a common electrode layer on the array substrate; conducting the metal layer and the common electrode layer at the periphery of the pixel display area; and a plurality of positions for conducting the metal layer and the common electrode layer are arranged, or adjacent boundaries between the metal layer and the common electrode layer are in continuous contact to realize conduction. In this way, the metal layer on the periphery of the pixel display area is used for providing the common voltage for the common electrode layer, a common electrode wire does not need to be manufactured in the pixel display area, the common voltage can be provided for the common electrode layer, the aperture opening ratio of the liquid crystal display panel is not influenced, and the display quality is improved.
Drawings
FIG. 1 is a schematic flow chart illustrating a method for fabricating an array substrate according to an embodiment of the present invention;
FIG. 2 is a schematic plan view of the array substrate prepared according to FIG. 1;
FIG. 3 is a flowchart illustrating a specific step S1 in FIG. 1;
FIG. 4 is a schematic structural view of a metal layer prepared according to FIG. 3;
FIG. 5 is another detailed flowchart of step S1 in FIG. 1;
FIG. 6 is a schematic structural view of a metal layer prepared according to FIG. 5;
FIG. 7 is another detailed flowchart of step S1 in FIG. 1;
FIG. 8 is a detailed flowchart of step S3 in FIG. 1;
FIGS. 9a to 9c are schematic structural diagrams illustrating an electrical connection between a metal layer and a common electrode layer in an array substrate according to the present invention;
FIG. 10 is a schematic flow chart illustrating a method for fabricating an array substrate according to another embodiment of the present invention;
FIGS. 11a to 11c are schematic structural views of another electrical connection between the metal layer and the common electrode layer in the array substrate according to the present invention;
FIGS. 12 a-12 c are schematic plan views of another electrical connection between the metal layer and the common electrode layer shown in FIGS. 11 a-11 c.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
In order to make those skilled in the art better understand the technical solution of the present invention, the FFS mode array substrate and the method for fabricating the FFS mode array substrate provided by the present invention will be described in further detail with reference to the accompanying drawings and specific examples. In the drawings, the thickness of layers and regions are exaggerated for clarity of the devices, and like reference numerals are used to designate like elements throughout the specification and drawings.
The array substrate of the FFS mode of the embodiment of the invention is defined with a pixel display area, and the pixel display area refers to an area which is provided with a pixel electrode and used for displaying of a liquid crystal display panel.
Fig. 1 is a schematic flow chart of an embodiment of a method for manufacturing an array substrate according to the present invention, the method specifically includes the following steps:
and S1, forming a metal layer surrounding the pixel display area on the periphery of the pixel display area of the array substrate.
The metal layer at the periphery of the pixel display area is formed together with the metal layer for preparing the scan lines and/or the data lines in the pixel display area. A metal layer for preparing a scanning line and/or a data line is formed on the array substrate through sputtering, deposition or coating, the scanning line and the data line are formed in the pixel display area through coating, exposing, developing, wet etching, dry etching, stripping and the like, and meanwhile, the metal layer surrounding the pixel display area is formed on the periphery of the pixel display area.
And S2, forming a common electrode layer on the array substrate.
The common electrode layer in the liquid crystal display panel based on the FFS mode is disposed on the array substrate, and on the array substrate, the common electrode layer at least covers a pixel display area of the array substrate, and optionally, an area covered by the common electrode layer is slightly larger than the pixel display area.
And S3, conducting the metal layer and the common electrode layer at the periphery of the pixel display area.
The metal layer and the common electrode layer are conducted on the periphery of the pixel display area, and the metal layer is connected with the common voltage source, so that the metal layer on the periphery of the pixel display area is used for providing common voltage for the common electrode layer, a common electrode wire does not need to be manufactured in the pixel display area, and the purpose of not influencing the aperture opening ratio of the liquid crystal display panel while providing the common voltage for the common electrode layer can be achieved.
And at the periphery of the pixel display area, the metal layer is conducted with the common electrode layer so that the metal layer is electrically connected with the common electrode layer. The metal layer and the common electrode layer are electrically connected in a plurality of positions, or adjacent boundaries between the metal layer and the common electrode layer are in continuous contact to realize electrical connection. Optionally, the position where the metal layer and the common electrode layer are conducted at the periphery of the pixel display area is at the edge of the pixel display area.
Fig. 2 is a schematic plan view of an array substrate obtained according to an embodiment of the method for manufacturing an array substrate shown in fig. 1, and since the structure of the array substrate is stacked, in order to more clearly show a transmission path of a common voltage of the array substrate obtained according to an embodiment of the method for manufacturing an array substrate shown in fig. 2, only a related hierarchical structure is labeled.
Referring to fig. 2, a central shadow region is a pixel display region 1, at least a common electrode layer 2 is disposed on the pixel display region 1, a metal layer 3 surrounding the pixel display region is disposed in the shadow region at the periphery of the pixel display region, a PCB 4 is disposed at the periphery of an array substrate, and optionally, the PCB 4 is disposed at a data signal input side of the array substrate; the PCB 4 is connected to the metal layer 2 at the periphery of the pixel display region On the array substrate through a plurality of feeding points 5, further, the PCB 4 is connected to the metal layer 2 through a Chip On Film (COF), and the PCB 4 transmits a common voltage signal to the array substrate through the COF. In fig. 2, the area covered by the common electrode layer is slightly larger than the pixel display area 1, the unfilled area is the overlapping area of the common electrode layer 2 and the metal layer 3, in the overlapping area, the metal layer 3 and the common electrode layer 2 are conducted, and there are a plurality of conducting positions 6; and at the conducting position of the metal layer and the common electrode layer, the metal layer is electrically connected with the common electrode layer, and a plurality of positions are arranged at which the metal layer is electrically connected with the common electrode layer. In addition, the metal layer and the common electrode layer can be in continuous contact through adjacent boundaries to achieve conduction, and the continuous conduction part of the metal layer and the common electrode layer is electrically connected.
The array substrate obtained by the preparation method of the array substrate utilizes the metal layer at the periphery of the pixel display area to provide the common voltage for the common electrode layer, establishes a conducting path of the common voltage at the periphery of the pixel display area, and does not need to manufacture a common electrode wire in the pixel display area, thereby achieving the purpose of providing the common voltage for the common electrode layer and simultaneously not influencing the aperture opening ratio of the liquid crystal display panel.
Optionally, as shown in fig. 3, step S1 specifically includes the following steps:
s101, forming a first metal layer surrounding a pixel display area on the periphery of the pixel display area of the array substrate.
The first metal layer is formed together with a metal layer for forming a scanning line in the pixel display area, namely, the metal layer for manufacturing the scanning line is formed on the array substrate by sputtering, deposition, coating or the like, the metal layer for manufacturing the scanning line is subjected to patterning processing through a photomask, and the first metal layer surrounding the pixel display area is formed on the periphery of the pixel display area while the scanning line is formed in the pixel display area.
S102, forming a first isolation layer on the first metal layer, and forming a through hole on the first isolation layer through a photomask.
The first isolation layer is formed together with a metal isolation layer used for forming a gap between a scanning line and a data line in the pixel display area, namely the first isolation layer and the metal isolation layer between the scanning line and the data line in the pixel display area are the same layer. The first isolation layer is a double-layer structure of silicon nitride and silicon oxide.
And carrying out patterning processing on the first isolation layer through a photomask, and forming a through hole on the first isolation layer at the periphery of the pixel display area, wherein the position of the through hole corresponds to the position 6 of the conduction of the metal layer 3 and the common electrode layer 2 in the graph 2.
And S103, forming a second metal layer on the second isolation layer.
The second metal layer is formed together with a metal layer for forming data lines in the pixel display area, that is, the metal layer for manufacturing the data lines is formed on the array substrate by sputtering, deposition, coating or the like, the metal layer for manufacturing the data lines is subjected to patterning processing through a photomask, the data lines are formed in the pixel display area, and the second metal layer surrounding the pixel display area is formed at the periphery of the pixel display area. The second metal layer is conducted with the first metal layer through the through hole formed in the first isolation layer, and when a voltage signal is input to the first metal layer, the voltage signal can be introduced into the second metal layer through the first metal layer.
The structure of the metal layer obtained at this time is shown in fig. 4, the metal layer includes a first metal layer 301 and a second metal layer 302 arranged from bottom to top, a first isolation layer 7 is arranged between the first metal layer 301 and the second metal layer 302, the first metal layer 301 and the second metal layer 302 are electrically connected through a through hole 701 on the first isolation layer 7, and the first metal layer 301 surrounds the pixel display area, that is, the first metal layer 301 is arranged on the periphery of the pixel display area.
Optionally, as shown in fig. 5, step S1 specifically includes the following steps:
and S104, forming a first metal layer surrounding the pixel display area on the periphery of the pixel display area of the array substrate.
Step S104 is the same as step S101, and is not described here again.
And S105, forming a first isolation layer on the first metal layer.
The first isolation layer is formed together with a metal isolation layer used for forming a gap between a scanning line and a data line in the pixel display area, namely the first isolation layer and the metal isolation layer between the scanning line and the data line in the pixel display area are the same layer. The first isolation layer is a double-layer structure of silicon nitride and silicon oxide.
And S106, forming a second metal layer on the second isolation layer.
Step S105 is the same as step S103, and is not described here again.
The structure of the metal layer obtained at this time is shown in fig. 6, and is different from the structure of the metal layer shown in fig. 4 in that no through hole is formed in the first isolation layer 7, the metal layer includes a first metal layer 301 and a second metal layer 302 which are arranged from bottom to top, the first isolation layer 7 is arranged between the first metal layer 301 and the second metal layer 302, the first metal layer 301 and the second metal layer 302 are not conductive, and the second metal layer 302 is directly connected to an external voltage signal source at this time.
Optionally, as shown in fig. 7, step S1 specifically includes the following steps:
and S107, forming a second metal layer surrounding the pixel display area on the periphery of the pixel display area of the array substrate.
In the embodiment of the manufacturing method shown in fig. 7, the metal layer of the scan line and the metal isolation layer at the periphery of the pixel display area are both etched, and only the metal layer for manufacturing the data line is etched. The second metal layer is formed together with a metal layer for forming data lines in the pixel display area, that is, the metal layer for manufacturing the data lines is formed on the array substrate by sputtering, deposition, coating or the like, the metal layer for manufacturing the data lines is subjected to patterning processing through a photomask, the data lines are formed in the pixel display area, and the second metal layer surrounding the pixel display area is formed at the periphery of the pixel display area. At this time, only the second metal layer is arranged at the periphery of the pixel display area, and the second metal layer is connected with an external voltage signal source.
The structure of the metal layer obtained by the preparation method of the metal layer shown in fig. 3, 5 and 7 is disposed at the periphery of the pixel display area of the array substrate, and optionally, the structure of the metal layer obtained by the preparation method of the metal layer shown in fig. 3, 5 and 7 is disposed at the periphery of the pixel display area and near the edge of the pixel display area.
Based on the above preparation method of the metal layer, as shown in fig. 8, step S3 specifically includes the following steps:
s301, forming a second isolation layer on the second metal layer, and forming a through hole on the second isolation layer through a photomask.
S302, forming a flat layer on the second isolation layer, and forming a through hole on the flat layer through a photomask.
The steps of forming the through holes on the second isolation layer and the planarization layer are similar to the steps of forming the through holes on the first isolation layer, and there are also a plurality of through holes formed on the second isolation layer and the planarization layer, and the positions of the plurality of through holes correspond to the positions 6 where the metal layer 3 and the common electrode layer 2 are conducted in fig. 2.
And S303, forming the common electrode layer on the flat layer, wherein the common electrode layer is electrically connected with the second metal layer through the flat layer and the through holes on the second isolation layer.
The method for conducting the metal layer 3 and the common electrode layer 2 shown in fig. 8 can be applied to the metal layer preparation methods shown in fig. 3, fig. 5 and fig. 7, and the obtained structures for electrically connecting the metal layer and the common electrode layer at the periphery of the pixel display area of the array substrate are respectively shown in fig. 9a, fig. 9b and fig. 9c, wherein the positions of the structures for electrically connecting the metal layer and the common electrode layer are a plurality, or adjacent boundaries between the metal layer and the common electrode layer are continuously contacted to realize the electrical connection.
In fig. 9a, the first metal layer 301 is conducted to the second metal layer 302 through the via hole 701 on the first isolation layer 7, the second metal layer 302 is conducted to the common electrode layer 2 through the via hole 801 on the second isolation layer 8 and the via hole 901 on the planarization layer 9, the first metal layer 301 is connected to an external common voltage source, and then a common voltage signal is introduced into the second metal layer 302 through the first metal layer 301, and then introduced into the common electrode layer 2 from the second metal layer 302. In fig. 9b, the first metal layer 301 and the second metal layer 302 are not conducted, the second metal layer 302 is connected to an external common voltage source, and a common voltage signal is introduced into the common electrode layer 2 through the second metal layer 302. In fig. 9c, only the second metal layer 302 is disposed at the periphery of the pixel display region, the second metal layer 302 is connected to an external common voltage source, and a common voltage signal is introduced into the common electrode layer through the second metal layer 302.
Optionally, when the first metal layer or the second metal layer is connected to an external common voltage source, the PCB is connected between the first metal layer or the second metal layer and the external common voltage source, that is, the first metal layer and the second metal layer are connected to the PCB, preferably, data signal input sides of the first metal layer and the second metal layer are connected to the PCB, further, the PCB is connected to the first metal layer and the second metal layer through a Chip On Film (COF), and the PCB 4 transmits a common voltage signal to the array substrate through a COF; the PCB board is connected to an external common voltage source in a manner, referring to fig. 2, the metal layer 3 in fig. 2 includes a first metal layer 301 and/or a second metal layer 302.
Fig. 10 is a flowchart illustrating a method for manufacturing an array substrate according to another embodiment of the present invention, wherein the method for manufacturing an array substrate includes the following steps:
and S4, forming a metal layer surrounding the pixel display area on the periphery of the pixel display area of the array substrate.
And S5, forming a common electrode layer on the array substrate.
And S6, conducting the metal layer and the common electrode layer at the periphery of the pixel display area.
Steps S4, S5, and S6 are the same as steps S1, S2, and S3 in fig. 1, respectively, and are not described herein again.
And S7, forming a third isolation layer on the common electrode layer, and forming a through hole on the third isolation layer through a photomask.
And S8, forming a pixel electrode layer on the third isolation layer, wherein the pixel electrode layer is arranged at the periphery of the pixel display area.
The structure of the array substrate obtained according to the embodiment of the preparation method shown in fig. 10, in which the metal layer is electrically connected with the common electrode layer, is shown in fig. 11a, 11b and 11 c. In fig. 11a, 11b and 11c, the third isolation layer 10 is disposed above the common electrode layer 2, the pixel electrode layer 11 is disposed above the third isolation layer 10, and the pixel electrode layer 11 is electrically connected to the common electrode layer 2 through a through hole on the third isolation layer 10.
The structure of the array substrate shown in fig. 11a, 11b and 11c is the structure where the metal layer and the common electrode layer are electrically connected at the periphery of the pixel display region; alternatively, the structure of the array substrate shown in fig. 11a, 11b and 11c is disposed at the periphery of the pixel display region and near the edge of the pixel display region.
At this time, the pixel electrode layer 11 at the periphery of the pixel display region overlaps with the overlapping region of the common electrode layer 2 and the metal layer 3 in fig. 2; at the periphery of the pixel display area, the position where the common electrode layer 2 is conducted with the pixel electrode layer 11 also corresponds to the position 6 where the metal layer is conducted with the common electrode layer.
Fig. 11a shows that the position of the via hole 701 on the first isolation layer 7 is consistent with the position of the via hole 1001 on the third isolation layer 10, the position of the via hole 801 on the second isolation layer 8 is consistent with the position of the via hole 901 on the planarization layer 9, and fig. 12a is a schematic plan view of the array substrate shown in fig. 11a, in which the metal layer is electrically connected to the common electrode layer; in fig. 11b, there is no through hole on the first isolation layer 7, the position of the through hole 801 on the second isolation layer 8 is the same as the position of the through hole 901 on the planarization layer 9, and fig. 12b is a schematic plan view of the electrical connection between the metal layer and the common electrode layer in the array substrate shown in fig. 11 b; fig. 11c is a schematic plan view illustrating the array substrate shown in fig. 11c, in which the metal layer is the second metal layer 302, the position of the through hole 801 on the second isolation layer 8 is the same as the position of the through hole 901 on the planarization layer 9, and fig. 12c is a schematic plan view illustrating the electrical connection between the metal layer and the common electrode layer in the array substrate shown in fig. 11 c.
In the array substrate obtained by the preparation method, after the common voltage is introduced into the common electrode layer through the metal layer, the common voltage is introduced into the pixel electrode layer at the periphery of the pixel display area through the through hole on the third isolation layer; because the pixel electrode layer and the common electrode layer are provided with a plurality of electrically connected positions at the periphery of the pixel display area, the electrically connected positions are distributed outside the pixel display area, and common voltage signals can be transmitted before the pixel electrode layer and the common electrode layer through the electrically connected positions, so that common voltage on the common electrode layer is more uniform and stable.
The preparation method of the array substrate comprises the steps of forming a metal layer surrounding a pixel display area on the periphery of the pixel display area of the array substrate; forming a common electrode layer on the array substrate; conducting the metal layer and the common electrode layer at the periphery of the pixel display area; and a plurality of positions for conducting the metal layer and the common electrode layer are arranged, or adjacent boundaries between the metal layer and the common electrode layer are in continuous contact to realize conduction. The invention provides the common voltage for the common electrode layer by utilizing the metal layer at the periphery of the pixel display area, does not need to manufacture the common electrode wire in the pixel display area, can provide the common voltage for the common electrode layer, does not influence the aperture opening ratio of the liquid crystal display panel and improves the display quality.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. The preparation method of the array substrate of FFS mode is characterized in that a pixel display area is defined on the array substrate;
the preparation method comprises the following steps:
forming a metal layer surrounding the pixel display area on the periphery of the pixel display area of the array substrate;
forming a common electrode layer on the array substrate;
conducting the metal layer and the common electrode layer at the periphery of the pixel display area;
the metal layer is conducted with the common electrode layer at the edge of the pixel display area;
and a plurality of positions for conducting the metal layer and the common electrode layer are arranged, or adjacent boundaries between the metal layer and the common electrode layer are in continuous contact to realize conduction.
2. The manufacturing method according to claim 1, wherein the metal layer is formed together with a display pixel region metal layer for forming a scan line and/or a data line in the pixel display region;
the method further comprises the following steps after the metal layer surrounding the pixel display area is formed on the periphery of the pixel display area of the array substrate:
forming a first isolation layer on the metal layer surrounding the pixel display area, and forming a through hole on the first isolation layer through a photomask;
forming a flat layer on the first isolation layer, and forming a through hole on the flat layer through a photomask;
the forming of the common electrode layer on the array substrate specifically includes:
forming the common electrode layer on the planarization layer.
3. The method for manufacturing the array substrate according to claim 1, wherein the forming of the metal layer surrounding the pixel display area on the periphery of the pixel display area of the array substrate comprises:
forming a first metal layer surrounding a pixel display area at the periphery of the pixel display area of the array substrate, wherein the first metal layer is formed together with a scan line metal layer for forming a scan line in the pixel display area;
forming a second isolation layer on the first metal layer, and forming a through hole on the second isolation layer through a photomask;
forming a second metal layer on the second isolation layer, wherein the second metal layer is formed together with a data line metal layer for forming a data line in the pixel display area;
after forming a second metal layer on the second isolation layer, the method further comprises:
forming a first isolation layer on the second metal layer, and forming a through hole on the first isolation layer through a photomask;
forming a flat layer on the first isolation layer, and forming a through hole on the flat layer through a photomask;
the forming of the common electrode layer on the array substrate specifically includes:
forming the common electrode layer on the planarization layer.
4. The production method according to claim 2 or 3, characterized by, after the forming of the common electrode layer on the planarization layer, comprising:
forming a third isolation layer on the common electrode layer, and forming a through hole on the third isolation layer through a photomask;
and forming a pixel electrode layer on the third isolation layer, wherein the pixel electrode layer is arranged at the periphery of the pixel display area.
5. The array substrate is characterized in that a pixel display area is defined on the array substrate, and a common electrode layer is arranged on at least the pixel display area;
a metal layer surrounding the pixel display area is arranged on the periphery of the pixel display area, and the metal layer is electrically connected with the common electrode layer and provides common voltage for the common electrode layer;
the metal layer is conducted with the common electrode layer at the edge of the pixel display area;
and a plurality of positions where the metal layer is electrically connected with the common electrode layer are arranged, or adjacent boundaries between the metal layer and the common electrode layer are in continuous contact to realize the electrical connection.
6. The array substrate of claim 5, wherein the metal layer is connected to a PCB board, and the PCB board is connected to a common voltage source.
7. The array substrate of claim 5, wherein the metal layer electrically connecting the common electrode layer specifically comprises:
a first isolation layer and a flat layer are arranged between the metal layer and the common electrode layer; and at the edge of the pixel display area, the metal layer is electrically connected with the common electrode layer through holes formed in the first isolation layer and the flat layer.
8. The array substrate of claim 6, wherein the metal layers comprise a first metal layer and a second metal layer arranged from bottom to top, a second isolation layer is arranged between the first metal layer and the second metal layer, and the first metal layer and the second metal layer are electrically connected through a through hole on the second isolation layer;
the metal layer electrically connected with the common electrode layer specifically comprises:
a first isolation layer and a flat layer are arranged between the second metal layer and the common electrode layer, and the second metal layer is electrically connected with the common electrode layer through holes formed in the first isolation layer and the flat layer;
the metal layer is connected with the PCB specifically as follows:
the first metal layer is connected with a PCB.
9. The array substrate of claim 8, wherein a third isolation layer and a pixel electrode layer are disposed on the common electrode layer, and the common electrode layer is electrically connected to the pixel electrode layer through a through hole formed in the third isolation layer;
the pixel electrode layer is arranged on the periphery of the pixel display area and is formed simultaneously with the pixel electrode in the pixel display area.
10. The array substrate of claim 9, wherein the position of the via hole on the first isolation layer is consistent with the position of the via hole on the planarization layer;
and the positions of the through holes on the second isolation layer are consistent with the positions of the through holes on the third isolation layer.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101093843A (en) * | 2006-06-23 | 2007-12-26 | 北京京东方光电科技有限公司 | Electrode structure in flat panel display, and fabricating method |
| CN101140912A (en) * | 2007-10-16 | 2008-03-12 | 友达光电股份有限公司 | Array substrates of LCD and method of producing the same |
| CN101614916A (en) * | 2008-06-25 | 2009-12-30 | 北京京东方光电科技有限公司 | The method of TFT-LCD dot structure and LCD reparation broken string |
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| JP2003172946A (en) * | 2001-09-28 | 2003-06-20 | Fujitsu Display Technologies Corp | Substrate for liquid crystal display device and liquid crystal display device using the substrate |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101093843A (en) * | 2006-06-23 | 2007-12-26 | 北京京东方光电科技有限公司 | Electrode structure in flat panel display, and fabricating method |
| CN101140912A (en) * | 2007-10-16 | 2008-03-12 | 友达光电股份有限公司 | Array substrates of LCD and method of producing the same |
| CN101614916A (en) * | 2008-06-25 | 2009-12-30 | 北京京东方光电科技有限公司 | The method of TFT-LCD dot structure and LCD reparation broken string |
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