CN105990294A - Application method of spacing layer in stacked crystal grain packaging - Google Patents

Application method of spacing layer in stacked crystal grain packaging Download PDF

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Publication number
CN105990294A
CN105990294A CN201510074772.4A CN201510074772A CN105990294A CN 105990294 A CN105990294 A CN 105990294A CN 201510074772 A CN201510074772 A CN 201510074772A CN 105990294 A CN105990294 A CN 105990294A
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film
step
layer
daf
plurality
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CN201510074772.4A
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Chinese (zh)
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凡会建
李文化
彭志文
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特科芯有限公司
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Priority to CN201510074772.4A priority Critical patent/CN105990294A/en
Publication of CN105990294A publication Critical patent/CN105990294A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

Abstract

The invention discloses an application method of spacing layer in stacked crystal grain packaging. The application method comprises a plurality of stacked crystal grains which are placed on a substrate, the bottom surface of each of the plurality of stacked crystal grains is attached with a DAF adhesive film, and adjacent crystal grains of the plurality of stacked crystal grains are attached with an FOW adhesive film therebetween, a spacing layer is applied to replace the FOW adhesive film between adjacent crystal grains of the plurality of stacked crystal grains, and the spacing layer is applied to the crystal gain on which the DAF adhesive film is attached. The process of replacing the FOW adhesive film with the spacing layer comprises three procedures which are silicon wafer thinning, DAF adhesive film attaching after silicon wafer thinning and scribing in sequence. Through the technical scheme disclosed by the invention, the spacing layer is additionally arranged, and the packaging cost and the packaging process difficulty are reduced. In addition, the DAF film adopted by the spacing layer is harder than the FOW film, thereby enabling scribing to be carried out conveniently.

Description

间隔层在堆叠晶粒封装的应用方法 The method of application of spacer layer stacked die package

技术领域 FIELD

[0001] 本发明属于集成电路封装技术领域,公开了间隔层在堆叠晶粒封装中的应用方法。 [0001] The present invention belongs to the field of integrated circuit packaging technology, the application discloses a method spacer layer stacked die package. 背景技术 Background technique

[0002] 在集成电路封装中,堆叠封装是1C封装非常常用的一种封装形式,可以使同种晶粒(die)的堆叠,也可以是不同晶粒(die)的堆叠,在堆叠设计时要避免下层金线与上层晶粒(die)接触通常采用F0W胶膜(film over wire)这种比较贵的胶膜,F0W胶膜在晶圆减薄后,贴在晶圆背面,划片时,将晶圆和F0W胶膜一起切开,其特性加热固化前非常软,固晶时,直接将贴有F0W胶膜的晶粒(die)压在下层已焊线的晶圆(die)上,下层的金线就陷入F0W胶膜里面。 [0002] In the integrated circuit package, the package 1C stacked packages is very commonly used package can be made with a stacked seed grains (Die), and may be a stack of different grain (Die), and the stack design to prevent the upper die and the lower layer of gold (die) contacting usually F0W film (film over wire) such expensive film, F0W film after wafer thinning, affixed to the back of the wafer, dicing on the cut film with the wafer and F0W, which prior to curing characteristics of the heating is very soft, solid crystal, the film directly affixed F0W grains (die) has been pressed against the lower wire bonding wafers (die) , lower gold sank F0W film inside. 而且价格不菲的F0W胶膜对工艺条件要求也很高,由于其非常软,在划片时容易产生胶丝,容易粘刀将刀上的钻石颗粒包裹失去切削能力,这样的刀切出来的晶圆会有崩缺造成电性失效,另外,切割时产生的胶丝比较多有些会粘到晶圆正面的bond pad(焊线盘)上造成焊线问题,其对die bond(固晶)制程条件要求也比较严格,die bond(固晶) 的压力和压力的均匀性要足以使下层晶圆(die)上的金线完全陷进上层晶粒(die)下面贴覆的F0W胶膜里面,同时还要保证上层晶圆(die)的水平度。 F0W film and expensive process conditions requirements are high, due to its very soft, easy to produce in plastic wire scribing, diamond particles is easy to stick the knife package on the knife cutting ability lost, such knife out wafer will collapse caused by the lack of electrical failure. in addition, plastic wire produced when cutting more and some will stick to the front of the wafer bond pad (bonding pad) wire bonders cause problems, its die bond (die bonding) process requirements are relatively stringent conditions, uniformity of die bond (die bonding) and a pressure sufficient to lower the pressure of the wafer (die) gold completely stuck on the upper die (die) below is pasted inside the film F0W while ensuring the upper wafer (die) level degree. 发明内容 SUMMARY

[0003] 本发明为了解决现有技术F0W胶膜用料昂贵,工艺条件要求高的问题,本发明提供了通过增加间隔层降低封装成本和封装工艺难度,且间隔层所用DAF胶层硬度高于F0W 胶层,使得划片方便的应用方法。 [0003] In order to solve the prior art F0W expensive film materials, the process conditions require high problems, the present invention provides a spacer layer by increasing packaging cost reduction and assembly process more difficult, and the spacer layer with the adhesive layer is harder than DAF F0W layer, so that convenient application methods dicing.

[0004] 本发明的具体技术方案为:间隔层在堆叠晶粒封装的应用方法,包括多个堆叠的晶粒,其放置在基板上,所述多个堆叠的晶粒的底面贴有DAF胶膜,所述多个堆叠的晶粒之间贴有F0W胶膜,所述多个堆叠的晶粒之间使用间隔层取代F0W胶膜,间隔层使用在贴有DAF胶膜的硅晶圆上,所述间隔层取代F0W胶膜三个流程,其依次为晶圆减薄、减薄后贴DAF 胶膜、划片; [0004] The specific technical solution of the present invention is: a method in the application of spacer layer stacked die package, comprising a plurality of stacked grains, which is placed on a substrate, the bottom surface of the plurality of stacked die affixed with glue DAF film, the film F0W plurality affixed between the stacked die, using a substituted F0W spacer layer between said plurality of stacked film grain, using a spacer layer on a silicon wafer film affixed DAF the spacer layer three substituents F0W film process, which in turn is a wafer thinning, thinning the film DAF paste, scribing;

[0005] 其具体包括六个步骤: [0005] which comprises six steps:

[0006] 步骤一、准备间隔层:即纯硅晶圆减薄到所需厚度,背面贴DAF胶膜,经划片制程切成所需大小的方块; [0006] Step a, to prepare the spacer layer: i.e. pure silicon wafer is thinned to a desired thickness, DAF affixed to the back film, by a dicing process diced desired size;

[0007] 步骤二、在基板上先贴第一层产品晶粒; [0007] Step two, the first layer on the substrate to product attached to the grain;

[0008] 步骤三、将间隔层贴在第一层晶粒上; [0008] Step three, the spacer layer affixed to the first layer die;

[0009] 步骤四、将步骤三完成的材料烘烤后,对第一层硅晶粒焊线; [0009] Step 4 Step Three complete after baking material, a first layer of silicon grains bonding wires;

[0010] 步骤五、将步骤四完成材料,返回固晶工序贴第二层晶粒; [0010] Step 5 Step Four complete the material returns to step posted solid crystal grains of the second layer;

[0011] 步骤六、将步骤四完成材料烘烤后,对第二层晶粒焊线,堆叠完成。 After [0011] Step six, four MATERIALS baking step, the second layer of the die bonding wire, to complete the stack.

[0012] 本发明的技术效果:本发明的间隔层在堆叠晶粒封装的应用方法,通过增加间隔层,降低封装成本和封装工艺难度,且间隔层所用DAF胶膜比F0W胶膜硬,使得划片方便。 [0012] Technical effects of the invention: the spacer layer applied in the method of the present invention is a stacked die package, by increasing the spacer layer, reducing the package cost and the difficulty of packaging process, and the spacer layer film used DAF than F0W hard film, such dicing convenient. 附图说明 BRIEF DESCRIPTION

[0013] 图1是本发明实施例的F0W胶膜叠加两个晶粒方式截面的横截面示意图。 [0013] FIG. 1 is a F0W film of the present invention is an embodiment in cross section of a superposition of two crystal grains schematic cross-section.

[0014] 图2是本发明实施例的间隔层叠加两个晶圆方式截面示意图。 [0014] FIG. 2 is a schematic sectional view of the two wafers spacer layer is superposed by way of example of the present invention.

[0015] 图3是本发明实施例的F0W堆叠流程示意图。 [0015] FIG. 3 is a flow diagram of one embodiment F0W stack of the present invention.

[0016] 图4是本发明实施例的间隔层堆叠流程示意图。 [0016] FIG. 4 is a spacer layer stack of the present invention, the procedure of Example FIG.

[0017] 图5是本发明实施例的步骤一示意图。 [0017] The procedure of Example 5 is a schematic diagram of the present invention.

[0018] 图6是本发明实施例的步骤二示意图。 [0018] FIG. 6 is a step of an embodiment of the present invention is a schematic view of two.

[0019] 图7是本发明实施例的步骤三示意图。 [0019] FIG. 7 is a step of an embodiment of the present invention is a schematic view of three.

[0020] 图8是本发明实施例的步骤四示意图。 [0020] FIG. 8 is a step of an embodiment of the present invention is a schematic view of four.

[0021] 图9是本发明实施例的步骤五示意图。 [0021] FIG. 9 is a step of an embodiment of the present invention is a schematic view of five.

[0022] 图10是本发明实施例的步骤六示意图。 [0022] FIG. 10 is a schematic view of the steps of the six embodiment of the present invention.

[0023] 图11是本发明实施例运用在其它结构中的示意图。 [0023] FIG. 11 is a schematic diagram of the structure used in other embodiments of the present invention.

[0024] 图中,晶粒1,第一晶粒2,第二晶粒20,F0W胶膜3,DAF胶膜4,间隔层5,基板6, 金线线弧7,划片后的娃晶圆8。 [0024] FIG, 1 die, the first die 2, the second die 20, F0W film 3, DAF film 4, a spacer layer 5, a substrate 6, a gold wire arc line 7, the baby after dicing wafer 8. 具体实施方式 Detailed ways

[0025] 下面结合附图对本发明做进一步说明。 [0025] DRAWINGS The present invention is further described.

[0026] 如图1和图2所示,使用间隔层5取代F0W胶膜6,间隔层5使用贴DAF胶膜4的硅晶圆8,比如75um厚的F0W胶膜层可以使用50um厚背面贴10um厚的DAF胶膜4的硅晶粒取代,这样增加间隔层的减薄,划片和固晶(die bond)工序,但是,其取代了F0W胶膜,降低了工艺难度。 [0026] FIGS. 1 and 2, the spacer layer 5 using a substituted F0W film 6, the spacer layer 5 using the silicon film 84 affixed to the DAF, such F0W 75um thick film layer may be 50um thick back surface 10um thick film paste DAF silicon grains 4 substituents, thus increasing the spacer layer thinning, dicing and die bonding (die bond) step, however, it is substituted F0W the film, reducing the difficulty of the process. 如图1所示,使用75um厚的F0W胶膜,第一晶粒2的焊接的金线线弧7可以陷入F0W胶膜6;如图2使用间隔层5,焊线边比第一晶圆,第二晶圆短最多为250um,给第一晶圆和第二晶圆之间撑起一个空间,第二晶粒在作业时,不会压到第一晶圆的金线线弧7。 1, the use of thick 75um F0W film, a first welding die 2 a gold wire into a wire loop 7 may F0W film 6; using the spacer layer 5 in FIG. 2, wire side than the first wafer , most short 250um second wafer, a second wafer between the first wafer and the hold up a space, the second die when the work will not be pressed against the first wafer gold wire loop 7.

[0027] 如图3和图4所示,包括晶圆,烘烤,晶圆焊线,晶圆,烘烤,晶圆焊线,注塑,所述晶圆背面贴有F0W贴膜,其放置在基板上,所述间隔层取代F0W胶膜三个流程,其依次为硅晶圆减薄、减薄后贴DAF胶膜、划片; [0027] As shown in FIG. 3 and FIG. 4, includes a wafer, baked wafer bonding wires, wafer baking, the wafer backside wire, injection molded, the wafer affixed F0W film, placed in on a substrate, said spacer layer three substituents F0W film process, which in turn is thinned silicon wafer after thinning DAF film paste, scribing;

[0028] 如图5至图10所示,间隔层在堆叠晶粒封装的应用方法具体的实施步骤如下: [0028] As shown in FIG. 5 to FIG. 10, a spacer layer stacked die packages in the application of the method specific embodiment the following steps:

[0029] 步骤一、准备间隔层:即硅晶圆减薄到所需厚度,背面贴DAF胶膜,然后经划片制程切成所需大小的方块(如图一); [0029] Step a, to prepare the spacer layer: the silicon wafer is thinned to a desired thickness, DAF affixed to the back film, and then by dicing process block size (Figure 1) cut into desired;

[0030] 步骤二、基板上先贴第一层产品晶粒(如图二); [0030] Step two, the first layer on the substrate to product attached to the grain (Figure 2);

[0031] 步骤三、将间隔层贴在第一层晶粒上(如图三); [0031] Step three, the spacer layer affixed to the first layer die (Figure 3);

[0032] 步骤四、将第三步完成的材料烘烤后,对第一层晶粒焊线(如图四); After [0032] Step four, the third step to complete the curing material, a first layer of grains bonding wire (Figure IV);

[0033] 步骤五、将步骤四完成材料返回固晶工序,贴第二层晶粒(如图五); [0033] Step 5 Step Four complete the solid crystal material to return step, the second paste layer die (FIG. V);

[0034] 步骤六、将步骤四完成材料烘烤后,对第二层晶圆焊线,堆叠完成(如图六)。 After [0034] Step six, four MATERIALS baking step, the wafer bonding wire of the second layer stack is completed (FIG. VI).

[0035] 如图11所示,多个晶圆的堆叠,除了从上到下的整齐的叠加方式外,还可以使用其它的叠加方式,如来回阶梯堆叠。 [0035] 11, a plurality of wafers stacked in a superimposed manner in addition to neat from top to bottom, is also possible to use other superimposed manner, such as a stack back and forth step.

[0036] 本发明的间隔层在堆叠晶粒封装的应用方法,,通过增加Spacer降低封装成本和封装工艺难度,而且间隔层所用DAF硬度比F0W胶层强,使得划片方便。 [0036] The spacer layer applied in the method of the present invention is a stacked die package ,, Spacer by increasing packaging cost reduction and assembly process difficult, and the hardness of the spacer layer is stronger than DAF F0W with glue, so that the dicing convenient. 需要指出的是,上述较佳实施例仅为说明本发明的技术构思及特点,其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施,并不能以此限制本发明的保护范围。 It should be noted that the above described preferred embodiments are merely technical concept and features of the invention, its object is to allow those skilled in the art to understand the present invention and accordingly embodiment, and thus does not limit the present invention protected range. 凡根据本发明精神实质所作的等效变化或修饰,都应涵盖在本发明的保护范围之内。 Where an equivalent changes or modifications made from the spirit of the present invention, shall fall within the scope of the present invention.

Claims (1)

1.间隔层在堆叠晶粒封装的应用方法,包括多个堆叠的晶粒,其放置在基板上,所述多个堆叠的晶粒的底面贴有DAF胶膜,所述多个堆叠的晶粒之间贴有一层有FOW胶膜,其特征在于:所述多个堆叠的晶粒之间使用间隔层取代FOW胶膜,间隔层使用在贴有DAF胶膜的晶圆上,所述间隔层取代FOW胶膜三个流程,其依次为硅晶圆减薄、减薄后贴DAF胶膜、划片; 其具体包括六个步骤:步骤一、准备间隔层:即硅晶圆减薄到所需厚度,背面贴DAF胶膜,经划片制程切成所需大小的方块;步骤二、在基板上先贴第一层产品晶粒;步骤三、将间隔层贴在第一层晶圆上;步骤四、将步骤三完成的材料烘烤后,对第一层晶粒焊线;步骤五、将步骤四完成材料,返回固晶工序贴第二层晶粒;步骤六、将步骤四完成材料烘烤后,对第二层硅晶粒焊线,堆叠完成。 1. Application of the method spacer layer stacked die package, comprising a plurality of stacked grains, which is placed on a substrate, the bottom surface of the plurality of stacked die affixed DAF film, said plurality of stacked crystal covered with a thin film between the particles have FOW, wherein: using between said plurality of stacked die substituted FOW film spacer layer, the spacer layer used in the film of DAF affixed wafer, the spacer FOW substituted three layer film process, which in turn is thinned silicon wafer after thinning DAF film paste, scribing; which comprises six steps: step a, to prepare the spacer layer: the silicon wafer is thinned to desired thickness, DAF affixed to the back film, by a dicing process diced desired size; two steps, in a first layer on a substrate to product attached to the grain; step three, the spacer layer affixed to the first layer of the wafer on; step 4 step three complete after baking material, a first layer of grains bonding wire; step five, four mATERIALS step, the step returns posted solid crystal grains of the second layer; step 6 to step four after completion of the baked material, a second layer of silicon die wire bonding, the stack is completed.
CN201510074772.4A 2015-02-11 2015-02-11 Application method of spacing layer in stacked crystal grain packaging CN105990294A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030095035A (en) * 2002-06-11 2003-12-18 주식회사 칩팩코리아 Chip size stack package using resin-spacer
US20080203575A1 (en) * 2004-03-02 2008-08-28 Jochen Thomas Integrated Circuit with Re-Route Layer and Stacked Die Assembly
US20120261810A1 (en) * 2006-08-18 2012-10-18 Sang-Ho Lee Integrated circuit package system with waferscale spacer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030095035A (en) * 2002-06-11 2003-12-18 주식회사 칩팩코리아 Chip size stack package using resin-spacer
US20080203575A1 (en) * 2004-03-02 2008-08-28 Jochen Thomas Integrated Circuit with Re-Route Layer and Stacked Die Assembly
US20120261810A1 (en) * 2006-08-18 2012-10-18 Sang-Ho Lee Integrated circuit package system with waferscale spacer

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