CN105990294A - Application method of spacing layer in stacked crystal grain packaging - Google Patents
Application method of spacing layer in stacked crystal grain packaging Download PDFInfo
- Publication number
- CN105990294A CN105990294A CN201510074772.4A CN201510074772A CN105990294A CN 105990294 A CN105990294 A CN 105990294A CN 201510074772 A CN201510074772 A CN 201510074772A CN 105990294 A CN105990294 A CN 105990294A
- Authority
- CN
- China
- Prior art keywords
- crystal grain
- glued membrane
- fow
- wall
- daf
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
Abstract
The invention discloses an application method of spacing layer in stacked crystal grain packaging. The application method comprises a plurality of stacked crystal grains which are placed on a substrate, the bottom surface of each of the plurality of stacked crystal grains is attached with a DAF adhesive film, and adjacent crystal grains of the plurality of stacked crystal grains are attached with an FOW adhesive film therebetween, a spacing layer is applied to replace the FOW adhesive film between adjacent crystal grains of the plurality of stacked crystal grains, and the spacing layer is applied to the crystal gain on which the DAF adhesive film is attached. The process of replacing the FOW adhesive film with the spacing layer comprises three procedures which are silicon wafer thinning, DAF adhesive film attaching after silicon wafer thinning and scribing in sequence. Through the technical scheme disclosed by the invention, the spacing layer is additionally arranged, and the packaging cost and the packaging process difficulty are reduced. In addition, the DAF film adopted by the spacing layer is harder than the FOW film, thereby enabling scribing to be carried out conveniently.
Description
Technical field
The invention belongs to integrated antenna package technical field, disclose wall application process in stacked die encapsulates.
Background technology
In integrated antenna package, stacked package is a kind of packing forms that IC encapsulation is very conventional, can make crystal grain of the same race (die)
Stacking, it is also possible to be the stacking of different crystal grain (die), lower floor to be avoided gold thread and upper strata crystal grain (die) when stack design
Contact generally uses FOW glued membrane (film over wire) this somewhat expensive glued membrane, and FOW glued membrane, after wafer is thinning, pastes
At wafer rear, during scribing, being cut by wafer together with FOW glued membrane, its characteristic is the softest before being heating and curing, during die bond, directly
Connecing and be pressed on the wafer (die) of lower floor's bonding wire by the crystal grain (die) posting FOW glued membrane, the gold thread of lower floor is just absorbed in FOW
Inside glued membrane.And process conditions are required the highest by expensive FOW glued membrane, owing to it is the softest, easy when scribing
Producing collodion silk, easily the diamond grains on cutter is wrapped up and loses cutting power by viscous cutter, the wafer that such cutter cuts out have collapse scarce
Cause electrical property failure, it addition, the collodion silk produced during cutting relatively many some can adhere to the bond pad (bonding wire dish) of wafer frontside
On cause bonding wire problem, die bond (die bond) process conditions is required also relatively stricter by it, die bond's (die bond)
The uniformity of pressure and pressure be enough to the making gold thread on lower floor's wafer (die) be trapped into completely below upper strata crystal grain (die) and paste
FOW glued membrane inside, the levelness on upper strata to be ensured wafer (die).
Summary of the invention
The present invention is to solve that prior art FOW glued membrane materials are expensive, process conditions require high problem, the invention provides logical
Cross increase wall and reduce packaging cost and packaging technology difficulty, and DAF glue-line hardness used by wall is higher than FOW glue-line, makes
Obtain the convenient application process of scribing.
The concrete technical scheme of the present invention is: the application process that wall encapsulates at stacked die, including the crystal grain of multiple stackings,
It is placed on substrate, and DAF glued membrane is posted in the bottom surface of the crystal grain of the plurality of stacking, posts between the crystal grain of the plurality of stacking
FOW glued membrane, uses wall to replace FOW glued membrane between the crystal grain of the plurality of stacking, wall uses and posting DAF glued membrane
Silicon Wafer on, described wall replace three flow processs of FOW glued membrane, its be followed successively by wafer thinning, thinning after patch DAF glued membrane,
Scribing；
It specifically includes six steps:
Step one, preparation wall: i.e. pure silicon wafer is thinned to desired thickness, back side patch DAF glued membrane, is cut into institute through scribing processing procedure
Need the square of size；
Step 2, on substrate, first paste ground floor product grains；
Step 3, wall is attached on ground floor crystal grain；
After the baking of step 4, the material that step 3 is completed, to ground floor silicon crystal grain bonding wire；
Step 5, step 4 is completed material, return die bond operation patch second layer crystal grain；
Step 6, step 4 is completed material baking after, to second layer crystal grain bonding wire, stacking completes.
The technique effect of the present invention: the application process that the wall of the present invention encapsulates at stacked die, by increasing wall, reduces
Packaging cost and packaging technology difficulty, and used by wall, DAF glued membrane is harder than FOW glued membrane so that scribing is convenient.
Accompanying drawing explanation
Fig. 1 is the cross sectional representation in two crystal grain mode cross sections of FOW glued membrane superposition of the embodiment of the present invention.
Fig. 2 is two wafer mode schematic cross-sections of wall superposition of the embodiment of the present invention.
Fig. 3 is that the FOW of the embodiment of the present invention stacks schematic flow sheet.
Fig. 4 is the wall stacking schematic flow sheet of the embodiment of the present invention.
Fig. 5 is step one schematic diagram of the embodiment of the present invention.
Fig. 6 is the step 2 schematic diagram of the embodiment of the present invention.
Fig. 7 is the step 3 schematic diagram of the embodiment of the present invention.
Fig. 8 is the step 4 schematic diagram of the embodiment of the present invention.
Fig. 9 is the step 5 schematic diagram of the embodiment of the present invention.
Figure 10 is the step 6 schematic diagram of the embodiment of the present invention.
Figure 11 is the schematic diagram that the embodiment of the present invention is used in other structure.
In figure, crystal grain 1, the first crystal grain 2, the second crystal grain 20, FOW glued membrane 3, DAF glued membrane 4, wall 5, substrate 6,
Gold thread bank 7, the Silicon Wafer 8 after scribing.
Detailed description of the invention
The present invention will be further described below in conjunction with the accompanying drawings.
As depicted in figs. 1 and 2, using wall 5 replacement FOW glued membrane 6, wall 5 uses the silicon wafer of patch DAF glued membrane 4
Circle 8, FOW adhesive film thick for such as 75um can use the silicon crystal grain of DAF glued membrane 4 thick for 50um thickness back side patch 10um to take
In generation, so increase wall is thinning, scribing and die bond (die bond) operation, but, that replace FOW glued membrane, fall
Low technology difficulty.As it is shown in figure 1, use FOW glued membrane thick for 75um, the gold thread bank 7 of the welding of the first crystal grain 2 is permissible
It is absorbed in FOW glued membrane 6；As Fig. 2 uses wall 5, bonding wire limit is than the first wafer, and the short up to 250um of the second wafer, to the
Propping up a space between one wafer and the second wafer, the second crystal grain, when operation, will not be pressed onto the gold thread bank 7 of the first wafer.
As shown in Figure 3 and Figure 4, including wafer, baking, wafer bonding wire, wafer, baking, wafer bonding wire, injection, described crystalline substance
FOW pad pasting is posted at the circle back side, and it is placed on substrate, and described wall replaces three flow processs of FOW glued membrane, and it is followed successively by Silicon Wafer
Patch DAF glued membrane, scribing after thinning, thinning；
As shown in Fig. 5 to Figure 10, the concrete enforcement step of application process that wall encapsulates at stacked die is as follows:
Step one, preparation wall: i.e. Silicon Wafer is thinned to desired thickness, back side patch DAF glued membrane, is then cut into through scribing processing procedure
The square (such as figure one) of required size；
Ground floor product grains (such as figure two) is first pasted on step 2, substrate；
Step 3, wall is attached on ground floor crystal grain (such as figure three)；
After the baking of step 4, the material that the 3rd step is completed, to ground floor crystal grain bonding wire (such as figure four)；
Step 5, step 4 is completed material return die bond operation, patch second layer crystal grain (such as figure five)；
Step 6, step 4 is completed material baking after, to second layer wafer bonding wire, stacked (such as figure six).
As shown in figure 11, the stacking of multiple wafers, in addition to neat stacked system from top to bottom, it is also possible to use other
Stacked system, as ladder stacks back and forth.
The application process that the wall of the present invention encapsulates at stacked die, reduce packaging cost and encapsulation work by increasing Spacer
Skill difficulty, and used by wall, DAF hardness ratio FOW glue-line is strong so that and scribing is convenient.It is pointed out that above-mentioned preferably
Embodiment is only technology design and the feature of the explanation present invention, its object is to allow person skilled in the art will appreciate that this
Bright content is also implemented according to this, can not limit the scope of the invention with this.All according to spirit of the invention made etc.
Effect change or modification, all should contain within protection scope of the present invention.
Claims (1)
1. the application process that wall encapsulates at stacked die, including the crystal grain of multiple stackings, it is placed on substrate, described many
DAF glued membrane is posted in the bottom surface of the crystal grain of individual stacking, and posting one layer between the crystal grain of the plurality of stacking has FOW glued membrane, its feature
It is: using wall to replace FOW glued membrane between the crystal grain of the plurality of stacking, wall uses at the crystalline substance posting DAF glued membrane
On circle, described wall replaces three flow processs of FOW glued membrane, and it is followed successively by Silicon Wafer rear patch thinning, thinning DAF glued membrane, scribing；
It specifically includes six steps:
Step one, preparation wall: i.e. Silicon Wafer is thinned to desired thickness, back side patch DAF glued membrane, is cut into required through scribing processing procedure
The square of size；
Step 2, on substrate, first paste ground floor product grains；
Step 3, wall is attached on ground floor wafer；
After the baking of step 4, the material that step 3 is completed, to ground floor crystal grain bonding wire；
Step 5, step 4 is completed material, return die bond operation patch second layer crystal grain；
Step 6, step 4 is completed material baking after, to second layer silicon crystal grain bonding wire, stacking completes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510074772.4A CN105990294A (en) | 2015-02-11 | 2015-02-11 | Application method of spacing layer in stacked crystal grain packaging |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510074772.4A CN105990294A (en) | 2015-02-11 | 2015-02-11 | Application method of spacing layer in stacked crystal grain packaging |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105990294A true CN105990294A (en) | 2016-10-05 |
Family
ID=57042014
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510074772.4A Pending CN105990294A (en) | 2015-02-11 | 2015-02-11 | Application method of spacing layer in stacked crystal grain packaging |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105990294A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021093408A1 (en) * | 2019-11-15 | 2021-05-20 | 天津大学 | Duplexer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030095035A (en) * | 2002-06-11 | 2003-12-18 | 주식회사 칩팩코리아 | Chip size stack package using resin-spacer |
| US20080203575A1 (en) * | 2004-03-02 | 2008-08-28 | Jochen Thomas | Integrated Circuit with Re-Route Layer and Stacked Die Assembly |
| US20120261810A1 (en) * | 2006-08-18 | 2012-10-18 | Sang-Ho Lee | Integrated circuit package system with waferscale spacer |
-
2015
- 2015-02-11 CN CN201510074772.4A patent/CN105990294A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030095035A (en) * | 2002-06-11 | 2003-12-18 | 주식회사 칩팩코리아 | Chip size stack package using resin-spacer |
| US20080203575A1 (en) * | 2004-03-02 | 2008-08-28 | Jochen Thomas | Integrated Circuit with Re-Route Layer and Stacked Die Assembly |
| US20120261810A1 (en) * | 2006-08-18 | 2012-10-18 | Sang-Ho Lee | Integrated circuit package system with waferscale spacer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021093408A1 (en) * | 2019-11-15 | 2021-05-20 | 天津大学 | Duplexer |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20161005 |