CN105990225A - Photomask optimization method used for copper/low-k interconnection structure and photomask - Google Patents
Photomask optimization method used for copper/low-k interconnection structure and photomask Download PDFInfo
- Publication number
- CN105990225A CN105990225A CN201510084491.7A CN201510084491A CN105990225A CN 105990225 A CN105990225 A CN 105990225A CN 201510084491 A CN201510084491 A CN 201510084491A CN 105990225 A CN105990225 A CN 105990225A
- Authority
- CN
- China
- Prior art keywords
- light shield
- optimization method
- copper
- interconnecting line
- line groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
Abstract
The present invention provides a photomask optimization method used for a copper/low-k interconnection structure and a photomask. The photomask optimization method includes the following steps that hole patterns which can generate a balance stress are added to the photomask patterns of copper line interconnection grooves. With the photomask optimization method used for the copper/low-k interconnection structure provided by the invention adopted, the defect of voids in the copper/low-k interconnection structure can be improved through optimizing the photomask patterns, and the change of processes such as etching or physical vapor deposition is not required.
Description
Technical field
The present invention relates to technical field of semiconductors, mutual for copper/low k in particular to one
Link light shield optimization method and the light shield of structure.
Background technology
As CMOS technology is reduced to 20 nanometer patterns and following, low k (dielectric constant)
Or Ultra low k dielectric is normally used as last part technology (BEOL) interlayer dielectric, to reduce
Resistance-capacitance (RC) time delay.When in 20 nanometers and techniques below, k is reduced to
During less than 2.0, Ultra low k dielectric more porous, and its mechanical strength is by worse, through carving
After erosion, the residual stress in the hard mask of TiN can make copper interconnecting line groove deform, and affects follow-up
Process is filled in gap.
Content of the invention
For the deficiencies in the prior art, the present invention provides a kind of for copper/low k interconnection structure
Light shield optimization method, described light shield optimization method includes in the mask pattern of copper interconnecting line groove
Interpolation can produce the poroid pattern of equilibrium stress.
In one embodiment of the invention, described light shield optimization method farther includes: putting down
Add described poroid pattern in the mask pattern of the adjacent copper interconnecting line groove of row.
In one embodiment of the invention, described light shield optimization method farther includes: three
The mask pattern of one the copper interconnecting line groove in centre in the parallel adjacent copper interconnecting line groove of bar
The described poroid pattern of upper interpolation.
In one embodiment of the invention, at described three parallel adjacent copper interconnecting line grooves
In, the length of one the copper interconnecting line groove in described centre is more than remaining two copper interconnecting line groove
Length.
In one embodiment of the invention, described poroid pattern includes multiple, each poroid figure
Distance between the size of case and each poroid pattern all meets design rule.
In one embodiment of the invention, described light shield optimization method can be used in k's < 2.0
Interconnection structure.
In one embodiment of the invention, described light shield optimization method is real when layout design
Execute.
In one embodiment of the invention, described light shield optimization method is repaiied carrying out optical adjacent
Timing is implemented.
The present invention also provides a kind of light shield for copper/low k interconnection structure, and described light shield wraps
Include the mask pattern of copper interconnecting line groove, described mask pattern includes to produce equilibrium stress
Poroid pattern.
In one embodiment of the invention, described poroid pattern is positioned at three parallel adjacent copper
In the mask pattern of one the copper interconnecting line groove in centre of interconnection line groove.
Light shield optimization method for copper/low k interconnection structure provided by the present invention can pass through
Improve the cavity blemish in copper/low k interconnection structure to the optimization of mask pattern, and be not necessarily to
The change of the processing procedures such as etching or physical vapour deposition (PVD) (PVD).
Brief description
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Attached
Figure shows embodiments of the invention and description thereof, is used for explaining the principle of the present invention.
In accompanying drawing:
Fig. 1 illustrates the example of the mask pattern of existing copper interconnecting line groove；
Fig. 2 illustrates that the copper interconnecting line groove of Fig. 1 causes deformation due to the residual stress of hard mask
Schematic diagram；
Fig. 3 illustrates that the deformation of the copper interconnecting line groove of Fig. 1 results in the schematic diagram in cavity；
Fig. 4 illustrates that poroid pattern according to embodiments of the present invention produces the schematic diagram of equilibrium stress；
Fig. 5 illustrates the example of the mask pattern of copper interconnecting line groove according to embodiments of the present invention；
And
Fig. 6 illustrates that the remnants of the hard mask of copper interconnecting line groove generation equilibrium stress antagonism of Fig. 5 should
The schematic diagram of power.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide to the present invention more
Understand thoroughly.It is, however, obvious to a person skilled in the art that the present invention
One or more of these details can be not necessarily to and be carried out.In other example, in order to keep away
Exempt to obscure with the present invention, some technical characteristics well known in the art are not described.
It it should be appreciated that the present invention can implement in different forms, and is not construed as office
It is limited to embodiments presented herein.On the contrary, it is open thorough and complete to provide these embodiments to make
Entirely, and will fully convey the scope of the invention to those skilled in the art.
The purpose of term as used herein is only that description specific embodiment and not as this
Bright restriction.When using at this, " one " of singulative, " one " and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " forms " and/or " including ", when using in this specification, determine described feature,
The existence of integer, step, operation, element and/or parts, but be not excluded for one or more its
The existence of its feature, integer, step, operation, element, parts and/or group or interpolation.
When using at this, term "and/or" includes any and all combination of related Listed Items.
In order to thoroughly understand the present invention, detailed step and in detail will be proposed in following description
Thin structure, in order to the technical scheme that the explaination present invention proposes.Presently preferred embodiments of the present invention is detailed
It is carefully described as follows, but in addition to these describe in detail, the present invention can also have other and implement
Mode.
Copper/low k interconnection structure uses copper interconnecting line and low k dielectric materials, copper interconnecting line and low k
The combination of dielectric material can be substantially reduced the RC time delay of circuit.But, due to low k
There is the shortcomings such as hardness is little, density is low, bad mechanical strength in material, can cause interconnection structure can
By sex chromosome mosaicism, in some instances it may even be possible to cause the inefficacy of interconnection structure.
Fig. 1 illustrates the example of the mask pattern of existing copper interconnecting line groove.Through photoetching and quarter
After erosion, copper interconnecting line groove owing to being deformed by the residual stress in the hard mask of TiN,
Go out as shown in Figure 2, and this problem with the reduction of dielectric k value more notable.
Due to such deformation, follow-up filling process will be affected, may be at copper interconnecting line groove
Middle formation cavity, goes out as shown in Figure 3.Such situation in the structure of MOM shape more
For seriously, when copper interconnecting line groove is adjacent with another two copper interconnecting line grooves, this copper interconnecting line
The critical size (CD) of groove is easier to therefore abnormal change occur, and forms multiple cavity.
For the problems referred to above, the present invention provides a kind of light shield for copper/low k interconnection structure excellent
Change method, this light shield optimization method includes that interpolation can in the mask pattern of copper interconnecting line groove
Producing the poroid pattern of equilibrium stress, Fig. 4 illustrates that poroid pattern according to embodiments of the present invention produces
The schematic diagram of raw equilibrium stress.
Fig. 5 illustrates the example of the mask pattern of copper interconnecting line groove according to embodiments of the present invention.
As it is shown in figure 5, add poroid figure in the mask pattern of copper interconnecting line groove as shown in Figure 1
Case, poroid pattern can produce equilibrium stress to resist the residual stress in the hard mask of TiN, just
Thus improve the problem on deformation of copper interconnecting line groove, go out as shown in Figure 6.
Specifically, can add in the mask pattern of parallel adjacent copper interconnecting line groove poroid
Pattern.Preferably, can centre one flat copper in three parallel adjacent copper interconnecting line grooves
Add poroid pattern in the mask pattern of interconnection line groove.Wherein, at three parallel adjacent copper
In interconnection line groove, the length of a middle copper interconnecting line groove can be mutual more than remaining two flat copper
The length of line groove.As mentioned above, when copper interconnecting line groove and another two copper interconnecting lines
When groove is adjacent, the critical size (CD) of this copper interconnecting line groove is easier to abnormal changing
Become, form multiple cavity.Therefore, it can the light shield emphatically for such copper interconnecting line groove
Pattern adds poroid pattern.
According to embodiments of the invention, the poroid pattern being added can include multiple, each hole
Distance between the size of shape pattern and each poroid pattern all meets design rule (Design
Rule,DR)。
As mentioned above, with the reduction of dielectric k value, copper interconnecting line groove be more easy to due to
Deformed by the residual stress in the hard mask of TiN.Therefore, above-mentioned light shield optimization method
Its advantage more can be embodied during for copper/ultralow k (such as k < 2.0) interconnection structure.
Specifically, above-mentioned light shield optimization method can be implemented when layout design, it is also possible to is entering
Implement during row optical proximity correction (Optical Proximity Correction, OPC).
The above-mentioned light shield for copper/low k interconnection structure being provided according to embodiments of the present invention is excellent
Change method can be improved the cavity in copper/low k interconnection structure by the optimization to mask pattern
Defect, and without the change of etching or the processing procedures such as physical vapour deposition (PVD), also will not to through when hit
Wear (Time-Dependent Dielectric Breakdown, TDDB) and produce impact.
Based on the above-mentioned light shield optimization method for copper/low k interconnection structure, the present invention also provides
A kind of light shield for copper/low k interconnection structure, this light shield includes the light of copper interconnecting line groove
Cover pattern, mask pattern includes the poroid pattern that can produce equilibrium stress.Specifically, hole
Shape pattern may be located at centre one copper interconnecting line of three parallel adjacent copper interconnecting line grooves
In the mask pattern of groove.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-mentioned
Embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that the present invention not office
It is limited to above-described embodiment, more kinds of modification can also be made according to the teachings of the present invention and repair
Change, within these variants and modifications all fall within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and equivalent scope thereof.
Claims (10)
1. the light shield optimization method for copper/low k interconnection structure, it is characterised in that institute
State light shield optimization method and include that interpolation can produce flat in the mask pattern of copper interconnecting line groove
The poroid pattern of weighing apparatus stress.
2. light shield optimization method as claimed in claim 1, it is characterised in that described light shield
Optimization method farther includes: add in the mask pattern of parallel adjacent copper interconnecting line groove
Described poroid pattern.
3. light shield optimization method as claimed in claim 2, it is characterised in that described light shield
Optimization method farther includes: the centre one in three parallel adjacent copper interconnecting line grooves
Add described poroid pattern in the mask pattern of copper interconnecting line groove.
4. light shield optimization method as claimed in claim 3, it is characterised in that described three
In the parallel adjacent copper interconnecting line groove of bar, the length of one the copper interconnecting line groove in described centre is big
Length in remaining two copper interconnecting line groove.
5. the light shield optimization method as described in any one in claim 1-4, its feature exists
In described poroid pattern includes multiple, the size of each poroid pattern and each poroid pattern
Between distance all meet design rule.
6. the light shield optimization method as described in any one in claim 1-4, its feature exists
In described light shield optimization method can be used in the interconnection structure of k < 2.0.
7. the light shield optimization method as described in any one in claim 1-4, its feature exists
In described light shield optimization method is implemented when layout design.
8. the light shield optimization method as described in any one in claim 1-4, its feature exists
In described light shield optimization method enforcement when carrying out optical proximity correction.
9. the light shield for copper/low k interconnection structure, it is characterised in that on described light shield
Including the mask pattern of copper interconnecting line groove, described mask pattern including can produce balance should
The poroid pattern of power.
10. such as the light shield in claim 9, it is characterised in that described poroid pattern is positioned at three
In the mask pattern of one the copper interconnecting line groove in centre of the parallel adjacent copper interconnecting line groove of bar.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510084491.7A CN105990225B (en) | 2015-02-16 | 2015-02-16 | For copper/low k interconnection structure light shield optimization method and light shield |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510084491.7A CN105990225B (en) | 2015-02-16 | 2015-02-16 | For copper/low k interconnection structure light shield optimization method and light shield |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105990225A true CN105990225A (en) | 2016-10-05 |
| CN105990225B CN105990225B (en) | 2019-04-09 |
Family
ID=57038472
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510084491.7A Active CN105990225B (en) | 2015-02-16 | 2015-02-16 | For copper/low k interconnection structure light shield optimization method and light shield |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105990225B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6109775A (en) * | 1991-07-19 | 2000-08-29 | Lsi Logic Corporation | Method for adjusting the density of lines and contact openings across a substrate region for improving the chemical-mechanical polishing of a thin-film later disposed thereon |
| US20080128924A1 (en) * | 2006-12-05 | 2008-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device Having In-Chip Critical Dimension and Focus Patterns |
| US20120149204A1 (en) * | 2010-12-13 | 2012-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming via holes |
-
2015
- 2015-02-16 CN CN201510084491.7A patent/CN105990225B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6109775A (en) * | 1991-07-19 | 2000-08-29 | Lsi Logic Corporation | Method for adjusting the density of lines and contact openings across a substrate region for improving the chemical-mechanical polishing of a thin-film later disposed thereon |
| US20080128924A1 (en) * | 2006-12-05 | 2008-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device Having In-Chip Critical Dimension and Focus Patterns |
| US20120149204A1 (en) * | 2010-12-13 | 2012-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming via holes |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105990225B (en) | 2019-04-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11138359B2 (en) | Method of fabricating a semiconductor device | |
| KR101911646B1 (en) | System for and method of manufacturing a layout design of an integrated circuit | |
| US11288429B2 (en) | Electrical mask validation | |
| CN102364480A (en) | Method and system for extracting parasitic parameter | |
| CN105990225A (en) | Photomask optimization method used for copper/low-k interconnection structure and photomask | |
| JP2017521871A5 (en) | ||
| CN105843976A (en) | Dummy fill method for modified chip design | |
| US8082536B2 (en) | Semiconductor integrated circuit manufacturing process evaluation method | |
| CN106033172B (en) | Method for optical proximity correction repair | |
| US20150097249A1 (en) | Cross coupling gate using mulitple patterning | |
| CN104063566A (en) | Method for determining degrees of importance of elements in electrical system under influences of two factors | |
| JP2010140276A (en) | Polishing prediction evaluation device, polishing prediction evaluating method, polishing prediction evaluation program | |
| JP6089723B2 (en) | Design method and design program | |
| Wang et al. | Capacitance calculation for a shared-antipad via structure using an integral equation method based on partial capacitance | |
| JP2013037413A (en) | Circuit layout device, processing method and program | |
| WO2010088141A3 (en) | Method and system for sizing polygons in an integrated circuit (ic) layout | |
| Rabie et al. | Optimization of Through Crackstop via using finite element modeling | |
| KR102344709B1 (en) | Two-dimensional via pillar structures | |
| US20210073457A1 (en) | Circuit design device, circuit design method, and storage medium | |
| CN108776294B (en) | Circuit board service life evaluation method based on self-adaptive strategy | |
| James | Design-for-manufacturing features in nanometer logic processes-a reverse engineering perspective | |
| CN103091969A (en) | Optical proximity effect correction method for opposite wire ends or nearly opposite wire ends | |
| Shoji et al. | Practical use of the repeating patterns in mask writing | |
| US20120273950A1 (en) | Integrated circuit structure including copper-aluminum interconnect and method for fabricating the same | |
| CN106229291A (en) | Semiconductor manufacturing process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |